1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 252 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 status = "disabled"; 255 }; 256 257 sdmmc2: sdhci@3420000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03420000 0x0 0x10000>; 260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 264 reset-names = "sdhci"; 265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 266 pinctrl-0 = <&sdmmc2_3v3>; 267 pinctrl-1 = <&sdmmc2_1v8>; 268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 272 nvidia,default-tap = <0x5>; 273 nvidia,default-trim = <0xb>; 274 status = "disabled"; 275 }; 276 277 sdmmc3: sdhci@3440000 { 278 compatible = "nvidia,tegra186-sdhci"; 279 reg = <0x0 0x03440000 0x0 0x10000>; 280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 282 clock-names = "sdhci"; 283 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 284 reset-names = "sdhci"; 285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 286 pinctrl-0 = <&sdmmc3_3v3>; 287 pinctrl-1 = <&sdmmc3_1v8>; 288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 294 nvidia,default-tap = <0x5>; 295 nvidia,default-trim = <0xb>; 296 status = "disabled"; 297 }; 298 299 sdmmc4: sdhci@3460000 { 300 compatible = "nvidia,tegra186-sdhci"; 301 reg = <0x0 0x03460000 0x0 0x10000>; 302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 304 clock-names = "sdhci"; 305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 306 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 308 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 309 reset-names = "sdhci"; 310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 314 nvidia,default-tap = <0x5>; 315 nvidia,default-trim = <0x9>; 316 status = "disabled"; 317 }; 318 319 fuse@3820000 { 320 compatible = "nvidia,tegra186-efuse"; 321 reg = <0x0 0x03820000 0x0 0x10000>; 322 clocks = <&bpmp TEGRA186_CLK_FUSE>; 323 clock-names = "fuse"; 324 }; 325 326 gic: interrupt-controller@3881000 { 327 compatible = "arm,gic-400"; 328 #interrupt-cells = <3>; 329 interrupt-controller; 330 reg = <0x0 0x03881000 0x0 0x1000>, 331 <0x0 0x03882000 0x0 0x2000>; 332 interrupts = <GIC_PPI 9 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 334 interrupt-parent = <&gic>; 335 }; 336 337 hsp_top0: hsp@3c00000 { 338 compatible = "nvidia,tegra186-hsp"; 339 reg = <0x0 0x03c00000 0x0 0xa0000>; 340 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 341 interrupt-names = "doorbell"; 342 #mbox-cells = <2>; 343 status = "disabled"; 344 }; 345 346 gen2_i2c: i2c@c240000 { 347 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 348 reg = <0x0 0x0c240000 0x0 0x10000>; 349 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clocks = <&bpmp TEGRA186_CLK_I2C2>; 353 clock-names = "div-clk"; 354 resets = <&bpmp TEGRA186_RESET_I2C2>; 355 reset-names = "i2c"; 356 status = "disabled"; 357 }; 358 359 gen8_i2c: i2c@c250000 { 360 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 361 reg = <0x0 0x0c250000 0x0 0x10000>; 362 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 clocks = <&bpmp TEGRA186_CLK_I2C8>; 366 clock-names = "div-clk"; 367 resets = <&bpmp TEGRA186_RESET_I2C8>; 368 reset-names = "i2c"; 369 status = "disabled"; 370 }; 371 372 uartc: serial@c280000 { 373 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 374 reg = <0x0 0x0c280000 0x0 0x40>; 375 reg-shift = <2>; 376 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&bpmp TEGRA186_CLK_UARTC>; 378 clock-names = "serial"; 379 resets = <&bpmp TEGRA186_RESET_UARTC>; 380 reset-names = "serial"; 381 status = "disabled"; 382 }; 383 384 uartg: serial@c290000 { 385 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 386 reg = <0x0 0x0c290000 0x0 0x40>; 387 reg-shift = <2>; 388 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&bpmp TEGRA186_CLK_UARTG>; 390 clock-names = "serial"; 391 resets = <&bpmp TEGRA186_RESET_UARTG>; 392 reset-names = "serial"; 393 status = "disabled"; 394 }; 395 396 gpio_aon: gpio@c2f0000 { 397 compatible = "nvidia,tegra186-gpio-aon"; 398 reg-names = "security", "gpio"; 399 reg = <0x0 0xc2f0000 0x0 0x1000>, 400 <0x0 0xc2f1000 0x0 0x1000>; 401 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 408 pmc@c360000 { 409 compatible = "nvidia,tegra186-pmc"; 410 reg = <0 0x0c360000 0 0x10000>, 411 <0 0x0c370000 0 0x10000>, 412 <0 0x0c380000 0 0x10000>, 413 <0 0x0c390000 0 0x10000>; 414 reg-names = "pmc", "wake", "aotag", "scratch"; 415 416 sdmmc1_3v3: sdmmc1-3v3 { 417 pins = "sdmmc1-hv"; 418 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 419 }; 420 421 sdmmc1_1v8: sdmmc1-1v8 { 422 pins = "sdmmc1-hv"; 423 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 424 }; 425 426 sdmmc2_3v3: sdmmc2-3v3 { 427 pins = "sdmmc2-hv"; 428 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 429 }; 430 431 sdmmc2_1v8: sdmmc2-1v8 { 432 pins = "sdmmc2-hv"; 433 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 434 }; 435 436 sdmmc3_3v3: sdmmc3-3v3 { 437 pins = "sdmmc3-hv"; 438 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 439 }; 440 441 sdmmc3_1v8: sdmmc3-1v8 { 442 pins = "sdmmc3-hv"; 443 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 444 }; 445 }; 446 447 ccplex@e000000 { 448 compatible = "nvidia,tegra186-ccplex-cluster"; 449 reg = <0x0 0x0e000000 0x0 0x3fffff>; 450 451 nvidia,bpmp = <&bpmp>; 452 }; 453 454 pcie@10003000 { 455 compatible = "nvidia,tegra186-pcie"; 456 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 457 device_type = "pci"; 458 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 459 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 460 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 461 reg-names = "pads", "afi", "cs"; 462 463 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 464 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 465 interrupt-names = "intr", "msi"; 466 467 #interrupt-cells = <1>; 468 interrupt-map-mask = <0 0 0 0>; 469 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 470 471 bus-range = <0x00 0xff>; 472 #address-cells = <3>; 473 #size-cells = <2>; 474 475 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 476 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 477 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 478 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 479 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 480 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 481 482 clocks = <&bpmp TEGRA186_CLK_AFI>, 483 <&bpmp TEGRA186_CLK_PCIE>, 484 <&bpmp TEGRA186_CLK_PLLE>; 485 clock-names = "afi", "pex", "pll_e"; 486 487 resets = <&bpmp TEGRA186_RESET_AFI>, 488 <&bpmp TEGRA186_RESET_PCIE>, 489 <&bpmp TEGRA186_RESET_PCIEXCLK>; 490 reset-names = "afi", "pex", "pcie_x"; 491 492 status = "disabled"; 493 494 pci@1,0 { 495 device_type = "pci"; 496 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 497 reg = <0x000800 0 0 0 0>; 498 status = "disabled"; 499 500 #address-cells = <3>; 501 #size-cells = <2>; 502 ranges; 503 504 nvidia,num-lanes = <2>; 505 }; 506 507 pci@2,0 { 508 device_type = "pci"; 509 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 510 reg = <0x001000 0 0 0 0>; 511 status = "disabled"; 512 513 #address-cells = <3>; 514 #size-cells = <2>; 515 ranges; 516 517 nvidia,num-lanes = <1>; 518 }; 519 520 pci@3,0 { 521 device_type = "pci"; 522 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 523 reg = <0x001800 0 0 0 0>; 524 status = "disabled"; 525 526 #address-cells = <3>; 527 #size-cells = <2>; 528 ranges; 529 530 nvidia,num-lanes = <1>; 531 }; 532 }; 533 534 smmu: iommu@12000000 { 535 compatible = "arm,mmu-500"; 536 reg = <0 0x12000000 0 0x800000>; 537 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 602 stream-match-mask = <0x7f80>; 603 #global-interrupts = <1>; 604 #iommu-cells = <1>; 605 }; 606 607 host1x@13e00000 { 608 compatible = "nvidia,tegra186-host1x", "simple-bus"; 609 reg = <0x0 0x13e00000 0x0 0x10000>, 610 <0x0 0x13e10000 0x0 0x10000>; 611 reg-names = "hypervisor", "vm"; 612 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 615 clock-names = "host1x"; 616 resets = <&bpmp TEGRA186_RESET_HOST1X>; 617 reset-names = "host1x"; 618 619 #address-cells = <1>; 620 #size-cells = <1>; 621 622 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 623 iommus = <&smmu TEGRA186_SID_HOST1X>; 624 625 dpaux1: dpaux@15040000 { 626 compatible = "nvidia,tegra186-dpaux"; 627 reg = <0x15040000 0x10000>; 628 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 630 <&bpmp TEGRA186_CLK_PLLDP>; 631 clock-names = "dpaux", "parent"; 632 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 633 reset-names = "dpaux"; 634 status = "disabled"; 635 636 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 637 638 state_dpaux1_aux: pinmux-aux { 639 groups = "dpaux-io"; 640 function = "aux"; 641 }; 642 643 state_dpaux1_i2c: pinmux-i2c { 644 groups = "dpaux-io"; 645 function = "i2c"; 646 }; 647 648 state_dpaux1_off: pinmux-off { 649 groups = "dpaux-io"; 650 function = "off"; 651 }; 652 653 i2c-bus { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 }; 657 }; 658 659 display-hub@15200000 { 660 compatible = "nvidia,tegra186-display", "simple-bus"; 661 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 662 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 663 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 664 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 665 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 666 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 667 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 668 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 669 "wgrp3", "wgrp4", "wgrp5"; 670 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 671 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 672 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 673 clock-names = "disp", "dsc", "hub"; 674 status = "disabled"; 675 676 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 677 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 ranges = <0x15200000 0x15200000 0x40000>; 682 683 display@15200000 { 684 compatible = "nvidia,tegra186-dc"; 685 reg = <0x15200000 0x10000>; 686 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 688 clock-names = "dc"; 689 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 690 reset-names = "dc"; 691 692 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 693 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 694 695 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 696 nvidia,head = <0>; 697 }; 698 699 display@15210000 { 700 compatible = "nvidia,tegra186-dc"; 701 reg = <0x15210000 0x10000>; 702 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 704 clock-names = "dc"; 705 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 706 reset-names = "dc"; 707 708 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 709 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 710 711 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 712 nvidia,head = <1>; 713 }; 714 715 display@15220000 { 716 compatible = "nvidia,tegra186-dc"; 717 reg = <0x15220000 0x10000>; 718 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 720 clock-names = "dc"; 721 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 722 reset-names = "dc"; 723 724 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 725 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 726 727 nvidia,outputs = <&sor0 &sor1>; 728 nvidia,head = <2>; 729 }; 730 }; 731 732 dsia: dsi@15300000 { 733 compatible = "nvidia,tegra186-dsi"; 734 reg = <0x15300000 0x10000>; 735 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&bpmp TEGRA186_CLK_DSI>, 737 <&bpmp TEGRA186_CLK_DSIA_LP>, 738 <&bpmp TEGRA186_CLK_PLLD>; 739 clock-names = "dsi", "lp", "parent"; 740 resets = <&bpmp TEGRA186_RESET_DSI>; 741 reset-names = "dsi"; 742 status = "disabled"; 743 744 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 745 }; 746 747 vic@15340000 { 748 compatible = "nvidia,tegra186-vic"; 749 reg = <0x15340000 0x40000>; 750 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&bpmp TEGRA186_CLK_VIC>; 752 clock-names = "vic"; 753 resets = <&bpmp TEGRA186_RESET_VIC>; 754 reset-names = "vic"; 755 756 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 757 }; 758 759 dsib: dsi@15400000 { 760 compatible = "nvidia,tegra186-dsi"; 761 reg = <0x15400000 0x10000>; 762 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&bpmp TEGRA186_CLK_DSIB>, 764 <&bpmp TEGRA186_CLK_DSIB_LP>, 765 <&bpmp TEGRA186_CLK_PLLD>; 766 clock-names = "dsi", "lp", "parent"; 767 resets = <&bpmp TEGRA186_RESET_DSIB>; 768 reset-names = "dsi"; 769 status = "disabled"; 770 771 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 772 }; 773 774 sor0: sor@15540000 { 775 compatible = "nvidia,tegra186-sor"; 776 reg = <0x15540000 0x10000>; 777 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&bpmp TEGRA186_CLK_SOR0>, 779 <&bpmp TEGRA186_CLK_SOR0_OUT>, 780 <&bpmp TEGRA186_CLK_PLLD2>, 781 <&bpmp TEGRA186_CLK_PLLDP>, 782 <&bpmp TEGRA186_CLK_SOR_SAFE>, 783 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 784 clock-names = "sor", "out", "parent", "dp", "safe", 785 "pad"; 786 resets = <&bpmp TEGRA186_RESET_SOR0>; 787 reset-names = "sor"; 788 pinctrl-0 = <&state_dpaux_aux>; 789 pinctrl-1 = <&state_dpaux_i2c>; 790 pinctrl-2 = <&state_dpaux_off>; 791 pinctrl-names = "aux", "i2c", "off"; 792 status = "disabled"; 793 794 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 795 nvidia,interface = <0>; 796 }; 797 798 sor1: sor@15580000 { 799 compatible = "nvidia,tegra186-sor1"; 800 reg = <0x15580000 0x10000>; 801 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&bpmp TEGRA186_CLK_SOR1>, 803 <&bpmp TEGRA186_CLK_SOR1_OUT>, 804 <&bpmp TEGRA186_CLK_PLLD3>, 805 <&bpmp TEGRA186_CLK_PLLDP>, 806 <&bpmp TEGRA186_CLK_SOR_SAFE>, 807 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 808 clock-names = "sor", "out", "parent", "dp", "safe", 809 "pad"; 810 resets = <&bpmp TEGRA186_RESET_SOR1>; 811 reset-names = "sor"; 812 pinctrl-0 = <&state_dpaux1_aux>; 813 pinctrl-1 = <&state_dpaux1_i2c>; 814 pinctrl-2 = <&state_dpaux1_off>; 815 pinctrl-names = "aux", "i2c", "off"; 816 status = "disabled"; 817 818 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 819 nvidia,interface = <1>; 820 }; 821 822 dpaux: dpaux@155c0000 { 823 compatible = "nvidia,tegra186-dpaux"; 824 reg = <0x155c0000 0x10000>; 825 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 827 <&bpmp TEGRA186_CLK_PLLDP>; 828 clock-names = "dpaux", "parent"; 829 resets = <&bpmp TEGRA186_RESET_DPAUX>; 830 reset-names = "dpaux"; 831 status = "disabled"; 832 833 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 834 835 state_dpaux_aux: pinmux-aux { 836 groups = "dpaux-io"; 837 function = "aux"; 838 }; 839 840 state_dpaux_i2c: pinmux-i2c { 841 groups = "dpaux-io"; 842 function = "i2c"; 843 }; 844 845 state_dpaux_off: pinmux-off { 846 groups = "dpaux-io"; 847 function = "off"; 848 }; 849 850 i2c-bus { 851 #address-cells = <1>; 852 #size-cells = <0>; 853 }; 854 }; 855 856 padctl@15880000 { 857 compatible = "nvidia,tegra186-dsi-padctl"; 858 reg = <0x15880000 0x10000>; 859 resets = <&bpmp TEGRA186_RESET_DSI>; 860 reset-names = "dsi"; 861 status = "disabled"; 862 }; 863 864 dsic: dsi@15900000 { 865 compatible = "nvidia,tegra186-dsi"; 866 reg = <0x15900000 0x10000>; 867 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&bpmp TEGRA186_CLK_DSIC>, 869 <&bpmp TEGRA186_CLK_DSIC_LP>, 870 <&bpmp TEGRA186_CLK_PLLD>; 871 clock-names = "dsi", "lp", "parent"; 872 resets = <&bpmp TEGRA186_RESET_DSIC>; 873 reset-names = "dsi"; 874 status = "disabled"; 875 876 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 877 }; 878 879 dsid: dsi@15940000 { 880 compatible = "nvidia,tegra186-dsi"; 881 reg = <0x15940000 0x10000>; 882 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&bpmp TEGRA186_CLK_DSID>, 884 <&bpmp TEGRA186_CLK_DSID_LP>, 885 <&bpmp TEGRA186_CLK_PLLD>; 886 clock-names = "dsi", "lp", "parent"; 887 resets = <&bpmp TEGRA186_RESET_DSID>; 888 reset-names = "dsi"; 889 status = "disabled"; 890 891 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 892 }; 893 }; 894 895 gpu@17000000 { 896 compatible = "nvidia,gp10b"; 897 reg = <0x0 0x17000000 0x0 0x1000000>, 898 <0x0 0x18000000 0x0 0x1000000>; 899 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 900 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 901 interrupt-names = "stall", "nonstall"; 902 903 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 904 <&bpmp TEGRA186_CLK_GPU>; 905 clock-names = "gpu", "pwr"; 906 resets = <&bpmp TEGRA186_RESET_GPU>; 907 reset-names = "gpu"; 908 status = "disabled"; 909 910 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 911 }; 912 913 sysram@30000000 { 914 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 915 reg = <0x0 0x30000000 0x0 0x50000>; 916 #address-cells = <2>; 917 #size-cells = <2>; 918 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 919 920 cpu_bpmp_tx: shmem@4e000 { 921 compatible = "nvidia,tegra186-bpmp-shmem"; 922 reg = <0x0 0x4e000 0x0 0x1000>; 923 label = "cpu-bpmp-tx"; 924 pool; 925 }; 926 927 cpu_bpmp_rx: shmem@4f000 { 928 compatible = "nvidia,tegra186-bpmp-shmem"; 929 reg = <0x0 0x4f000 0x0 0x1000>; 930 label = "cpu-bpmp-rx"; 931 pool; 932 }; 933 }; 934 935 cpus { 936 #address-cells = <1>; 937 #size-cells = <0>; 938 939 cpu@0 { 940 compatible = "nvidia,tegra186-denver", "arm,armv8"; 941 device_type = "cpu"; 942 reg = <0x000>; 943 }; 944 945 cpu@1 { 946 compatible = "nvidia,tegra186-denver", "arm,armv8"; 947 device_type = "cpu"; 948 reg = <0x001>; 949 }; 950 951 cpu@2 { 952 compatible = "arm,cortex-a57", "arm,armv8"; 953 device_type = "cpu"; 954 reg = <0x100>; 955 }; 956 957 cpu@3 { 958 compatible = "arm,cortex-a57", "arm,armv8"; 959 device_type = "cpu"; 960 reg = <0x101>; 961 }; 962 963 cpu@4 { 964 compatible = "arm,cortex-a57", "arm,armv8"; 965 device_type = "cpu"; 966 reg = <0x102>; 967 }; 968 969 cpu@5 { 970 compatible = "arm,cortex-a57", "arm,armv8"; 971 device_type = "cpu"; 972 reg = <0x103>; 973 }; 974 }; 975 976 bpmp: bpmp { 977 compatible = "nvidia,tegra186-bpmp"; 978 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 979 TEGRA_HSP_DB_MASTER_BPMP>; 980 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 981 #clock-cells = <1>; 982 #reset-cells = <1>; 983 #power-domain-cells = <1>; 984 985 bpmp_i2c: i2c { 986 compatible = "nvidia,tegra186-bpmp-i2c"; 987 nvidia,bpmp-bus-id = <5>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 bpmp_thermal: thermal { 994 compatible = "nvidia,tegra186-bpmp-thermal"; 995 #thermal-sensor-cells = <1>; 996 }; 997 }; 998 999 thermal-zones { 1000 a57 { 1001 polling-delay = <0>; 1002 polling-delay-passive = <1000>; 1003 1004 thermal-sensors = 1005 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1006 1007 trips { 1008 critical { 1009 temperature = <101000>; 1010 hysteresis = <0>; 1011 type = "critical"; 1012 }; 1013 }; 1014 1015 cooling-maps { 1016 }; 1017 }; 1018 1019 denver { 1020 polling-delay = <0>; 1021 polling-delay-passive = <1000>; 1022 1023 thermal-sensors = 1024 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1025 1026 trips { 1027 critical { 1028 temperature = <101000>; 1029 hysteresis = <0>; 1030 type = "critical"; 1031 }; 1032 }; 1033 1034 cooling-maps { 1035 }; 1036 }; 1037 1038 gpu { 1039 polling-delay = <0>; 1040 polling-delay-passive = <1000>; 1041 1042 thermal-sensors = 1043 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1044 1045 trips { 1046 critical { 1047 temperature = <101000>; 1048 hysteresis = <0>; 1049 type = "critical"; 1050 }; 1051 }; 1052 1053 cooling-maps { 1054 }; 1055 }; 1056 1057 pll { 1058 polling-delay = <0>; 1059 polling-delay-passive = <1000>; 1060 1061 thermal-sensors = 1062 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1063 1064 trips { 1065 critical { 1066 temperature = <101000>; 1067 hysteresis = <0>; 1068 type = "critical"; 1069 }; 1070 }; 1071 1072 cooling-maps { 1073 }; 1074 }; 1075 1076 always_on { 1077 polling-delay = <0>; 1078 polling-delay-passive = <1000>; 1079 1080 thermal-sensors = 1081 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1082 1083 trips { 1084 critical { 1085 temperature = <101000>; 1086 hysteresis = <0>; 1087 type = "critical"; 1088 }; 1089 }; 1090 1091 cooling-maps { 1092 }; 1093 }; 1094 }; 1095 1096 timer { 1097 compatible = "arm,armv8-timer"; 1098 interrupts = <GIC_PPI 13 1099 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1100 <GIC_PPI 14 1101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1102 <GIC_PPI 11 1103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1104 <GIC_PPI 10 1105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1106 interrupt-parent = <&gic>; 1107 }; 1108}; 1109