arm64: tegra: Update AHUB clock parent and rate

I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely

arm64: tegra: Update AHUB clock parent and rate

I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely that similar issues would be seen. Thus update the
AHUB clock parent and rates here as well for Tegra194, Tegra186
and Tegra210.

Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components")
Cc: stable@vger.kernel.org
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop serial clock-names and reset-names

The serial node does not use clock-names and reset-names:

tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('cloc

arm64: tegra: Drop serial clock-names and reset-names

The serial node does not use clock-names and reset-names:

tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop I2C iommus and dma-coherent properties

Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that r

arm64: tegra: Drop I2C iommus and dma-coherent properties

Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that represent the GPC DMA controller, since that is the device
performing the direct memory accesses.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Sort nodes by unit-address, then alphabetically

Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions

arm64: tegra: Sort nodes by unit-address, then alphabetically

Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.

These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").

While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add dma-channel-mask in GPCDMA node

Add dma-channel-mask property in Tegra GPCDMA device tree node.

The property would help to specify the channels to be used in
kernel and reserve fe

arm64: tegra: Add dma-channel-mask in GPCDMA node

Add dma-channel-mask property in Tegra GPCDMA device tree node.

The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
This is wrong and does not align with the hardware. Correct this
and update the interrupts property to list all 32 interrupts.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove clock-names from PWM nodes

The Tegra PWFM controllers use a single clock, so there's no need for a
clock-names property.

Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+

arm64: tegra: Remove clock-names from PWM nodes

The Tegra PWFM controllers use a single clock, so there's no need for a
clock-names property.

Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add GPCDMA support for Tegra I2C

Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Redin

arm64: tegra: Add GPCDMA support for Tegra I2C

Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fixup iommu-map property formatting

Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@n

arm64: tegra: Fixup iommu-map property formatting

Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add Host1x context stream IDs on Tegra186+

Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow

arm64: tegra: Add Host1x context stream IDs on Tegra186+

Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.

The specified stream IDs must match those configured by the hypervisor,
if one is present.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable native timers on Tegra186

Enable the native timers on Tegra186 chips to allow using the watchdog
functionality to recover from system hangs.

Signed-off-by: Kartik <kkartik@nvid

arm64: tegra: Enable native timers on Tegra186

Enable the native timers on Tegra186 chips to allow using the watchdog
functionality to recover from system hangs.

Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Mark BPMP channels as no-memory-wc

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will caus

arm64: tegra: Mark BPMP channels as no-memory-wc

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will cause issues.

Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted
to resolve this by only mapping the regions specified in the device
tree on the assumption that there are no such restricted areas within
the 64K-aligned area of memory that contains the memory we wish to map.

Turns out this assumption is wrong, as there are such areas above the
4K pages described in the device trees. As such, we need to use the
bigger hammer that is no-memory-wc, which causes the memory to be
mapped as Device memory to which speculative accesses are disallowed.

As such, the previous patch in the series,
'firmware: tegra: bpmp: do only aligned access to IPC memory area',
is required with this patch to make the BPMP driver only issue aligned
memory accesses as those are also required with Device memory.

Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add OPE device on Tegra210 and later

Output Processing Engine (OPE) is a client of AHUB and is present on
Tegra210 and later generations of Tegra SoC. Add this device on the
relevant S

arm64: tegra: Add OPE device on Tegra210 and later

Output Processing Engine (OPE) is a client of AHUB and is present on
Tegra210 and later generations of Tegra SoC. Add this device on the
relevant SoC DTSI files.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add memory controller channels

From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be

arm64: tegra: Add memory controller channels

From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller. Also add reg-names
for each of these reg items which are used by driver for mapping.

Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add ASRC device on Tegra186 and later

Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is
present on Tegra186 and later generations of Tegra SoC. Add this device
on th

arm64: tegra: Add ASRC device on Tegra186 and later

Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is
present on Tegra186 and later generations of Tegra SoC. Add this device
on the relevant SoC DTSI files.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop arm,armv8-pmuv3 compatible string

The arm,armv8-pmuv3 compatible string is meant to be used only for
software models and not silicon chips. Drop them and use silicon-
specific com

arm64: tegra: Drop arm,armv8-pmuv3 compatible string

The arm,armv8-pmuv3 compatible string is meant to be used only for
software models and not silicon chips. Drop them and use silicon-
specific compatible strings instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add GPCDMA node for tegra186 and tegra194

Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.

Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed

arm64: tegra: Add GPCDMA node for tegra186 and tegra194

Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.

Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Adjust length of CCPLEX cluster MMIO region

The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length

arm64: tegra: Adjust length of CCPLEX cluster MMIO region

The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix Tegra186 compatible string list

The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.

Signe

arm64: tegra: Fix Tegra186 compatible string list

The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename thermal zones nodes

The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Add native timer support on Tegra186

The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tre

arm64: tegra: Add native timer support on Tegra186

The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194

Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.

Signed-off-by: Jon Hunter <jonathanh@nv

arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194

Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fixup SYSRAM references

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM refere

arm64: tegra: Fixup SYSRAM references

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add few AHUB devices for Tegra210 and later

Add DT nodes for following AHUB devices:
* SFC (Sampling Frequency Converter)
* MVC (Master Volume Control)
* AMX (Audio Multiplexer)
*

arm64: tegra: Add few AHUB devices for Tegra210 and later

Add DT nodes for following AHUB devices:
* SFC (Sampling Frequency Converter)
* MVC (Master Volume Control)
* AMX (Audio Multiplexer)
* ADX (Audio Demultiplexer)
* Mixer

Above devices are added for Tegra210, Tegra186 and Tegra194 generations
of Tegra SoC.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add NVDEC to Tegra186/194 device trees

Add a device tree node for NVDEC on Tegra186, and
device tree nodes for NVDEC and NVDEC1 on Tegra194.

Signed-off-by: Mikko Perttunen <mperttunen

arm64: tegra: Add NVDEC to Tegra186/194 device trees

Add a device tree node for NVDEC on Tegra186, and
device tree nodes for NVDEC and NVDEC1 on Tegra194.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Mark BPMP channels as no-memory-wc

[ Upstream commit 61192a9d8a6367ae1b8234876941b037910a2459 ]

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blo

arm64: tegra: Mark BPMP channels as no-memory-wc

[ Upstream commit 61192a9d8a6367ae1b8234876941b037910a2459 ]

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will cause issues.

Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted
to resolve this by only mapping the regions specified in the device
tree on the assumption that there are no such restricted areas within
the 64K-aligned area of memory that contains the memory we wish to map.

Turns out this assumption is wrong, as there are such areas above the
4K pages described in the device trees. As such, we need to use the
bigger hammer that is no-memory-wc, which causes the memory to be
mapped as Device memory to which speculative accesses are disallowed.

As such, the previous patch in the series,
'firmware: tegra: bpmp: do only aligned access to IPC memory area',
is required with this patch to make the BPMP driver only issue aligned
memory accesses as those are also required with Device memory.

Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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