1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/power/tegra186-powergate.h> 7#include <dt-bindings/reset/tegra186-reset.h> 8#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra186"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 misc@100000 { 17 compatible = "nvidia,tegra186-misc"; 18 reg = <0x0 0x00100000 0x0 0xf000>, 19 <0x0 0x0010f000 0x0 0x1000>; 20 }; 21 22 gpio: gpio@2200000 { 23 compatible = "nvidia,tegra186-gpio"; 24 reg-names = "security", "gpio"; 25 reg = <0x0 0x2200000 0x0 0x10000>, 26 <0x0 0x2210000 0x0 0x10000>; 27 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 33 #interrupt-cells = <2>; 34 interrupt-controller; 35 #gpio-cells = <2>; 36 gpio-controller; 37 }; 38 39 ethernet@2490000 { 40 compatible = "nvidia,tegra186-eqos", 41 "snps,dwc-qos-ethernet-4.10"; 42 reg = <0x0 0x02490000 0x0 0x10000>; 43 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 44 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 45 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 46 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 47 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 48 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 49 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 50 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 51 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 52 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 53 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 54 <&bpmp TEGRA186_CLK_EQOS_AXI>, 55 <&bpmp TEGRA186_CLK_EQOS_RX>, 56 <&bpmp TEGRA186_CLK_EQOS_TX>, 57 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 58 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 59 resets = <&bpmp TEGRA186_RESET_EQOS>; 60 reset-names = "eqos"; 61 status = "disabled"; 62 63 snps,write-requests = <1>; 64 snps,read-requests = <3>; 65 snps,burst-map = <0x7>; 66 snps,txpbl = <32>; 67 snps,rxpbl = <8>; 68 }; 69 70 uarta: serial@3100000 { 71 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 72 reg = <0x0 0x03100000 0x0 0x40>; 73 reg-shift = <2>; 74 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 75 clocks = <&bpmp TEGRA186_CLK_UARTA>; 76 clock-names = "serial"; 77 resets = <&bpmp TEGRA186_RESET_UARTA>; 78 reset-names = "serial"; 79 status = "disabled"; 80 }; 81 82 uartb: serial@3110000 { 83 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 84 reg = <0x0 0x03110000 0x0 0x40>; 85 reg-shift = <2>; 86 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 87 clocks = <&bpmp TEGRA186_CLK_UARTB>; 88 clock-names = "serial"; 89 resets = <&bpmp TEGRA186_RESET_UARTB>; 90 reset-names = "serial"; 91 status = "disabled"; 92 }; 93 94 uartd: serial@3130000 { 95 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 96 reg = <0x0 0x03130000 0x0 0x40>; 97 reg-shift = <2>; 98 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&bpmp TEGRA186_CLK_UARTD>; 100 clock-names = "serial"; 101 resets = <&bpmp TEGRA186_RESET_UARTD>; 102 reset-names = "serial"; 103 status = "disabled"; 104 }; 105 106 uarte: serial@3140000 { 107 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 108 reg = <0x0 0x03140000 0x0 0x40>; 109 reg-shift = <2>; 110 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&bpmp TEGRA186_CLK_UARTE>; 112 clock-names = "serial"; 113 resets = <&bpmp TEGRA186_RESET_UARTE>; 114 reset-names = "serial"; 115 status = "disabled"; 116 }; 117 118 uartf: serial@3150000 { 119 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 120 reg = <0x0 0x03150000 0x0 0x40>; 121 reg-shift = <2>; 122 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&bpmp TEGRA186_CLK_UARTF>; 124 clock-names = "serial"; 125 resets = <&bpmp TEGRA186_RESET_UARTF>; 126 reset-names = "serial"; 127 status = "disabled"; 128 }; 129 130 gen1_i2c: i2c@3160000 { 131 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 132 reg = <0x0 0x03160000 0x0 0x10000>; 133 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 clocks = <&bpmp TEGRA186_CLK_I2C1>; 137 clock-names = "div-clk"; 138 resets = <&bpmp TEGRA186_RESET_I2C1>; 139 reset-names = "i2c"; 140 status = "disabled"; 141 }; 142 143 cam_i2c: i2c@3180000 { 144 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 145 reg = <0x0 0x03180000 0x0 0x10000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 clocks = <&bpmp TEGRA186_CLK_I2C3>; 150 clock-names = "div-clk"; 151 resets = <&bpmp TEGRA186_RESET_I2C3>; 152 reset-names = "i2c"; 153 status = "disabled"; 154 }; 155 156 /* shares pads with dpaux1 */ 157 dp_aux_ch1_i2c: i2c@3190000 { 158 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 159 reg = <0x0 0x03190000 0x0 0x10000>; 160 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&bpmp TEGRA186_CLK_I2C4>; 164 clock-names = "div-clk"; 165 resets = <&bpmp TEGRA186_RESET_I2C4>; 166 reset-names = "i2c"; 167 status = "disabled"; 168 }; 169 170 /* controlled by BPMP, should not be enabled */ 171 pwr_i2c: i2c@31a0000 { 172 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 173 reg = <0x0 0x031a0000 0x0 0x10000>; 174 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clocks = <&bpmp TEGRA186_CLK_I2C5>; 178 clock-names = "div-clk"; 179 resets = <&bpmp TEGRA186_RESET_I2C5>; 180 reset-names = "i2c"; 181 status = "disabled"; 182 }; 183 184 /* shares pads with dpaux0 */ 185 dp_aux_ch0_i2c: i2c@31b0000 { 186 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 187 reg = <0x0 0x031b0000 0x0 0x10000>; 188 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 clocks = <&bpmp TEGRA186_CLK_I2C6>; 192 clock-names = "div-clk"; 193 resets = <&bpmp TEGRA186_RESET_I2C6>; 194 reset-names = "i2c"; 195 status = "disabled"; 196 }; 197 198 gen7_i2c: i2c@31c0000 { 199 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 200 reg = <0x0 0x031c0000 0x0 0x10000>; 201 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 clocks = <&bpmp TEGRA186_CLK_I2C7>; 205 clock-names = "div-clk"; 206 resets = <&bpmp TEGRA186_RESET_I2C7>; 207 reset-names = "i2c"; 208 status = "disabled"; 209 }; 210 211 gen9_i2c: i2c@31e0000 { 212 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 213 reg = <0x0 0x031e0000 0x0 0x10000>; 214 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 clocks = <&bpmp TEGRA186_CLK_I2C9>; 218 clock-names = "div-clk"; 219 resets = <&bpmp TEGRA186_RESET_I2C9>; 220 reset-names = "i2c"; 221 status = "disabled"; 222 }; 223 224 sdmmc1: sdhci@3400000 { 225 compatible = "nvidia,tegra186-sdhci"; 226 reg = <0x0 0x03400000 0x0 0x10000>; 227 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 229 clock-names = "sdhci"; 230 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 231 reset-names = "sdhci"; 232 status = "disabled"; 233 }; 234 235 sdmmc2: sdhci@3420000 { 236 compatible = "nvidia,tegra186-sdhci"; 237 reg = <0x0 0x03420000 0x0 0x10000>; 238 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 240 clock-names = "sdhci"; 241 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 242 reset-names = "sdhci"; 243 status = "disabled"; 244 }; 245 246 sdmmc3: sdhci@3440000 { 247 compatible = "nvidia,tegra186-sdhci"; 248 reg = <0x0 0x03440000 0x0 0x10000>; 249 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 251 clock-names = "sdhci"; 252 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 253 reset-names = "sdhci"; 254 status = "disabled"; 255 }; 256 257 sdmmc4: sdhci@3460000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03460000 0x0 0x10000>; 260 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 264 reset-names = "sdhci"; 265 status = "disabled"; 266 }; 267 268 fuse@3820000 { 269 compatible = "nvidia,tegra186-efuse"; 270 reg = <0x0 0x03820000 0x0 0x10000>; 271 clocks = <&bpmp TEGRA186_CLK_FUSE>; 272 clock-names = "fuse"; 273 }; 274 275 gic: interrupt-controller@3881000 { 276 compatible = "arm,gic-400"; 277 #interrupt-cells = <3>; 278 interrupt-controller; 279 reg = <0x0 0x03881000 0x0 0x1000>, 280 <0x0 0x03882000 0x0 0x2000>; 281 interrupts = <GIC_PPI 9 282 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 283 interrupt-parent = <&gic>; 284 }; 285 286 hsp_top0: hsp@3c00000 { 287 compatible = "nvidia,tegra186-hsp"; 288 reg = <0x0 0x03c00000 0x0 0xa0000>; 289 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "doorbell"; 291 #mbox-cells = <2>; 292 status = "disabled"; 293 }; 294 295 gen2_i2c: i2c@c240000 { 296 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 297 reg = <0x0 0x0c240000 0x0 0x10000>; 298 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clocks = <&bpmp TEGRA186_CLK_I2C2>; 302 clock-names = "div-clk"; 303 resets = <&bpmp TEGRA186_RESET_I2C2>; 304 reset-names = "i2c"; 305 status = "disabled"; 306 }; 307 308 gen8_i2c: i2c@c250000 { 309 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 310 reg = <0x0 0x0c250000 0x0 0x10000>; 311 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clocks = <&bpmp TEGRA186_CLK_I2C8>; 315 clock-names = "div-clk"; 316 resets = <&bpmp TEGRA186_RESET_I2C8>; 317 reset-names = "i2c"; 318 status = "disabled"; 319 }; 320 321 uartc: serial@c280000 { 322 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 323 reg = <0x0 0x0c280000 0x0 0x40>; 324 reg-shift = <2>; 325 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&bpmp TEGRA186_CLK_UARTC>; 327 clock-names = "serial"; 328 resets = <&bpmp TEGRA186_RESET_UARTC>; 329 reset-names = "serial"; 330 status = "disabled"; 331 }; 332 333 uartg: serial@c290000 { 334 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 335 reg = <0x0 0x0c290000 0x0 0x40>; 336 reg-shift = <2>; 337 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&bpmp TEGRA186_CLK_UARTG>; 339 clock-names = "serial"; 340 resets = <&bpmp TEGRA186_RESET_UARTG>; 341 reset-names = "serial"; 342 status = "disabled"; 343 }; 344 345 gpio_aon: gpio@c2f0000 { 346 compatible = "nvidia,tegra186-gpio-aon"; 347 reg-names = "security", "gpio"; 348 reg = <0x0 0xc2f0000 0x0 0x1000>, 349 <0x0 0xc2f1000 0x0 0x1000>; 350 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 351 gpio-controller; 352 #gpio-cells = <2>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 }; 356 357 pmc@c360000 { 358 compatible = "nvidia,tegra186-pmc"; 359 reg = <0 0x0c360000 0 0x10000>, 360 <0 0x0c370000 0 0x10000>, 361 <0 0x0c380000 0 0x10000>, 362 <0 0x0c390000 0 0x10000>; 363 reg-names = "pmc", "wake", "aotag", "scratch"; 364 }; 365 366 ccplex@e000000 { 367 compatible = "nvidia,tegra186-ccplex-cluster"; 368 reg = <0x0 0x0e000000 0x0 0x3fffff>; 369 370 nvidia,bpmp = <&bpmp>; 371 }; 372 373 pcie@10003000 { 374 compatible = "nvidia,tegra186-pcie"; 375 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 376 device_type = "pci"; 377 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 378 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 379 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 380 reg-names = "pads", "afi", "cs"; 381 382 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 383 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 384 interrupt-names = "intr", "msi"; 385 386 #interrupt-cells = <1>; 387 interrupt-map-mask = <0 0 0 0>; 388 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 389 390 bus-range = <0x00 0xff>; 391 #address-cells = <3>; 392 #size-cells = <2>; 393 394 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 395 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 396 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 397 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 398 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 399 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 400 401 clocks = <&bpmp TEGRA186_CLK_AFI>, 402 <&bpmp TEGRA186_CLK_PCIE>, 403 <&bpmp TEGRA186_CLK_PLLE>; 404 clock-names = "afi", "pex", "pll_e"; 405 406 resets = <&bpmp TEGRA186_RESET_AFI>, 407 <&bpmp TEGRA186_RESET_PCIE>, 408 <&bpmp TEGRA186_RESET_PCIEXCLK>; 409 reset-names = "afi", "pex", "pcie_x"; 410 411 status = "disabled"; 412 413 pci@1,0 { 414 device_type = "pci"; 415 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 416 reg = <0x000800 0 0 0 0>; 417 status = "disabled"; 418 419 #address-cells = <3>; 420 #size-cells = <2>; 421 ranges; 422 423 nvidia,num-lanes = <2>; 424 }; 425 426 pci@2,0 { 427 device_type = "pci"; 428 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 429 reg = <0x001000 0 0 0 0>; 430 status = "disabled"; 431 432 #address-cells = <3>; 433 #size-cells = <2>; 434 ranges; 435 436 nvidia,num-lanes = <1>; 437 }; 438 439 pci@3,0 { 440 device_type = "pci"; 441 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 442 reg = <0x001800 0 0 0 0>; 443 status = "disabled"; 444 445 #address-cells = <3>; 446 #size-cells = <2>; 447 ranges; 448 449 nvidia,num-lanes = <1>; 450 }; 451 }; 452 453 host1x@13e00000 { 454 compatible = "nvidia,tegra186-host1x", "simple-bus"; 455 reg = <0x0 0x13e00000 0x0 0x10000>, 456 <0x0 0x13e10000 0x0 0x10000>; 457 reg-names = "hypervisor", "vm"; 458 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 461 clock-names = "host1x"; 462 resets = <&bpmp TEGRA186_RESET_HOST1X>; 463 reset-names = "host1x"; 464 465 #address-cells = <1>; 466 #size-cells = <1>; 467 468 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 469 470 vic@15340000 { 471 compatible = "nvidia,tegra186-vic"; 472 reg = <0x15340000 0x40000>; 473 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&bpmp TEGRA186_CLK_VIC>; 475 clock-names = "vic"; 476 resets = <&bpmp TEGRA186_RESET_VIC>; 477 reset-names = "vic"; 478 479 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 480 }; 481 }; 482 483 gpu@17000000 { 484 compatible = "nvidia,gp10b"; 485 reg = <0x0 0x17000000 0x0 0x1000000>, 486 <0x0 0x18000000 0x0 0x1000000>; 487 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 488 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-names = "stall", "nonstall"; 490 491 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 492 <&bpmp TEGRA186_CLK_GPU>; 493 clock-names = "gpu", "pwr"; 494 resets = <&bpmp TEGRA186_RESET_GPU>; 495 reset-names = "gpu"; 496 status = "disabled"; 497 498 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 499 }; 500 501 sysram@30000000 { 502 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 503 reg = <0x0 0x30000000 0x0 0x50000>; 504 #address-cells = <2>; 505 #size-cells = <2>; 506 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 507 508 cpu_bpmp_tx: shmem@4e000 { 509 compatible = "nvidia,tegra186-bpmp-shmem"; 510 reg = <0x0 0x4e000 0x0 0x1000>; 511 label = "cpu-bpmp-tx"; 512 pool; 513 }; 514 515 cpu_bpmp_rx: shmem@4f000 { 516 compatible = "nvidia,tegra186-bpmp-shmem"; 517 reg = <0x0 0x4f000 0x0 0x1000>; 518 label = "cpu-bpmp-rx"; 519 pool; 520 }; 521 }; 522 523 cpus { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 527 cpu@0 { 528 compatible = "nvidia,tegra186-denver", "arm,armv8"; 529 device_type = "cpu"; 530 reg = <0x000>; 531 }; 532 533 cpu@1 { 534 compatible = "nvidia,tegra186-denver", "arm,armv8"; 535 device_type = "cpu"; 536 reg = <0x001>; 537 }; 538 539 cpu@2 { 540 compatible = "arm,cortex-a57", "arm,armv8"; 541 device_type = "cpu"; 542 reg = <0x100>; 543 }; 544 545 cpu@3 { 546 compatible = "arm,cortex-a57", "arm,armv8"; 547 device_type = "cpu"; 548 reg = <0x101>; 549 }; 550 551 cpu@4 { 552 compatible = "arm,cortex-a57", "arm,armv8"; 553 device_type = "cpu"; 554 reg = <0x102>; 555 }; 556 557 cpu@5 { 558 compatible = "arm,cortex-a57", "arm,armv8"; 559 device_type = "cpu"; 560 reg = <0x103>; 561 }; 562 }; 563 564 bpmp: bpmp { 565 compatible = "nvidia,tegra186-bpmp"; 566 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 567 TEGRA_HSP_DB_MASTER_BPMP>; 568 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 569 #clock-cells = <1>; 570 #reset-cells = <1>; 571 #power-domain-cells = <1>; 572 573 bpmp_i2c: i2c { 574 compatible = "nvidia,tegra186-bpmp-i2c"; 575 nvidia,bpmp-bus-id = <5>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 status = "disabled"; 579 }; 580 581 bpmp_thermal: thermal { 582 compatible = "nvidia,tegra186-bpmp-thermal"; 583 #thermal-sensor-cells = <1>; 584 }; 585 }; 586 587 thermal-zones { 588 a57 { 589 polling-delay = <0>; 590 polling-delay-passive = <1000>; 591 592 thermal-sensors = 593 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 594 595 trips { 596 critical { 597 temperature = <101000>; 598 hysteresis = <0>; 599 type = "critical"; 600 }; 601 }; 602 603 cooling-maps { 604 }; 605 }; 606 607 denver { 608 polling-delay = <0>; 609 polling-delay-passive = <1000>; 610 611 thermal-sensors = 612 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 613 614 trips { 615 critical { 616 temperature = <101000>; 617 hysteresis = <0>; 618 type = "critical"; 619 }; 620 }; 621 622 cooling-maps { 623 }; 624 }; 625 626 gpu { 627 polling-delay = <0>; 628 polling-delay-passive = <1000>; 629 630 thermal-sensors = 631 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 632 633 trips { 634 critical { 635 temperature = <101000>; 636 hysteresis = <0>; 637 type = "critical"; 638 }; 639 }; 640 641 cooling-maps { 642 }; 643 }; 644 645 pll { 646 polling-delay = <0>; 647 polling-delay-passive = <1000>; 648 649 thermal-sensors = 650 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 651 652 trips { 653 critical { 654 temperature = <101000>; 655 hysteresis = <0>; 656 type = "critical"; 657 }; 658 }; 659 660 cooling-maps { 661 }; 662 }; 663 664 always_on { 665 polling-delay = <0>; 666 polling-delay-passive = <1000>; 667 668 thermal-sensors = 669 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 670 671 trips { 672 critical { 673 temperature = <101000>; 674 hysteresis = <0>; 675 type = "critical"; 676 }; 677 }; 678 679 cooling-maps { 680 }; 681 }; 682 }; 683 684 timer { 685 compatible = "arm,armv8-timer"; 686 interrupts = <GIC_PPI 13 687 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 688 <GIC_PPI 14 689 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 690 <GIC_PPI 11 691 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 692 <GIC_PPI 10 693 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 694 interrupt-parent = <&gic>; 695 }; 696}; 697