1#include <dt-bindings/clock/tegra186-clock.h> 2#include <dt-bindings/gpio/tegra186-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h> 5#include <dt-bindings/power/tegra186-powergate.h> 6#include <dt-bindings/reset/tegra186-reset.h> 7 8/ { 9 compatible = "nvidia,tegra186"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 gpio: gpio@2200000 { 15 compatible = "nvidia,tegra186-gpio"; 16 reg-names = "security", "gpio"; 17 reg = <0x0 0x2200000 0x0 0x10000>, 18 <0x0 0x2210000 0x0 0x10000>; 19 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 25 #interrupt-cells = <2>; 26 interrupt-controller; 27 #gpio-cells = <2>; 28 gpio-controller; 29 }; 30 31 ethernet@2490000 { 32 compatible = "nvidia,tegra186-eqos", 33 "snps,dwc-qos-ethernet-4.10"; 34 reg = <0x0 0x02490000 0x0 0x10000>; 35 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 36 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 37 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 38 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 39 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 40 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 41 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 42 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 43 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 44 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 45 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 46 <&bpmp TEGRA186_CLK_EQOS_AXI>, 47 <&bpmp TEGRA186_CLK_EQOS_RX>, 48 <&bpmp TEGRA186_CLK_EQOS_TX>, 49 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA186_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <32>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 64 reg = <0x0 0x03100000 0x0 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA186_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA186_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 76 reg = <0x0 0x03110000 0x0 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA186_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA186_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 88 reg = <0x0 0x03130000 0x0 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA186_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA186_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 100 reg = <0x0 0x03140000 0x0 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA186_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA186_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 112 reg = <0x0 0x03150000 0x0 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA186_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA186_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 124 reg = <0x0 0x03160000 0x0 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA186_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA186_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 cam_i2c: i2c@3180000 { 136 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 137 reg = <0x0 0x03180000 0x0 0x10000>; 138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 clocks = <&bpmp TEGRA186_CLK_I2C3>; 142 clock-names = "div-clk"; 143 resets = <&bpmp TEGRA186_RESET_I2C3>; 144 reset-names = "i2c"; 145 status = "disabled"; 146 }; 147 148 /* shares pads with dpaux1 */ 149 dp_aux_ch1_i2c: i2c@3190000 { 150 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 151 reg = <0x0 0x03190000 0x0 0x10000>; 152 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 clocks = <&bpmp TEGRA186_CLK_I2C4>; 156 clock-names = "div-clk"; 157 resets = <&bpmp TEGRA186_RESET_I2C4>; 158 reset-names = "i2c"; 159 status = "disabled"; 160 }; 161 162 /* controlled by BPMP, should not be enabled */ 163 pwr_i2c: i2c@31a0000 { 164 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 165 reg = <0x0 0x031a0000 0x0 0x10000>; 166 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 clocks = <&bpmp TEGRA186_CLK_I2C5>; 170 clock-names = "div-clk"; 171 resets = <&bpmp TEGRA186_RESET_I2C5>; 172 reset-names = "i2c"; 173 status = "disabled"; 174 }; 175 176 /* shares pads with dpaux0 */ 177 dp_aux_ch0_i2c: i2c@31b0000 { 178 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 179 reg = <0x0 0x031b0000 0x0 0x10000>; 180 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 clocks = <&bpmp TEGRA186_CLK_I2C6>; 184 clock-names = "div-clk"; 185 resets = <&bpmp TEGRA186_RESET_I2C6>; 186 reset-names = "i2c"; 187 status = "disabled"; 188 }; 189 190 gen7_i2c: i2c@31c0000 { 191 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 192 reg = <0x0 0x031c0000 0x0 0x10000>; 193 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 clocks = <&bpmp TEGRA186_CLK_I2C7>; 197 clock-names = "div-clk"; 198 resets = <&bpmp TEGRA186_RESET_I2C7>; 199 reset-names = "i2c"; 200 status = "disabled"; 201 }; 202 203 gen9_i2c: i2c@31e0000 { 204 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 205 reg = <0x0 0x031e0000 0x0 0x10000>; 206 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 clocks = <&bpmp TEGRA186_CLK_I2C9>; 210 clock-names = "div-clk"; 211 resets = <&bpmp TEGRA186_RESET_I2C9>; 212 reset-names = "i2c"; 213 status = "disabled"; 214 }; 215 216 sdmmc1: sdhci@3400000 { 217 compatible = "nvidia,tegra186-sdhci"; 218 reg = <0x0 0x03400000 0x0 0x10000>; 219 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 221 clock-names = "sdhci"; 222 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 223 reset-names = "sdhci"; 224 status = "disabled"; 225 }; 226 227 sdmmc2: sdhci@3420000 { 228 compatible = "nvidia,tegra186-sdhci"; 229 reg = <0x0 0x03420000 0x0 0x10000>; 230 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 232 clock-names = "sdhci"; 233 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 234 reset-names = "sdhci"; 235 status = "disabled"; 236 }; 237 238 sdmmc3: sdhci@3440000 { 239 compatible = "nvidia,tegra186-sdhci"; 240 reg = <0x0 0x03440000 0x0 0x10000>; 241 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 243 clock-names = "sdhci"; 244 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 245 reset-names = "sdhci"; 246 status = "disabled"; 247 }; 248 249 sdmmc4: sdhci@3460000 { 250 compatible = "nvidia,tegra186-sdhci"; 251 reg = <0x0 0x03460000 0x0 0x10000>; 252 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 254 clock-names = "sdhci"; 255 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 256 reset-names = "sdhci"; 257 status = "disabled"; 258 }; 259 260 gic: interrupt-controller@3881000 { 261 compatible = "arm,gic-400"; 262 #interrupt-cells = <3>; 263 interrupt-controller; 264 reg = <0x0 0x03881000 0x0 0x1000>, 265 <0x0 0x03882000 0x0 0x2000>; 266 interrupts = <GIC_PPI 9 267 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 268 interrupt-parent = <&gic>; 269 }; 270 271 hsp_top0: hsp@3c00000 { 272 compatible = "nvidia,tegra186-hsp"; 273 reg = <0x0 0x03c00000 0x0 0xa0000>; 274 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-names = "doorbell"; 276 #mbox-cells = <2>; 277 status = "disabled"; 278 }; 279 280 gen2_i2c: i2c@c240000 { 281 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 282 reg = <0x0 0x0c240000 0x0 0x10000>; 283 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&bpmp TEGRA186_CLK_I2C2>; 287 clock-names = "div-clk"; 288 resets = <&bpmp TEGRA186_RESET_I2C2>; 289 reset-names = "i2c"; 290 status = "disabled"; 291 }; 292 293 gen8_i2c: i2c@c250000 { 294 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 295 reg = <0x0 0x0c250000 0x0 0x10000>; 296 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clocks = <&bpmp TEGRA186_CLK_I2C8>; 300 clock-names = "div-clk"; 301 resets = <&bpmp TEGRA186_RESET_I2C8>; 302 reset-names = "i2c"; 303 status = "disabled"; 304 }; 305 306 uartc: serial@c280000 { 307 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 308 reg = <0x0 0x0c280000 0x0 0x40>; 309 reg-shift = <2>; 310 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&bpmp TEGRA186_CLK_UARTC>; 312 clock-names = "serial"; 313 resets = <&bpmp TEGRA186_RESET_UARTC>; 314 reset-names = "serial"; 315 status = "disabled"; 316 }; 317 318 uartg: serial@c290000 { 319 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 320 reg = <0x0 0x0c290000 0x0 0x40>; 321 reg-shift = <2>; 322 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&bpmp TEGRA186_CLK_UARTG>; 324 clock-names = "serial"; 325 resets = <&bpmp TEGRA186_RESET_UARTG>; 326 reset-names = "serial"; 327 status = "disabled"; 328 }; 329 330 gpio_aon: gpio@c2f0000 { 331 compatible = "nvidia,tegra186-gpio-aon"; 332 reg-names = "security", "gpio"; 333 reg = <0x0 0xc2f0000 0x0 0x1000>, 334 <0x0 0xc2f1000 0x0 0x1000>; 335 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 342 pmc@c360000 { 343 compatible = "nvidia,tegra186-pmc"; 344 reg = <0 0x0c360000 0 0x10000>, 345 <0 0x0c370000 0 0x10000>, 346 <0 0x0c380000 0 0x10000>, 347 <0 0x0c390000 0 0x10000>; 348 reg-names = "pmc", "wake", "aotag", "scratch"; 349 }; 350 351 ccplex@e000000 { 352 compatible = "nvidia,tegra186-ccplex-cluster"; 353 reg = <0x0 0x0e000000 0x0 0x3fffff>; 354 355 nvidia,bpmp = <&bpmp>; 356 }; 357 358 pcie@10003000 { 359 compatible = "nvidia,tegra186-pcie"; 360 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 361 device_type = "pci"; 362 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 363 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 364 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 365 reg-names = "pads", "afi", "cs"; 366 367 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 368 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 369 interrupt-names = "intr", "msi"; 370 371 #interrupt-cells = <1>; 372 interrupt-map-mask = <0 0 0 0>; 373 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 374 375 bus-range = <0x00 0xff>; 376 #address-cells = <3>; 377 #size-cells = <2>; 378 379 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 380 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 381 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 382 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 383 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 384 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 385 386 clocks = <&bpmp TEGRA186_CLK_AFI>, 387 <&bpmp TEGRA186_CLK_PCIE>, 388 <&bpmp TEGRA186_CLK_PLLE>; 389 clock-names = "afi", "pex", "pll_e"; 390 391 resets = <&bpmp TEGRA186_RESET_AFI>, 392 <&bpmp TEGRA186_RESET_PCIE>, 393 <&bpmp TEGRA186_RESET_PCIEXCLK>; 394 reset-names = "afi", "pex", "pcie_x"; 395 396 status = "disabled"; 397 398 pci@1,0 { 399 device_type = "pci"; 400 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 401 reg = <0x000800 0 0 0 0>; 402 status = "disabled"; 403 404 #address-cells = <3>; 405 #size-cells = <2>; 406 ranges; 407 408 nvidia,num-lanes = <2>; 409 }; 410 411 pci@2,0 { 412 device_type = "pci"; 413 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 414 reg = <0x001000 0 0 0 0>; 415 status = "disabled"; 416 417 #address-cells = <3>; 418 #size-cells = <2>; 419 ranges; 420 421 nvidia,num-lanes = <1>; 422 }; 423 424 pci@3,0 { 425 device_type = "pci"; 426 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 427 reg = <0x001800 0 0 0 0>; 428 status = "disabled"; 429 430 #address-cells = <3>; 431 #size-cells = <2>; 432 ranges; 433 434 nvidia,num-lanes = <1>; 435 }; 436 }; 437 438 host1x@13e00000 { 439 compatible = "nvidia,tegra186-host1x", "simple-bus"; 440 reg = <0x0 0x13e00000 0x0 0x10000>, 441 <0x0 0x13e10000 0x0 0x10000>; 442 reg-names = "hypervisor", "vm"; 443 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 446 clock-names = "host1x"; 447 resets = <&bpmp TEGRA186_RESET_HOST1X>; 448 reset-names = "host1x"; 449 450 #address-cells = <1>; 451 #size-cells = <1>; 452 453 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 454 455 vic@15340000 { 456 compatible = "nvidia,tegra186-vic"; 457 reg = <0x15340000 0x40000>; 458 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&bpmp TEGRA186_CLK_VIC>; 460 clock-names = "vic"; 461 resets = <&bpmp TEGRA186_RESET_VIC>; 462 reset-names = "vic"; 463 464 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 465 }; 466 }; 467 468 gpu@17000000 { 469 compatible = "nvidia,gp10b"; 470 reg = <0x0 0x17000000 0x0 0x1000000>, 471 <0x0 0x18000000 0x0 0x1000000>; 472 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 473 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 474 interrupt-names = "stall", "nonstall"; 475 476 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 477 <&bpmp TEGRA186_CLK_GPU>; 478 clock-names = "gpu", "pwr"; 479 resets = <&bpmp TEGRA186_RESET_GPU>; 480 reset-names = "gpu"; 481 status = "disabled"; 482 483 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 484 }; 485 486 sysram@30000000 { 487 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 488 reg = <0x0 0x30000000 0x0 0x50000>; 489 #address-cells = <2>; 490 #size-cells = <2>; 491 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 492 493 cpu_bpmp_tx: shmem@4e000 { 494 compatible = "nvidia,tegra186-bpmp-shmem"; 495 reg = <0x0 0x4e000 0x0 0x1000>; 496 label = "cpu-bpmp-tx"; 497 pool; 498 }; 499 500 cpu_bpmp_rx: shmem@4f000 { 501 compatible = "nvidia,tegra186-bpmp-shmem"; 502 reg = <0x0 0x4f000 0x0 0x1000>; 503 label = "cpu-bpmp-rx"; 504 pool; 505 }; 506 }; 507 508 cpus { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 cpu@0 { 513 compatible = "nvidia,tegra186-denver", "arm,armv8"; 514 device_type = "cpu"; 515 reg = <0x000>; 516 }; 517 518 cpu@1 { 519 compatible = "nvidia,tegra186-denver", "arm,armv8"; 520 device_type = "cpu"; 521 reg = <0x001>; 522 }; 523 524 cpu@2 { 525 compatible = "arm,cortex-a57", "arm,armv8"; 526 device_type = "cpu"; 527 reg = <0x100>; 528 }; 529 530 cpu@3 { 531 compatible = "arm,cortex-a57", "arm,armv8"; 532 device_type = "cpu"; 533 reg = <0x101>; 534 }; 535 536 cpu@4 { 537 compatible = "arm,cortex-a57", "arm,armv8"; 538 device_type = "cpu"; 539 reg = <0x102>; 540 }; 541 542 cpu@5 { 543 compatible = "arm,cortex-a57", "arm,armv8"; 544 device_type = "cpu"; 545 reg = <0x103>; 546 }; 547 }; 548 549 bpmp: bpmp { 550 compatible = "nvidia,tegra186-bpmp"; 551 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 552 TEGRA_HSP_DB_MASTER_BPMP>; 553 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 554 #clock-cells = <1>; 555 #reset-cells = <1>; 556 #power-domain-cells = <1>; 557 558 bpmp_i2c: i2c { 559 compatible = "nvidia,tegra186-bpmp-i2c"; 560 nvidia,bpmp-bus-id = <5>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 }; 566 567 timer { 568 compatible = "arm,armv8-timer"; 569 interrupts = <GIC_PPI 13 570 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 571 <GIC_PPI 14 572 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 573 <GIC_PPI 11 574 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 575 <GIC_PPI 10 576 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 577 interrupt-parent = <&gic>; 578 }; 579}; 580