1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 252 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 status = "disabled"; 255 }; 256 257 sdmmc2: sdhci@3420000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03420000 0x0 0x10000>; 260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 264 reset-names = "sdhci"; 265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 266 pinctrl-0 = <&sdmmc2_3v3>; 267 pinctrl-1 = <&sdmmc2_1v8>; 268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 272 nvidia,default-tap = <0x5>; 273 nvidia,default-trim = <0xb>; 274 status = "disabled"; 275 }; 276 277 sdmmc3: sdhci@3440000 { 278 compatible = "nvidia,tegra186-sdhci"; 279 reg = <0x0 0x03440000 0x0 0x10000>; 280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 282 clock-names = "sdhci"; 283 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 284 reset-names = "sdhci"; 285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 286 pinctrl-0 = <&sdmmc3_3v3>; 287 pinctrl-1 = <&sdmmc3_1v8>; 288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 294 nvidia,default-tap = <0x5>; 295 nvidia,default-trim = <0xb>; 296 status = "disabled"; 297 }; 298 299 sdmmc4: sdhci@3460000 { 300 compatible = "nvidia,tegra186-sdhci"; 301 reg = <0x0 0x03460000 0x0 0x10000>; 302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 304 clock-names = "sdhci"; 305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 306 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 308 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 309 reset-names = "sdhci"; 310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 314 nvidia,default-tap = <0x5>; 315 nvidia,default-trim = <0x9>; 316 nvidia,dqs-trim = <63>; 317 mmc-hs400-1_8v; 318 status = "disabled"; 319 }; 320 321 hda@3510000 { 322 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 323 reg = <0x0 0x03510000 0x0 0x10000>; 324 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&bpmp TEGRA186_CLK_HDA>, 326 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 327 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 328 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 329 resets = <&bpmp TEGRA186_RESET_HDA>, 330 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 331 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 332 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 333 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 334 status = "disabled"; 335 }; 336 337 fuse@3820000 { 338 compatible = "nvidia,tegra186-efuse"; 339 reg = <0x0 0x03820000 0x0 0x10000>; 340 clocks = <&bpmp TEGRA186_CLK_FUSE>; 341 clock-names = "fuse"; 342 }; 343 344 gic: interrupt-controller@3881000 { 345 compatible = "arm,gic-400"; 346 #interrupt-cells = <3>; 347 interrupt-controller; 348 reg = <0x0 0x03881000 0x0 0x1000>, 349 <0x0 0x03882000 0x0 0x2000>; 350 interrupts = <GIC_PPI 9 351 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 352 interrupt-parent = <&gic>; 353 }; 354 355 hsp_top0: hsp@3c00000 { 356 compatible = "nvidia,tegra186-hsp"; 357 reg = <0x0 0x03c00000 0x0 0xa0000>; 358 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 359 interrupt-names = "doorbell"; 360 #mbox-cells = <2>; 361 status = "disabled"; 362 }; 363 364 gen2_i2c: i2c@c240000 { 365 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 366 reg = <0x0 0x0c240000 0x0 0x10000>; 367 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 clocks = <&bpmp TEGRA186_CLK_I2C2>; 371 clock-names = "div-clk"; 372 resets = <&bpmp TEGRA186_RESET_I2C2>; 373 reset-names = "i2c"; 374 status = "disabled"; 375 }; 376 377 gen8_i2c: i2c@c250000 { 378 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 379 reg = <0x0 0x0c250000 0x0 0x10000>; 380 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&bpmp TEGRA186_CLK_I2C8>; 384 clock-names = "div-clk"; 385 resets = <&bpmp TEGRA186_RESET_I2C8>; 386 reset-names = "i2c"; 387 status = "disabled"; 388 }; 389 390 uartc: serial@c280000 { 391 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 392 reg = <0x0 0x0c280000 0x0 0x40>; 393 reg-shift = <2>; 394 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA186_CLK_UARTC>; 396 clock-names = "serial"; 397 resets = <&bpmp TEGRA186_RESET_UARTC>; 398 reset-names = "serial"; 399 status = "disabled"; 400 }; 401 402 uartg: serial@c290000 { 403 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 404 reg = <0x0 0x0c290000 0x0 0x40>; 405 reg-shift = <2>; 406 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&bpmp TEGRA186_CLK_UARTG>; 408 clock-names = "serial"; 409 resets = <&bpmp TEGRA186_RESET_UARTG>; 410 reset-names = "serial"; 411 status = "disabled"; 412 }; 413 414 rtc: rtc@c2a0000 { 415 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 416 reg = <0 0x0c2a0000 0 0x10000>; 417 interrupt-parent = <&pmc>; 418 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 420 clock-names = "rtc"; 421 status = "disabled"; 422 }; 423 424 gpio_aon: gpio@c2f0000 { 425 compatible = "nvidia,tegra186-gpio-aon"; 426 reg-names = "security", "gpio"; 427 reg = <0x0 0xc2f0000 0x0 0x1000>, 428 <0x0 0xc2f1000 0x0 0x1000>; 429 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 }; 435 436 pmc: pmc@c360000 { 437 compatible = "nvidia,tegra186-pmc"; 438 reg = <0 0x0c360000 0 0x10000>, 439 <0 0x0c370000 0 0x10000>, 440 <0 0x0c380000 0 0x10000>, 441 <0 0x0c390000 0 0x10000>; 442 reg-names = "pmc", "wake", "aotag", "scratch"; 443 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 447 sdmmc1_3v3: sdmmc1-3v3 { 448 pins = "sdmmc1-hv"; 449 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 450 }; 451 452 sdmmc1_1v8: sdmmc1-1v8 { 453 pins = "sdmmc1-hv"; 454 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 455 }; 456 457 sdmmc2_3v3: sdmmc2-3v3 { 458 pins = "sdmmc2-hv"; 459 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 460 }; 461 462 sdmmc2_1v8: sdmmc2-1v8 { 463 pins = "sdmmc2-hv"; 464 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 465 }; 466 467 sdmmc3_3v3: sdmmc3-3v3 { 468 pins = "sdmmc3-hv"; 469 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 470 }; 471 472 sdmmc3_1v8: sdmmc3-1v8 { 473 pins = "sdmmc3-hv"; 474 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 475 }; 476 }; 477 478 ccplex@e000000 { 479 compatible = "nvidia,tegra186-ccplex-cluster"; 480 reg = <0x0 0x0e000000 0x0 0x3fffff>; 481 482 nvidia,bpmp = <&bpmp>; 483 }; 484 485 pcie@10003000 { 486 compatible = "nvidia,tegra186-pcie"; 487 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 488 device_type = "pci"; 489 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 490 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 491 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 492 reg-names = "pads", "afi", "cs"; 493 494 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 495 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 496 interrupt-names = "intr", "msi"; 497 498 #interrupt-cells = <1>; 499 interrupt-map-mask = <0 0 0 0>; 500 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 501 502 bus-range = <0x00 0xff>; 503 #address-cells = <3>; 504 #size-cells = <2>; 505 506 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 507 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 508 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 509 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 510 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 511 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 512 513 clocks = <&bpmp TEGRA186_CLK_AFI>, 514 <&bpmp TEGRA186_CLK_PCIE>, 515 <&bpmp TEGRA186_CLK_PLLE>; 516 clock-names = "afi", "pex", "pll_e"; 517 518 resets = <&bpmp TEGRA186_RESET_AFI>, 519 <&bpmp TEGRA186_RESET_PCIE>, 520 <&bpmp TEGRA186_RESET_PCIEXCLK>; 521 reset-names = "afi", "pex", "pcie_x"; 522 523 status = "disabled"; 524 525 pci@1,0 { 526 device_type = "pci"; 527 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 528 reg = <0x000800 0 0 0 0>; 529 status = "disabled"; 530 531 #address-cells = <3>; 532 #size-cells = <2>; 533 ranges; 534 535 nvidia,num-lanes = <2>; 536 }; 537 538 pci@2,0 { 539 device_type = "pci"; 540 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 541 reg = <0x001000 0 0 0 0>; 542 status = "disabled"; 543 544 #address-cells = <3>; 545 #size-cells = <2>; 546 ranges; 547 548 nvidia,num-lanes = <1>; 549 }; 550 551 pci@3,0 { 552 device_type = "pci"; 553 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 554 reg = <0x001800 0 0 0 0>; 555 status = "disabled"; 556 557 #address-cells = <3>; 558 #size-cells = <2>; 559 ranges; 560 561 nvidia,num-lanes = <1>; 562 }; 563 }; 564 565 smmu: iommu@12000000 { 566 compatible = "arm,mmu-500"; 567 reg = <0 0x12000000 0 0x800000>; 568 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 633 stream-match-mask = <0x7f80>; 634 #global-interrupts = <1>; 635 #iommu-cells = <1>; 636 }; 637 638 host1x@13e00000 { 639 compatible = "nvidia,tegra186-host1x", "simple-bus"; 640 reg = <0x0 0x13e00000 0x0 0x10000>, 641 <0x0 0x13e10000 0x0 0x10000>; 642 reg-names = "hypervisor", "vm"; 643 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 646 clock-names = "host1x"; 647 resets = <&bpmp TEGRA186_RESET_HOST1X>; 648 reset-names = "host1x"; 649 650 #address-cells = <1>; 651 #size-cells = <1>; 652 653 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 654 iommus = <&smmu TEGRA186_SID_HOST1X>; 655 656 dpaux1: dpaux@15040000 { 657 compatible = "nvidia,tegra186-dpaux"; 658 reg = <0x15040000 0x10000>; 659 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 661 <&bpmp TEGRA186_CLK_PLLDP>; 662 clock-names = "dpaux", "parent"; 663 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 664 reset-names = "dpaux"; 665 status = "disabled"; 666 667 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 668 669 state_dpaux1_aux: pinmux-aux { 670 groups = "dpaux-io"; 671 function = "aux"; 672 }; 673 674 state_dpaux1_i2c: pinmux-i2c { 675 groups = "dpaux-io"; 676 function = "i2c"; 677 }; 678 679 state_dpaux1_off: pinmux-off { 680 groups = "dpaux-io"; 681 function = "off"; 682 }; 683 684 i2c-bus { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 }; 688 }; 689 690 display-hub@15200000 { 691 compatible = "nvidia,tegra186-display", "simple-bus"; 692 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 693 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 694 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 695 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 696 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 697 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 698 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 699 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 700 "wgrp3", "wgrp4", "wgrp5"; 701 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 702 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 703 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 704 clock-names = "disp", "dsc", "hub"; 705 status = "disabled"; 706 707 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 708 709 #address-cells = <1>; 710 #size-cells = <1>; 711 712 ranges = <0x15200000 0x15200000 0x40000>; 713 714 display@15200000 { 715 compatible = "nvidia,tegra186-dc"; 716 reg = <0x15200000 0x10000>; 717 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 719 clock-names = "dc"; 720 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 721 reset-names = "dc"; 722 723 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 724 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 725 726 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 727 nvidia,head = <0>; 728 }; 729 730 display@15210000 { 731 compatible = "nvidia,tegra186-dc"; 732 reg = <0x15210000 0x10000>; 733 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 735 clock-names = "dc"; 736 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 737 reset-names = "dc"; 738 739 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 740 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 741 742 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 743 nvidia,head = <1>; 744 }; 745 746 display@15220000 { 747 compatible = "nvidia,tegra186-dc"; 748 reg = <0x15220000 0x10000>; 749 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 751 clock-names = "dc"; 752 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 753 reset-names = "dc"; 754 755 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 756 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 757 758 nvidia,outputs = <&sor0 &sor1>; 759 nvidia,head = <2>; 760 }; 761 }; 762 763 dsia: dsi@15300000 { 764 compatible = "nvidia,tegra186-dsi"; 765 reg = <0x15300000 0x10000>; 766 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA186_CLK_DSI>, 768 <&bpmp TEGRA186_CLK_DSIA_LP>, 769 <&bpmp TEGRA186_CLK_PLLD>; 770 clock-names = "dsi", "lp", "parent"; 771 resets = <&bpmp TEGRA186_RESET_DSI>; 772 reset-names = "dsi"; 773 status = "disabled"; 774 775 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 776 }; 777 778 vic@15340000 { 779 compatible = "nvidia,tegra186-vic"; 780 reg = <0x15340000 0x40000>; 781 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&bpmp TEGRA186_CLK_VIC>; 783 clock-names = "vic"; 784 resets = <&bpmp TEGRA186_RESET_VIC>; 785 reset-names = "vic"; 786 787 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 788 }; 789 790 dsib: dsi@15400000 { 791 compatible = "nvidia,tegra186-dsi"; 792 reg = <0x15400000 0x10000>; 793 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&bpmp TEGRA186_CLK_DSIB>, 795 <&bpmp TEGRA186_CLK_DSIB_LP>, 796 <&bpmp TEGRA186_CLK_PLLD>; 797 clock-names = "dsi", "lp", "parent"; 798 resets = <&bpmp TEGRA186_RESET_DSIB>; 799 reset-names = "dsi"; 800 status = "disabled"; 801 802 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 803 }; 804 805 sor0: sor@15540000 { 806 compatible = "nvidia,tegra186-sor"; 807 reg = <0x15540000 0x10000>; 808 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&bpmp TEGRA186_CLK_SOR0>, 810 <&bpmp TEGRA186_CLK_SOR0_OUT>, 811 <&bpmp TEGRA186_CLK_PLLD2>, 812 <&bpmp TEGRA186_CLK_PLLDP>, 813 <&bpmp TEGRA186_CLK_SOR_SAFE>, 814 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 815 clock-names = "sor", "out", "parent", "dp", "safe", 816 "pad"; 817 resets = <&bpmp TEGRA186_RESET_SOR0>; 818 reset-names = "sor"; 819 pinctrl-0 = <&state_dpaux_aux>; 820 pinctrl-1 = <&state_dpaux_i2c>; 821 pinctrl-2 = <&state_dpaux_off>; 822 pinctrl-names = "aux", "i2c", "off"; 823 status = "disabled"; 824 825 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 826 nvidia,interface = <0>; 827 }; 828 829 sor1: sor@15580000 { 830 compatible = "nvidia,tegra186-sor1"; 831 reg = <0x15580000 0x10000>; 832 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&bpmp TEGRA186_CLK_SOR1>, 834 <&bpmp TEGRA186_CLK_SOR1_OUT>, 835 <&bpmp TEGRA186_CLK_PLLD3>, 836 <&bpmp TEGRA186_CLK_PLLDP>, 837 <&bpmp TEGRA186_CLK_SOR_SAFE>, 838 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 839 clock-names = "sor", "out", "parent", "dp", "safe", 840 "pad"; 841 resets = <&bpmp TEGRA186_RESET_SOR1>; 842 reset-names = "sor"; 843 pinctrl-0 = <&state_dpaux1_aux>; 844 pinctrl-1 = <&state_dpaux1_i2c>; 845 pinctrl-2 = <&state_dpaux1_off>; 846 pinctrl-names = "aux", "i2c", "off"; 847 status = "disabled"; 848 849 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 850 nvidia,interface = <1>; 851 }; 852 853 dpaux: dpaux@155c0000 { 854 compatible = "nvidia,tegra186-dpaux"; 855 reg = <0x155c0000 0x10000>; 856 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 858 <&bpmp TEGRA186_CLK_PLLDP>; 859 clock-names = "dpaux", "parent"; 860 resets = <&bpmp TEGRA186_RESET_DPAUX>; 861 reset-names = "dpaux"; 862 status = "disabled"; 863 864 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 865 866 state_dpaux_aux: pinmux-aux { 867 groups = "dpaux-io"; 868 function = "aux"; 869 }; 870 871 state_dpaux_i2c: pinmux-i2c { 872 groups = "dpaux-io"; 873 function = "i2c"; 874 }; 875 876 state_dpaux_off: pinmux-off { 877 groups = "dpaux-io"; 878 function = "off"; 879 }; 880 881 i2c-bus { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 }; 885 }; 886 887 padctl@15880000 { 888 compatible = "nvidia,tegra186-dsi-padctl"; 889 reg = <0x15880000 0x10000>; 890 resets = <&bpmp TEGRA186_RESET_DSI>; 891 reset-names = "dsi"; 892 status = "disabled"; 893 }; 894 895 dsic: dsi@15900000 { 896 compatible = "nvidia,tegra186-dsi"; 897 reg = <0x15900000 0x10000>; 898 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&bpmp TEGRA186_CLK_DSIC>, 900 <&bpmp TEGRA186_CLK_DSIC_LP>, 901 <&bpmp TEGRA186_CLK_PLLD>; 902 clock-names = "dsi", "lp", "parent"; 903 resets = <&bpmp TEGRA186_RESET_DSIC>; 904 reset-names = "dsi"; 905 status = "disabled"; 906 907 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 908 }; 909 910 dsid: dsi@15940000 { 911 compatible = "nvidia,tegra186-dsi"; 912 reg = <0x15940000 0x10000>; 913 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&bpmp TEGRA186_CLK_DSID>, 915 <&bpmp TEGRA186_CLK_DSID_LP>, 916 <&bpmp TEGRA186_CLK_PLLD>; 917 clock-names = "dsi", "lp", "parent"; 918 resets = <&bpmp TEGRA186_RESET_DSID>; 919 reset-names = "dsi"; 920 status = "disabled"; 921 922 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 923 }; 924 }; 925 926 gpu@17000000 { 927 compatible = "nvidia,gp10b"; 928 reg = <0x0 0x17000000 0x0 0x1000000>, 929 <0x0 0x18000000 0x0 0x1000000>; 930 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 931 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 932 interrupt-names = "stall", "nonstall"; 933 934 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 935 <&bpmp TEGRA186_CLK_GPU>; 936 clock-names = "gpu", "pwr"; 937 resets = <&bpmp TEGRA186_RESET_GPU>; 938 reset-names = "gpu"; 939 status = "disabled"; 940 941 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 942 }; 943 944 sysram@30000000 { 945 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 946 reg = <0x0 0x30000000 0x0 0x50000>; 947 #address-cells = <2>; 948 #size-cells = <2>; 949 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 950 951 cpu_bpmp_tx: shmem@4e000 { 952 compatible = "nvidia,tegra186-bpmp-shmem"; 953 reg = <0x0 0x4e000 0x0 0x1000>; 954 label = "cpu-bpmp-tx"; 955 pool; 956 }; 957 958 cpu_bpmp_rx: shmem@4f000 { 959 compatible = "nvidia,tegra186-bpmp-shmem"; 960 reg = <0x0 0x4f000 0x0 0x1000>; 961 label = "cpu-bpmp-rx"; 962 pool; 963 }; 964 }; 965 966 cpus { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 cpu@0 { 971 compatible = "nvidia,tegra186-denver", "arm,armv8"; 972 device_type = "cpu"; 973 reg = <0x000>; 974 }; 975 976 cpu@1 { 977 compatible = "nvidia,tegra186-denver", "arm,armv8"; 978 device_type = "cpu"; 979 reg = <0x001>; 980 }; 981 982 cpu@2 { 983 compatible = "arm,cortex-a57", "arm,armv8"; 984 device_type = "cpu"; 985 reg = <0x100>; 986 }; 987 988 cpu@3 { 989 compatible = "arm,cortex-a57", "arm,armv8"; 990 device_type = "cpu"; 991 reg = <0x101>; 992 }; 993 994 cpu@4 { 995 compatible = "arm,cortex-a57", "arm,armv8"; 996 device_type = "cpu"; 997 reg = <0x102>; 998 }; 999 1000 cpu@5 { 1001 compatible = "arm,cortex-a57", "arm,armv8"; 1002 device_type = "cpu"; 1003 reg = <0x103>; 1004 }; 1005 }; 1006 1007 bpmp: bpmp { 1008 compatible = "nvidia,tegra186-bpmp"; 1009 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1010 TEGRA_HSP_DB_MASTER_BPMP>; 1011 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1012 #clock-cells = <1>; 1013 #reset-cells = <1>; 1014 #power-domain-cells = <1>; 1015 1016 bpmp_i2c: i2c { 1017 compatible = "nvidia,tegra186-bpmp-i2c"; 1018 nvidia,bpmp-bus-id = <5>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 bpmp_thermal: thermal { 1025 compatible = "nvidia,tegra186-bpmp-thermal"; 1026 #thermal-sensor-cells = <1>; 1027 }; 1028 }; 1029 1030 thermal-zones { 1031 a57 { 1032 polling-delay = <0>; 1033 polling-delay-passive = <1000>; 1034 1035 thermal-sensors = 1036 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1037 1038 trips { 1039 critical { 1040 temperature = <101000>; 1041 hysteresis = <0>; 1042 type = "critical"; 1043 }; 1044 }; 1045 1046 cooling-maps { 1047 }; 1048 }; 1049 1050 denver { 1051 polling-delay = <0>; 1052 polling-delay-passive = <1000>; 1053 1054 thermal-sensors = 1055 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1056 1057 trips { 1058 critical { 1059 temperature = <101000>; 1060 hysteresis = <0>; 1061 type = "critical"; 1062 }; 1063 }; 1064 1065 cooling-maps { 1066 }; 1067 }; 1068 1069 gpu { 1070 polling-delay = <0>; 1071 polling-delay-passive = <1000>; 1072 1073 thermal-sensors = 1074 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1075 1076 trips { 1077 critical { 1078 temperature = <101000>; 1079 hysteresis = <0>; 1080 type = "critical"; 1081 }; 1082 }; 1083 1084 cooling-maps { 1085 }; 1086 }; 1087 1088 pll { 1089 polling-delay = <0>; 1090 polling-delay-passive = <1000>; 1091 1092 thermal-sensors = 1093 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1094 1095 trips { 1096 critical { 1097 temperature = <101000>; 1098 hysteresis = <0>; 1099 type = "critical"; 1100 }; 1101 }; 1102 1103 cooling-maps { 1104 }; 1105 }; 1106 1107 always_on { 1108 polling-delay = <0>; 1109 polling-delay-passive = <1000>; 1110 1111 thermal-sensors = 1112 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1113 1114 trips { 1115 critical { 1116 temperature = <101000>; 1117 hysteresis = <0>; 1118 type = "critical"; 1119 }; 1120 }; 1121 1122 cooling-maps { 1123 }; 1124 }; 1125 }; 1126 1127 timer { 1128 compatible = "arm,armv8-timer"; 1129 interrupts = <GIC_PPI 13 1130 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1131 <GIC_PPI 14 1132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1133 <GIC_PPI 11 1134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1135 <GIC_PPI 10 1136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1137 interrupt-parent = <&gic>; 1138 }; 1139}; 1140