1#include <dt-bindings/clock/tegra186-clock.h> 2#include <dt-bindings/gpio/tegra186-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h> 5#include <dt-bindings/power/tegra186-powergate.h> 6#include <dt-bindings/reset/tegra186-reset.h> 7#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 8 9/ { 10 compatible = "nvidia,tegra186"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 gpio: gpio@2200000 { 16 compatible = "nvidia,tegra186-gpio"; 17 reg-names = "security", "gpio"; 18 reg = <0x0 0x2200000 0x0 0x10000>, 19 <0x0 0x2210000 0x0 0x10000>; 20 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 26 #interrupt-cells = <2>; 27 interrupt-controller; 28 #gpio-cells = <2>; 29 gpio-controller; 30 }; 31 32 ethernet@2490000 { 33 compatible = "nvidia,tegra186-eqos", 34 "snps,dwc-qos-ethernet-4.10"; 35 reg = <0x0 0x02490000 0x0 0x10000>; 36 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 37 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 38 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 39 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 40 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 41 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 42 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 43 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 44 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 45 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 46 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 47 <&bpmp TEGRA186_CLK_EQOS_AXI>, 48 <&bpmp TEGRA186_CLK_EQOS_RX>, 49 <&bpmp TEGRA186_CLK_EQOS_TX>, 50 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 51 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 52 resets = <&bpmp TEGRA186_RESET_EQOS>; 53 reset-names = "eqos"; 54 status = "disabled"; 55 56 snps,write-requests = <1>; 57 snps,read-requests = <3>; 58 snps,burst-map = <0x7>; 59 snps,txpbl = <32>; 60 snps,rxpbl = <8>; 61 }; 62 63 uarta: serial@3100000 { 64 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 65 reg = <0x0 0x03100000 0x0 0x40>; 66 reg-shift = <2>; 67 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&bpmp TEGRA186_CLK_UARTA>; 69 clock-names = "serial"; 70 resets = <&bpmp TEGRA186_RESET_UARTA>; 71 reset-names = "serial"; 72 status = "disabled"; 73 }; 74 75 uartb: serial@3110000 { 76 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 77 reg = <0x0 0x03110000 0x0 0x40>; 78 reg-shift = <2>; 79 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 80 clocks = <&bpmp TEGRA186_CLK_UARTB>; 81 clock-names = "serial"; 82 resets = <&bpmp TEGRA186_RESET_UARTB>; 83 reset-names = "serial"; 84 status = "disabled"; 85 }; 86 87 uartd: serial@3130000 { 88 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 89 reg = <0x0 0x03130000 0x0 0x40>; 90 reg-shift = <2>; 91 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 92 clocks = <&bpmp TEGRA186_CLK_UARTD>; 93 clock-names = "serial"; 94 resets = <&bpmp TEGRA186_RESET_UARTD>; 95 reset-names = "serial"; 96 status = "disabled"; 97 }; 98 99 uarte: serial@3140000 { 100 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 101 reg = <0x0 0x03140000 0x0 0x40>; 102 reg-shift = <2>; 103 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&bpmp TEGRA186_CLK_UARTE>; 105 clock-names = "serial"; 106 resets = <&bpmp TEGRA186_RESET_UARTE>; 107 reset-names = "serial"; 108 status = "disabled"; 109 }; 110 111 uartf: serial@3150000 { 112 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 113 reg = <0x0 0x03150000 0x0 0x40>; 114 reg-shift = <2>; 115 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&bpmp TEGRA186_CLK_UARTF>; 117 clock-names = "serial"; 118 resets = <&bpmp TEGRA186_RESET_UARTF>; 119 reset-names = "serial"; 120 status = "disabled"; 121 }; 122 123 gen1_i2c: i2c@3160000 { 124 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 125 reg = <0x0 0x03160000 0x0 0x10000>; 126 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 clocks = <&bpmp TEGRA186_CLK_I2C1>; 130 clock-names = "div-clk"; 131 resets = <&bpmp TEGRA186_RESET_I2C1>; 132 reset-names = "i2c"; 133 status = "disabled"; 134 }; 135 136 cam_i2c: i2c@3180000 { 137 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 138 reg = <0x0 0x03180000 0x0 0x10000>; 139 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 clocks = <&bpmp TEGRA186_CLK_I2C3>; 143 clock-names = "div-clk"; 144 resets = <&bpmp TEGRA186_RESET_I2C3>; 145 reset-names = "i2c"; 146 status = "disabled"; 147 }; 148 149 /* shares pads with dpaux1 */ 150 dp_aux_ch1_i2c: i2c@3190000 { 151 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 152 reg = <0x0 0x03190000 0x0 0x10000>; 153 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 clocks = <&bpmp TEGRA186_CLK_I2C4>; 157 clock-names = "div-clk"; 158 resets = <&bpmp TEGRA186_RESET_I2C4>; 159 reset-names = "i2c"; 160 status = "disabled"; 161 }; 162 163 /* controlled by BPMP, should not be enabled */ 164 pwr_i2c: i2c@31a0000 { 165 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 166 reg = <0x0 0x031a0000 0x0 0x10000>; 167 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clocks = <&bpmp TEGRA186_CLK_I2C5>; 171 clock-names = "div-clk"; 172 resets = <&bpmp TEGRA186_RESET_I2C5>; 173 reset-names = "i2c"; 174 status = "disabled"; 175 }; 176 177 /* shares pads with dpaux0 */ 178 dp_aux_ch0_i2c: i2c@31b0000 { 179 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 180 reg = <0x0 0x031b0000 0x0 0x10000>; 181 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 clocks = <&bpmp TEGRA186_CLK_I2C6>; 185 clock-names = "div-clk"; 186 resets = <&bpmp TEGRA186_RESET_I2C6>; 187 reset-names = "i2c"; 188 status = "disabled"; 189 }; 190 191 gen7_i2c: i2c@31c0000 { 192 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 193 reg = <0x0 0x031c0000 0x0 0x10000>; 194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 clocks = <&bpmp TEGRA186_CLK_I2C7>; 198 clock-names = "div-clk"; 199 resets = <&bpmp TEGRA186_RESET_I2C7>; 200 reset-names = "i2c"; 201 status = "disabled"; 202 }; 203 204 gen9_i2c: i2c@31e0000 { 205 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 206 reg = <0x0 0x031e0000 0x0 0x10000>; 207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 clocks = <&bpmp TEGRA186_CLK_I2C9>; 211 clock-names = "div-clk"; 212 resets = <&bpmp TEGRA186_RESET_I2C9>; 213 reset-names = "i2c"; 214 status = "disabled"; 215 }; 216 217 sdmmc1: sdhci@3400000 { 218 compatible = "nvidia,tegra186-sdhci"; 219 reg = <0x0 0x03400000 0x0 0x10000>; 220 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 222 clock-names = "sdhci"; 223 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 224 reset-names = "sdhci"; 225 status = "disabled"; 226 }; 227 228 sdmmc2: sdhci@3420000 { 229 compatible = "nvidia,tegra186-sdhci"; 230 reg = <0x0 0x03420000 0x0 0x10000>; 231 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 233 clock-names = "sdhci"; 234 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 235 reset-names = "sdhci"; 236 status = "disabled"; 237 }; 238 239 sdmmc3: sdhci@3440000 { 240 compatible = "nvidia,tegra186-sdhci"; 241 reg = <0x0 0x03440000 0x0 0x10000>; 242 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 244 clock-names = "sdhci"; 245 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 246 reset-names = "sdhci"; 247 status = "disabled"; 248 }; 249 250 sdmmc4: sdhci@3460000 { 251 compatible = "nvidia,tegra186-sdhci"; 252 reg = <0x0 0x03460000 0x0 0x10000>; 253 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 255 clock-names = "sdhci"; 256 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 257 reset-names = "sdhci"; 258 status = "disabled"; 259 }; 260 261 gic: interrupt-controller@3881000 { 262 compatible = "arm,gic-400"; 263 #interrupt-cells = <3>; 264 interrupt-controller; 265 reg = <0x0 0x03881000 0x0 0x1000>, 266 <0x0 0x03882000 0x0 0x2000>; 267 interrupts = <GIC_PPI 9 268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 269 interrupt-parent = <&gic>; 270 }; 271 272 hsp_top0: hsp@3c00000 { 273 compatible = "nvidia,tegra186-hsp"; 274 reg = <0x0 0x03c00000 0x0 0xa0000>; 275 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "doorbell"; 277 #mbox-cells = <2>; 278 status = "disabled"; 279 }; 280 281 gen2_i2c: i2c@c240000 { 282 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 283 reg = <0x0 0x0c240000 0x0 0x10000>; 284 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 clocks = <&bpmp TEGRA186_CLK_I2C2>; 288 clock-names = "div-clk"; 289 resets = <&bpmp TEGRA186_RESET_I2C2>; 290 reset-names = "i2c"; 291 status = "disabled"; 292 }; 293 294 gen8_i2c: i2c@c250000 { 295 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 296 reg = <0x0 0x0c250000 0x0 0x10000>; 297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&bpmp TEGRA186_CLK_I2C8>; 301 clock-names = "div-clk"; 302 resets = <&bpmp TEGRA186_RESET_I2C8>; 303 reset-names = "i2c"; 304 status = "disabled"; 305 }; 306 307 uartc: serial@c280000 { 308 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 309 reg = <0x0 0x0c280000 0x0 0x40>; 310 reg-shift = <2>; 311 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&bpmp TEGRA186_CLK_UARTC>; 313 clock-names = "serial"; 314 resets = <&bpmp TEGRA186_RESET_UARTC>; 315 reset-names = "serial"; 316 status = "disabled"; 317 }; 318 319 uartg: serial@c290000 { 320 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 321 reg = <0x0 0x0c290000 0x0 0x40>; 322 reg-shift = <2>; 323 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA186_CLK_UARTG>; 325 clock-names = "serial"; 326 resets = <&bpmp TEGRA186_RESET_UARTG>; 327 reset-names = "serial"; 328 status = "disabled"; 329 }; 330 331 gpio_aon: gpio@c2f0000 { 332 compatible = "nvidia,tegra186-gpio-aon"; 333 reg-names = "security", "gpio"; 334 reg = <0x0 0xc2f0000 0x0 0x1000>, 335 <0x0 0xc2f1000 0x0 0x1000>; 336 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 }; 342 343 pmc@c360000 { 344 compatible = "nvidia,tegra186-pmc"; 345 reg = <0 0x0c360000 0 0x10000>, 346 <0 0x0c370000 0 0x10000>, 347 <0 0x0c380000 0 0x10000>, 348 <0 0x0c390000 0 0x10000>; 349 reg-names = "pmc", "wake", "aotag", "scratch"; 350 }; 351 352 ccplex@e000000 { 353 compatible = "nvidia,tegra186-ccplex-cluster"; 354 reg = <0x0 0x0e000000 0x0 0x3fffff>; 355 356 nvidia,bpmp = <&bpmp>; 357 }; 358 359 pcie@10003000 { 360 compatible = "nvidia,tegra186-pcie"; 361 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 362 device_type = "pci"; 363 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 364 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 365 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 366 reg-names = "pads", "afi", "cs"; 367 368 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 369 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 370 interrupt-names = "intr", "msi"; 371 372 #interrupt-cells = <1>; 373 interrupt-map-mask = <0 0 0 0>; 374 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 375 376 bus-range = <0x00 0xff>; 377 #address-cells = <3>; 378 #size-cells = <2>; 379 380 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 381 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 382 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 383 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 384 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 385 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 386 387 clocks = <&bpmp TEGRA186_CLK_AFI>, 388 <&bpmp TEGRA186_CLK_PCIE>, 389 <&bpmp TEGRA186_CLK_PLLE>; 390 clock-names = "afi", "pex", "pll_e"; 391 392 resets = <&bpmp TEGRA186_RESET_AFI>, 393 <&bpmp TEGRA186_RESET_PCIE>, 394 <&bpmp TEGRA186_RESET_PCIEXCLK>; 395 reset-names = "afi", "pex", "pcie_x"; 396 397 status = "disabled"; 398 399 pci@1,0 { 400 device_type = "pci"; 401 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 402 reg = <0x000800 0 0 0 0>; 403 status = "disabled"; 404 405 #address-cells = <3>; 406 #size-cells = <2>; 407 ranges; 408 409 nvidia,num-lanes = <2>; 410 }; 411 412 pci@2,0 { 413 device_type = "pci"; 414 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 415 reg = <0x001000 0 0 0 0>; 416 status = "disabled"; 417 418 #address-cells = <3>; 419 #size-cells = <2>; 420 ranges; 421 422 nvidia,num-lanes = <1>; 423 }; 424 425 pci@3,0 { 426 device_type = "pci"; 427 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 428 reg = <0x001800 0 0 0 0>; 429 status = "disabled"; 430 431 #address-cells = <3>; 432 #size-cells = <2>; 433 ranges; 434 435 nvidia,num-lanes = <1>; 436 }; 437 }; 438 439 host1x@13e00000 { 440 compatible = "nvidia,tegra186-host1x", "simple-bus"; 441 reg = <0x0 0x13e00000 0x0 0x10000>, 442 <0x0 0x13e10000 0x0 0x10000>; 443 reg-names = "hypervisor", "vm"; 444 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 447 clock-names = "host1x"; 448 resets = <&bpmp TEGRA186_RESET_HOST1X>; 449 reset-names = "host1x"; 450 451 #address-cells = <1>; 452 #size-cells = <1>; 453 454 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 455 456 vic@15340000 { 457 compatible = "nvidia,tegra186-vic"; 458 reg = <0x15340000 0x40000>; 459 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&bpmp TEGRA186_CLK_VIC>; 461 clock-names = "vic"; 462 resets = <&bpmp TEGRA186_RESET_VIC>; 463 reset-names = "vic"; 464 465 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 466 }; 467 }; 468 469 gpu@17000000 { 470 compatible = "nvidia,gp10b"; 471 reg = <0x0 0x17000000 0x0 0x1000000>, 472 <0x0 0x18000000 0x0 0x1000000>; 473 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 474 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 475 interrupt-names = "stall", "nonstall"; 476 477 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 478 <&bpmp TEGRA186_CLK_GPU>; 479 clock-names = "gpu", "pwr"; 480 resets = <&bpmp TEGRA186_RESET_GPU>; 481 reset-names = "gpu"; 482 status = "disabled"; 483 484 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 485 }; 486 487 sysram@30000000 { 488 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 489 reg = <0x0 0x30000000 0x0 0x50000>; 490 #address-cells = <2>; 491 #size-cells = <2>; 492 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 493 494 cpu_bpmp_tx: shmem@4e000 { 495 compatible = "nvidia,tegra186-bpmp-shmem"; 496 reg = <0x0 0x4e000 0x0 0x1000>; 497 label = "cpu-bpmp-tx"; 498 pool; 499 }; 500 501 cpu_bpmp_rx: shmem@4f000 { 502 compatible = "nvidia,tegra186-bpmp-shmem"; 503 reg = <0x0 0x4f000 0x0 0x1000>; 504 label = "cpu-bpmp-rx"; 505 pool; 506 }; 507 }; 508 509 cpus { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 513 cpu@0 { 514 compatible = "nvidia,tegra186-denver", "arm,armv8"; 515 device_type = "cpu"; 516 reg = <0x000>; 517 }; 518 519 cpu@1 { 520 compatible = "nvidia,tegra186-denver", "arm,armv8"; 521 device_type = "cpu"; 522 reg = <0x001>; 523 }; 524 525 cpu@2 { 526 compatible = "arm,cortex-a57", "arm,armv8"; 527 device_type = "cpu"; 528 reg = <0x100>; 529 }; 530 531 cpu@3 { 532 compatible = "arm,cortex-a57", "arm,armv8"; 533 device_type = "cpu"; 534 reg = <0x101>; 535 }; 536 537 cpu@4 { 538 compatible = "arm,cortex-a57", "arm,armv8"; 539 device_type = "cpu"; 540 reg = <0x102>; 541 }; 542 543 cpu@5 { 544 compatible = "arm,cortex-a57", "arm,armv8"; 545 device_type = "cpu"; 546 reg = <0x103>; 547 }; 548 }; 549 550 bpmp: bpmp { 551 compatible = "nvidia,tegra186-bpmp"; 552 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 553 TEGRA_HSP_DB_MASTER_BPMP>; 554 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 555 #clock-cells = <1>; 556 #reset-cells = <1>; 557 #power-domain-cells = <1>; 558 559 bpmp_i2c: i2c { 560 compatible = "nvidia,tegra186-bpmp-i2c"; 561 nvidia,bpmp-bus-id = <5>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 bpmp_thermal: thermal { 568 compatible = "nvidia,tegra186-bpmp-thermal"; 569 #thermal-sensor-cells = <1>; 570 }; 571 }; 572 573 thermal-zones { 574 a57 { 575 polling-delay = <0>; 576 polling-delay-passive = <1000>; 577 578 thermal-sensors = 579 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 580 581 trips { 582 critical { 583 temperature = <101000>; 584 hysteresis = <0>; 585 type = "critical"; 586 }; 587 }; 588 589 cooling-maps { 590 }; 591 }; 592 593 denver { 594 polling-delay = <0>; 595 polling-delay-passive = <1000>; 596 597 thermal-sensors = 598 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 599 600 trips { 601 critical { 602 temperature = <101000>; 603 hysteresis = <0>; 604 type = "critical"; 605 }; 606 }; 607 608 cooling-maps { 609 }; 610 }; 611 612 gpu { 613 polling-delay = <0>; 614 polling-delay-passive = <1000>; 615 616 thermal-sensors = 617 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 618 619 trips { 620 critical { 621 temperature = <101000>; 622 hysteresis = <0>; 623 type = "critical"; 624 }; 625 }; 626 627 cooling-maps { 628 }; 629 }; 630 631 pll { 632 polling-delay = <0>; 633 polling-delay-passive = <1000>; 634 635 thermal-sensors = 636 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 637 638 trips { 639 critical { 640 temperature = <101000>; 641 hysteresis = <0>; 642 type = "critical"; 643 }; 644 }; 645 646 cooling-maps { 647 }; 648 }; 649 650 always_on { 651 polling-delay = <0>; 652 polling-delay-passive = <1000>; 653 654 thermal-sensors = 655 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 656 657 trips { 658 critical { 659 temperature = <101000>; 660 hysteresis = <0>; 661 type = "critical"; 662 }; 663 }; 664 665 cooling-maps { 666 }; 667 }; 668 }; 669 670 timer { 671 compatible = "arm,armv8-timer"; 672 interrupts = <GIC_PPI 13 673 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 674 <GIC_PPI 14 675 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 676 <GIC_PPI 11 677 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 678 <GIC_PPI 10 679 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 680 interrupt-parent = <&gic>; 681 }; 682}; 683