1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/power/tegra186-powergate.h> 7#include <dt-bindings/reset/tegra186-reset.h> 8#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra186"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 misc@100000 { 17 compatible = "nvidia,tegra186-misc"; 18 reg = <0x0 0x00100000 0x0 0xf000>, 19 <0x0 0x0010f000 0x0 0x1000>; 20 }; 21 22 gpio: gpio@2200000 { 23 compatible = "nvidia,tegra186-gpio"; 24 reg-names = "security", "gpio"; 25 reg = <0x0 0x2200000 0x0 0x10000>, 26 <0x0 0x2210000 0x0 0x10000>; 27 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 33 #interrupt-cells = <2>; 34 interrupt-controller; 35 #gpio-cells = <2>; 36 gpio-controller; 37 }; 38 39 ethernet@2490000 { 40 compatible = "nvidia,tegra186-eqos", 41 "snps,dwc-qos-ethernet-4.10"; 42 reg = <0x0 0x02490000 0x0 0x10000>; 43 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 44 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 45 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 46 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 47 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 48 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 49 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 50 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 51 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 52 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 53 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 54 <&bpmp TEGRA186_CLK_EQOS_AXI>, 55 <&bpmp TEGRA186_CLK_EQOS_RX>, 56 <&bpmp TEGRA186_CLK_EQOS_TX>, 57 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 58 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 59 resets = <&bpmp TEGRA186_RESET_EQOS>; 60 reset-names = "eqos"; 61 status = "disabled"; 62 63 snps,write-requests = <1>; 64 snps,read-requests = <3>; 65 snps,burst-map = <0x7>; 66 snps,txpbl = <32>; 67 snps,rxpbl = <8>; 68 }; 69 70 uarta: serial@3100000 { 71 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 72 reg = <0x0 0x03100000 0x0 0x40>; 73 reg-shift = <2>; 74 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 75 clocks = <&bpmp TEGRA186_CLK_UARTA>; 76 clock-names = "serial"; 77 resets = <&bpmp TEGRA186_RESET_UARTA>; 78 reset-names = "serial"; 79 status = "disabled"; 80 }; 81 82 uartb: serial@3110000 { 83 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 84 reg = <0x0 0x03110000 0x0 0x40>; 85 reg-shift = <2>; 86 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 87 clocks = <&bpmp TEGRA186_CLK_UARTB>; 88 clock-names = "serial"; 89 resets = <&bpmp TEGRA186_RESET_UARTB>; 90 reset-names = "serial"; 91 status = "disabled"; 92 }; 93 94 uartd: serial@3130000 { 95 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 96 reg = <0x0 0x03130000 0x0 0x40>; 97 reg-shift = <2>; 98 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&bpmp TEGRA186_CLK_UARTD>; 100 clock-names = "serial"; 101 resets = <&bpmp TEGRA186_RESET_UARTD>; 102 reset-names = "serial"; 103 status = "disabled"; 104 }; 105 106 uarte: serial@3140000 { 107 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 108 reg = <0x0 0x03140000 0x0 0x40>; 109 reg-shift = <2>; 110 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&bpmp TEGRA186_CLK_UARTE>; 112 clock-names = "serial"; 113 resets = <&bpmp TEGRA186_RESET_UARTE>; 114 reset-names = "serial"; 115 status = "disabled"; 116 }; 117 118 uartf: serial@3150000 { 119 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 120 reg = <0x0 0x03150000 0x0 0x40>; 121 reg-shift = <2>; 122 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&bpmp TEGRA186_CLK_UARTF>; 124 clock-names = "serial"; 125 resets = <&bpmp TEGRA186_RESET_UARTF>; 126 reset-names = "serial"; 127 status = "disabled"; 128 }; 129 130 gen1_i2c: i2c@3160000 { 131 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 132 reg = <0x0 0x03160000 0x0 0x10000>; 133 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 clocks = <&bpmp TEGRA186_CLK_I2C1>; 137 clock-names = "div-clk"; 138 resets = <&bpmp TEGRA186_RESET_I2C1>; 139 reset-names = "i2c"; 140 status = "disabled"; 141 }; 142 143 cam_i2c: i2c@3180000 { 144 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 145 reg = <0x0 0x03180000 0x0 0x10000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 clocks = <&bpmp TEGRA186_CLK_I2C3>; 150 clock-names = "div-clk"; 151 resets = <&bpmp TEGRA186_RESET_I2C3>; 152 reset-names = "i2c"; 153 status = "disabled"; 154 }; 155 156 /* shares pads with dpaux1 */ 157 dp_aux_ch1_i2c: i2c@3190000 { 158 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 159 reg = <0x0 0x03190000 0x0 0x10000>; 160 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&bpmp TEGRA186_CLK_I2C4>; 164 clock-names = "div-clk"; 165 resets = <&bpmp TEGRA186_RESET_I2C4>; 166 reset-names = "i2c"; 167 status = "disabled"; 168 }; 169 170 /* controlled by BPMP, should not be enabled */ 171 pwr_i2c: i2c@31a0000 { 172 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 173 reg = <0x0 0x031a0000 0x0 0x10000>; 174 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clocks = <&bpmp TEGRA186_CLK_I2C5>; 178 clock-names = "div-clk"; 179 resets = <&bpmp TEGRA186_RESET_I2C5>; 180 reset-names = "i2c"; 181 status = "disabled"; 182 }; 183 184 /* shares pads with dpaux0 */ 185 dp_aux_ch0_i2c: i2c@31b0000 { 186 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 187 reg = <0x0 0x031b0000 0x0 0x10000>; 188 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 clocks = <&bpmp TEGRA186_CLK_I2C6>; 192 clock-names = "div-clk"; 193 resets = <&bpmp TEGRA186_RESET_I2C6>; 194 reset-names = "i2c"; 195 status = "disabled"; 196 }; 197 198 gen7_i2c: i2c@31c0000 { 199 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 200 reg = <0x0 0x031c0000 0x0 0x10000>; 201 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 clocks = <&bpmp TEGRA186_CLK_I2C7>; 205 clock-names = "div-clk"; 206 resets = <&bpmp TEGRA186_RESET_I2C7>; 207 reset-names = "i2c"; 208 status = "disabled"; 209 }; 210 211 gen9_i2c: i2c@31e0000 { 212 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 213 reg = <0x0 0x031e0000 0x0 0x10000>; 214 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 clocks = <&bpmp TEGRA186_CLK_I2C9>; 218 clock-names = "div-clk"; 219 resets = <&bpmp TEGRA186_RESET_I2C9>; 220 reset-names = "i2c"; 221 status = "disabled"; 222 }; 223 224 sdmmc1: sdhci@3400000 { 225 compatible = "nvidia,tegra186-sdhci"; 226 reg = <0x0 0x03400000 0x0 0x10000>; 227 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 229 clock-names = "sdhci"; 230 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 231 reset-names = "sdhci"; 232 status = "disabled"; 233 }; 234 235 sdmmc2: sdhci@3420000 { 236 compatible = "nvidia,tegra186-sdhci"; 237 reg = <0x0 0x03420000 0x0 0x10000>; 238 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 240 clock-names = "sdhci"; 241 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 242 reset-names = "sdhci"; 243 status = "disabled"; 244 }; 245 246 sdmmc3: sdhci@3440000 { 247 compatible = "nvidia,tegra186-sdhci"; 248 reg = <0x0 0x03440000 0x0 0x10000>; 249 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 251 clock-names = "sdhci"; 252 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 253 reset-names = "sdhci"; 254 status = "disabled"; 255 }; 256 257 sdmmc4: sdhci@3460000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03460000 0x0 0x10000>; 260 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 264 reset-names = "sdhci"; 265 status = "disabled"; 266 }; 267 268 gic: interrupt-controller@3881000 { 269 compatible = "arm,gic-400"; 270 #interrupt-cells = <3>; 271 interrupt-controller; 272 reg = <0x0 0x03881000 0x0 0x1000>, 273 <0x0 0x03882000 0x0 0x2000>; 274 interrupts = <GIC_PPI 9 275 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 276 interrupt-parent = <&gic>; 277 }; 278 279 hsp_top0: hsp@3c00000 { 280 compatible = "nvidia,tegra186-hsp"; 281 reg = <0x0 0x03c00000 0x0 0xa0000>; 282 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "doorbell"; 284 #mbox-cells = <2>; 285 status = "disabled"; 286 }; 287 288 gen2_i2c: i2c@c240000 { 289 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 290 reg = <0x0 0x0c240000 0x0 0x10000>; 291 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clocks = <&bpmp TEGRA186_CLK_I2C2>; 295 clock-names = "div-clk"; 296 resets = <&bpmp TEGRA186_RESET_I2C2>; 297 reset-names = "i2c"; 298 status = "disabled"; 299 }; 300 301 gen8_i2c: i2c@c250000 { 302 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 303 reg = <0x0 0x0c250000 0x0 0x10000>; 304 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 clocks = <&bpmp TEGRA186_CLK_I2C8>; 308 clock-names = "div-clk"; 309 resets = <&bpmp TEGRA186_RESET_I2C8>; 310 reset-names = "i2c"; 311 status = "disabled"; 312 }; 313 314 uartc: serial@c280000 { 315 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 316 reg = <0x0 0x0c280000 0x0 0x40>; 317 reg-shift = <2>; 318 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&bpmp TEGRA186_CLK_UARTC>; 320 clock-names = "serial"; 321 resets = <&bpmp TEGRA186_RESET_UARTC>; 322 reset-names = "serial"; 323 status = "disabled"; 324 }; 325 326 uartg: serial@c290000 { 327 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 328 reg = <0x0 0x0c290000 0x0 0x40>; 329 reg-shift = <2>; 330 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&bpmp TEGRA186_CLK_UARTG>; 332 clock-names = "serial"; 333 resets = <&bpmp TEGRA186_RESET_UARTG>; 334 reset-names = "serial"; 335 status = "disabled"; 336 }; 337 338 gpio_aon: gpio@c2f0000 { 339 compatible = "nvidia,tegra186-gpio-aon"; 340 reg-names = "security", "gpio"; 341 reg = <0x0 0xc2f0000 0x0 0x1000>, 342 <0x0 0xc2f1000 0x0 0x1000>; 343 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 }; 349 350 pmc@c360000 { 351 compatible = "nvidia,tegra186-pmc"; 352 reg = <0 0x0c360000 0 0x10000>, 353 <0 0x0c370000 0 0x10000>, 354 <0 0x0c380000 0 0x10000>, 355 <0 0x0c390000 0 0x10000>; 356 reg-names = "pmc", "wake", "aotag", "scratch"; 357 }; 358 359 ccplex@e000000 { 360 compatible = "nvidia,tegra186-ccplex-cluster"; 361 reg = <0x0 0x0e000000 0x0 0x3fffff>; 362 363 nvidia,bpmp = <&bpmp>; 364 }; 365 366 pcie@10003000 { 367 compatible = "nvidia,tegra186-pcie"; 368 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 369 device_type = "pci"; 370 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 371 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 372 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 373 reg-names = "pads", "afi", "cs"; 374 375 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 376 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 377 interrupt-names = "intr", "msi"; 378 379 #interrupt-cells = <1>; 380 interrupt-map-mask = <0 0 0 0>; 381 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 382 383 bus-range = <0x00 0xff>; 384 #address-cells = <3>; 385 #size-cells = <2>; 386 387 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 388 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 389 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 390 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 391 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 392 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 393 394 clocks = <&bpmp TEGRA186_CLK_AFI>, 395 <&bpmp TEGRA186_CLK_PCIE>, 396 <&bpmp TEGRA186_CLK_PLLE>; 397 clock-names = "afi", "pex", "pll_e"; 398 399 resets = <&bpmp TEGRA186_RESET_AFI>, 400 <&bpmp TEGRA186_RESET_PCIE>, 401 <&bpmp TEGRA186_RESET_PCIEXCLK>; 402 reset-names = "afi", "pex", "pcie_x"; 403 404 status = "disabled"; 405 406 pci@1,0 { 407 device_type = "pci"; 408 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 409 reg = <0x000800 0 0 0 0>; 410 status = "disabled"; 411 412 #address-cells = <3>; 413 #size-cells = <2>; 414 ranges; 415 416 nvidia,num-lanes = <2>; 417 }; 418 419 pci@2,0 { 420 device_type = "pci"; 421 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 422 reg = <0x001000 0 0 0 0>; 423 status = "disabled"; 424 425 #address-cells = <3>; 426 #size-cells = <2>; 427 ranges; 428 429 nvidia,num-lanes = <1>; 430 }; 431 432 pci@3,0 { 433 device_type = "pci"; 434 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 435 reg = <0x001800 0 0 0 0>; 436 status = "disabled"; 437 438 #address-cells = <3>; 439 #size-cells = <2>; 440 ranges; 441 442 nvidia,num-lanes = <1>; 443 }; 444 }; 445 446 host1x@13e00000 { 447 compatible = "nvidia,tegra186-host1x", "simple-bus"; 448 reg = <0x0 0x13e00000 0x0 0x10000>, 449 <0x0 0x13e10000 0x0 0x10000>; 450 reg-names = "hypervisor", "vm"; 451 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 454 clock-names = "host1x"; 455 resets = <&bpmp TEGRA186_RESET_HOST1X>; 456 reset-names = "host1x"; 457 458 #address-cells = <1>; 459 #size-cells = <1>; 460 461 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 462 463 vic@15340000 { 464 compatible = "nvidia,tegra186-vic"; 465 reg = <0x15340000 0x40000>; 466 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&bpmp TEGRA186_CLK_VIC>; 468 clock-names = "vic"; 469 resets = <&bpmp TEGRA186_RESET_VIC>; 470 reset-names = "vic"; 471 472 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 473 }; 474 }; 475 476 gpu@17000000 { 477 compatible = "nvidia,gp10b"; 478 reg = <0x0 0x17000000 0x0 0x1000000>, 479 <0x0 0x18000000 0x0 0x1000000>; 480 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 481 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "stall", "nonstall"; 483 484 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 485 <&bpmp TEGRA186_CLK_GPU>; 486 clock-names = "gpu", "pwr"; 487 resets = <&bpmp TEGRA186_RESET_GPU>; 488 reset-names = "gpu"; 489 status = "disabled"; 490 491 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 492 }; 493 494 sysram@30000000 { 495 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 496 reg = <0x0 0x30000000 0x0 0x50000>; 497 #address-cells = <2>; 498 #size-cells = <2>; 499 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 500 501 cpu_bpmp_tx: shmem@4e000 { 502 compatible = "nvidia,tegra186-bpmp-shmem"; 503 reg = <0x0 0x4e000 0x0 0x1000>; 504 label = "cpu-bpmp-tx"; 505 pool; 506 }; 507 508 cpu_bpmp_rx: shmem@4f000 { 509 compatible = "nvidia,tegra186-bpmp-shmem"; 510 reg = <0x0 0x4f000 0x0 0x1000>; 511 label = "cpu-bpmp-rx"; 512 pool; 513 }; 514 }; 515 516 cpus { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 520 cpu@0 { 521 compatible = "nvidia,tegra186-denver", "arm,armv8"; 522 device_type = "cpu"; 523 reg = <0x000>; 524 }; 525 526 cpu@1 { 527 compatible = "nvidia,tegra186-denver", "arm,armv8"; 528 device_type = "cpu"; 529 reg = <0x001>; 530 }; 531 532 cpu@2 { 533 compatible = "arm,cortex-a57", "arm,armv8"; 534 device_type = "cpu"; 535 reg = <0x100>; 536 }; 537 538 cpu@3 { 539 compatible = "arm,cortex-a57", "arm,armv8"; 540 device_type = "cpu"; 541 reg = <0x101>; 542 }; 543 544 cpu@4 { 545 compatible = "arm,cortex-a57", "arm,armv8"; 546 device_type = "cpu"; 547 reg = <0x102>; 548 }; 549 550 cpu@5 { 551 compatible = "arm,cortex-a57", "arm,armv8"; 552 device_type = "cpu"; 553 reg = <0x103>; 554 }; 555 }; 556 557 bpmp: bpmp { 558 compatible = "nvidia,tegra186-bpmp"; 559 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 560 TEGRA_HSP_DB_MASTER_BPMP>; 561 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 562 #clock-cells = <1>; 563 #reset-cells = <1>; 564 #power-domain-cells = <1>; 565 566 bpmp_i2c: i2c { 567 compatible = "nvidia,tegra186-bpmp-i2c"; 568 nvidia,bpmp-bus-id = <5>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 status = "disabled"; 572 }; 573 574 bpmp_thermal: thermal { 575 compatible = "nvidia,tegra186-bpmp-thermal"; 576 #thermal-sensor-cells = <1>; 577 }; 578 }; 579 580 thermal-zones { 581 a57 { 582 polling-delay = <0>; 583 polling-delay-passive = <1000>; 584 585 thermal-sensors = 586 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 587 588 trips { 589 critical { 590 temperature = <101000>; 591 hysteresis = <0>; 592 type = "critical"; 593 }; 594 }; 595 596 cooling-maps { 597 }; 598 }; 599 600 denver { 601 polling-delay = <0>; 602 polling-delay-passive = <1000>; 603 604 thermal-sensors = 605 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 606 607 trips { 608 critical { 609 temperature = <101000>; 610 hysteresis = <0>; 611 type = "critical"; 612 }; 613 }; 614 615 cooling-maps { 616 }; 617 }; 618 619 gpu { 620 polling-delay = <0>; 621 polling-delay-passive = <1000>; 622 623 thermal-sensors = 624 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 625 626 trips { 627 critical { 628 temperature = <101000>; 629 hysteresis = <0>; 630 type = "critical"; 631 }; 632 }; 633 634 cooling-maps { 635 }; 636 }; 637 638 pll { 639 polling-delay = <0>; 640 polling-delay-passive = <1000>; 641 642 thermal-sensors = 643 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 644 645 trips { 646 critical { 647 temperature = <101000>; 648 hysteresis = <0>; 649 type = "critical"; 650 }; 651 }; 652 653 cooling-maps { 654 }; 655 }; 656 657 always_on { 658 polling-delay = <0>; 659 polling-delay-passive = <1000>; 660 661 thermal-sensors = 662 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 663 664 trips { 665 critical { 666 temperature = <101000>; 667 hysteresis = <0>; 668 type = "critical"; 669 }; 670 }; 671 672 cooling-maps { 673 }; 674 }; 675 }; 676 677 timer { 678 compatible = "arm,armv8-timer"; 679 interrupts = <GIC_PPI 13 680 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 681 <GIC_PPI 14 682 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 683 <GIC_PPI 11 684 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 685 <GIC_PPI 10 686 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 687 interrupt-parent = <&gic>; 688 }; 689}; 690