1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 status = "disabled"; 244 }; 245 246 sdmmc2: sdhci@3420000 { 247 compatible = "nvidia,tegra186-sdhci"; 248 reg = <0x0 0x03420000 0x0 0x10000>; 249 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 251 clock-names = "sdhci"; 252 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 253 reset-names = "sdhci"; 254 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 255 pinctrl-0 = <&sdmmc2_3v3>; 256 pinctrl-1 = <&sdmmc2_1v8>; 257 status = "disabled"; 258 }; 259 260 sdmmc3: sdhci@3440000 { 261 compatible = "nvidia,tegra186-sdhci"; 262 reg = <0x0 0x03440000 0x0 0x10000>; 263 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 265 clock-names = "sdhci"; 266 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 267 reset-names = "sdhci"; 268 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 269 pinctrl-0 = <&sdmmc3_3v3>; 270 pinctrl-1 = <&sdmmc3_1v8>; 271 status = "disabled"; 272 }; 273 274 sdmmc4: sdhci@3460000 { 275 compatible = "nvidia,tegra186-sdhci"; 276 reg = <0x0 0x03460000 0x0 0x10000>; 277 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 279 clock-names = "sdhci"; 280 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 281 reset-names = "sdhci"; 282 status = "disabled"; 283 }; 284 285 fuse@3820000 { 286 compatible = "nvidia,tegra186-efuse"; 287 reg = <0x0 0x03820000 0x0 0x10000>; 288 clocks = <&bpmp TEGRA186_CLK_FUSE>; 289 clock-names = "fuse"; 290 }; 291 292 gic: interrupt-controller@3881000 { 293 compatible = "arm,gic-400"; 294 #interrupt-cells = <3>; 295 interrupt-controller; 296 reg = <0x0 0x03881000 0x0 0x1000>, 297 <0x0 0x03882000 0x0 0x2000>; 298 interrupts = <GIC_PPI 9 299 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 300 interrupt-parent = <&gic>; 301 }; 302 303 hsp_top0: hsp@3c00000 { 304 compatible = "nvidia,tegra186-hsp"; 305 reg = <0x0 0x03c00000 0x0 0xa0000>; 306 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "doorbell"; 308 #mbox-cells = <2>; 309 status = "disabled"; 310 }; 311 312 gen2_i2c: i2c@c240000 { 313 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 314 reg = <0x0 0x0c240000 0x0 0x10000>; 315 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 clocks = <&bpmp TEGRA186_CLK_I2C2>; 319 clock-names = "div-clk"; 320 resets = <&bpmp TEGRA186_RESET_I2C2>; 321 reset-names = "i2c"; 322 status = "disabled"; 323 }; 324 325 gen8_i2c: i2c@c250000 { 326 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 327 reg = <0x0 0x0c250000 0x0 0x10000>; 328 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 clocks = <&bpmp TEGRA186_CLK_I2C8>; 332 clock-names = "div-clk"; 333 resets = <&bpmp TEGRA186_RESET_I2C8>; 334 reset-names = "i2c"; 335 status = "disabled"; 336 }; 337 338 uartc: serial@c280000 { 339 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 340 reg = <0x0 0x0c280000 0x0 0x40>; 341 reg-shift = <2>; 342 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&bpmp TEGRA186_CLK_UARTC>; 344 clock-names = "serial"; 345 resets = <&bpmp TEGRA186_RESET_UARTC>; 346 reset-names = "serial"; 347 status = "disabled"; 348 }; 349 350 uartg: serial@c290000 { 351 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 352 reg = <0x0 0x0c290000 0x0 0x40>; 353 reg-shift = <2>; 354 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&bpmp TEGRA186_CLK_UARTG>; 356 clock-names = "serial"; 357 resets = <&bpmp TEGRA186_RESET_UARTG>; 358 reset-names = "serial"; 359 status = "disabled"; 360 }; 361 362 gpio_aon: gpio@c2f0000 { 363 compatible = "nvidia,tegra186-gpio-aon"; 364 reg-names = "security", "gpio"; 365 reg = <0x0 0xc2f0000 0x0 0x1000>, 366 <0x0 0xc2f1000 0x0 0x1000>; 367 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 }; 373 374 pmc@c360000 { 375 compatible = "nvidia,tegra186-pmc"; 376 reg = <0 0x0c360000 0 0x10000>, 377 <0 0x0c370000 0 0x10000>, 378 <0 0x0c380000 0 0x10000>, 379 <0 0x0c390000 0 0x10000>; 380 reg-names = "pmc", "wake", "aotag", "scratch"; 381 382 sdmmc1_3v3: sdmmc1-3v3 { 383 pins = "sdmmc1-hv"; 384 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 385 }; 386 387 sdmmc1_1v8: sdmmc1-1v8 { 388 pins = "sdmmc1-hv"; 389 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 390 }; 391 392 sdmmc2_3v3: sdmmc2-3v3 { 393 pins = "sdmmc2-hv"; 394 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 395 }; 396 397 sdmmc2_1v8: sdmmc2-1v8 { 398 pins = "sdmmc2-hv"; 399 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 400 }; 401 402 sdmmc3_3v3: sdmmc3-3v3 { 403 pins = "sdmmc3-hv"; 404 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 405 }; 406 407 sdmmc3_1v8: sdmmc3-1v8 { 408 pins = "sdmmc3-hv"; 409 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 410 }; 411 }; 412 413 ccplex@e000000 { 414 compatible = "nvidia,tegra186-ccplex-cluster"; 415 reg = <0x0 0x0e000000 0x0 0x3fffff>; 416 417 nvidia,bpmp = <&bpmp>; 418 }; 419 420 pcie@10003000 { 421 compatible = "nvidia,tegra186-pcie"; 422 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 423 device_type = "pci"; 424 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 425 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 426 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 427 reg-names = "pads", "afi", "cs"; 428 429 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 430 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 431 interrupt-names = "intr", "msi"; 432 433 #interrupt-cells = <1>; 434 interrupt-map-mask = <0 0 0 0>; 435 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 436 437 bus-range = <0x00 0xff>; 438 #address-cells = <3>; 439 #size-cells = <2>; 440 441 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 442 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 443 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 444 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 445 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 446 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 447 448 clocks = <&bpmp TEGRA186_CLK_AFI>, 449 <&bpmp TEGRA186_CLK_PCIE>, 450 <&bpmp TEGRA186_CLK_PLLE>; 451 clock-names = "afi", "pex", "pll_e"; 452 453 resets = <&bpmp TEGRA186_RESET_AFI>, 454 <&bpmp TEGRA186_RESET_PCIE>, 455 <&bpmp TEGRA186_RESET_PCIEXCLK>; 456 reset-names = "afi", "pex", "pcie_x"; 457 458 status = "disabled"; 459 460 pci@1,0 { 461 device_type = "pci"; 462 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 463 reg = <0x000800 0 0 0 0>; 464 status = "disabled"; 465 466 #address-cells = <3>; 467 #size-cells = <2>; 468 ranges; 469 470 nvidia,num-lanes = <2>; 471 }; 472 473 pci@2,0 { 474 device_type = "pci"; 475 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 476 reg = <0x001000 0 0 0 0>; 477 status = "disabled"; 478 479 #address-cells = <3>; 480 #size-cells = <2>; 481 ranges; 482 483 nvidia,num-lanes = <1>; 484 }; 485 486 pci@3,0 { 487 device_type = "pci"; 488 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 489 reg = <0x001800 0 0 0 0>; 490 status = "disabled"; 491 492 #address-cells = <3>; 493 #size-cells = <2>; 494 ranges; 495 496 nvidia,num-lanes = <1>; 497 }; 498 }; 499 500 smmu: iommu@12000000 { 501 compatible = "arm,mmu-500"; 502 reg = <0 0x12000000 0 0x800000>; 503 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 568 stream-match-mask = <0x7f80>; 569 #global-interrupts = <1>; 570 #iommu-cells = <1>; 571 }; 572 573 host1x@13e00000 { 574 compatible = "nvidia,tegra186-host1x", "simple-bus"; 575 reg = <0x0 0x13e00000 0x0 0x10000>, 576 <0x0 0x13e10000 0x0 0x10000>; 577 reg-names = "hypervisor", "vm"; 578 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 581 clock-names = "host1x"; 582 resets = <&bpmp TEGRA186_RESET_HOST1X>; 583 reset-names = "host1x"; 584 585 #address-cells = <1>; 586 #size-cells = <1>; 587 588 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 589 iommus = <&smmu TEGRA186_SID_HOST1X>; 590 591 dpaux1: dpaux@15040000 { 592 compatible = "nvidia,tegra186-dpaux"; 593 reg = <0x15040000 0x10000>; 594 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 596 <&bpmp TEGRA186_CLK_PLLDP>; 597 clock-names = "dpaux", "parent"; 598 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 599 reset-names = "dpaux"; 600 status = "disabled"; 601 602 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 603 604 state_dpaux1_aux: pinmux-aux { 605 groups = "dpaux-io"; 606 function = "aux"; 607 }; 608 609 state_dpaux1_i2c: pinmux-i2c { 610 groups = "dpaux-io"; 611 function = "i2c"; 612 }; 613 614 state_dpaux1_off: pinmux-off { 615 groups = "dpaux-io"; 616 function = "off"; 617 }; 618 619 i2c-bus { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 }; 623 }; 624 625 display-hub@15200000 { 626 compatible = "nvidia,tegra186-display", "simple-bus"; 627 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 628 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 629 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 630 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 631 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 632 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 633 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 634 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 635 "wgrp3", "wgrp4", "wgrp5"; 636 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 637 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 638 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 639 clock-names = "disp", "dsc", "hub"; 640 status = "disabled"; 641 642 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 643 644 #address-cells = <1>; 645 #size-cells = <1>; 646 647 ranges = <0x15200000 0x15200000 0x40000>; 648 649 display@15200000 { 650 compatible = "nvidia,tegra186-dc"; 651 reg = <0x15200000 0x10000>; 652 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 654 clock-names = "dc"; 655 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 656 reset-names = "dc"; 657 658 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 659 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 660 661 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 662 nvidia,head = <0>; 663 }; 664 665 display@15210000 { 666 compatible = "nvidia,tegra186-dc"; 667 reg = <0x15210000 0x10000>; 668 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 670 clock-names = "dc"; 671 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 672 reset-names = "dc"; 673 674 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 675 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 676 677 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 678 nvidia,head = <1>; 679 }; 680 681 display@15220000 { 682 compatible = "nvidia,tegra186-dc"; 683 reg = <0x15220000 0x10000>; 684 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 686 clock-names = "dc"; 687 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 688 reset-names = "dc"; 689 690 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 691 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 692 693 nvidia,outputs = <&sor0 &sor1>; 694 nvidia,head = <2>; 695 }; 696 }; 697 698 dsia: dsi@15300000 { 699 compatible = "nvidia,tegra186-dsi"; 700 reg = <0x15300000 0x10000>; 701 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&bpmp TEGRA186_CLK_DSI>, 703 <&bpmp TEGRA186_CLK_DSIA_LP>, 704 <&bpmp TEGRA186_CLK_PLLD>; 705 clock-names = "dsi", "lp", "parent"; 706 resets = <&bpmp TEGRA186_RESET_DSI>; 707 reset-names = "dsi"; 708 status = "disabled"; 709 710 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 711 }; 712 713 vic@15340000 { 714 compatible = "nvidia,tegra186-vic"; 715 reg = <0x15340000 0x40000>; 716 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&bpmp TEGRA186_CLK_VIC>; 718 clock-names = "vic"; 719 resets = <&bpmp TEGRA186_RESET_VIC>; 720 reset-names = "vic"; 721 722 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 723 }; 724 725 dsib: dsi@15400000 { 726 compatible = "nvidia,tegra186-dsi"; 727 reg = <0x15400000 0x10000>; 728 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&bpmp TEGRA186_CLK_DSIB>, 730 <&bpmp TEGRA186_CLK_DSIB_LP>, 731 <&bpmp TEGRA186_CLK_PLLD>; 732 clock-names = "dsi", "lp", "parent"; 733 resets = <&bpmp TEGRA186_RESET_DSIB>; 734 reset-names = "dsi"; 735 status = "disabled"; 736 737 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 738 }; 739 740 sor0: sor@15540000 { 741 compatible = "nvidia,tegra186-sor"; 742 reg = <0x15540000 0x10000>; 743 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&bpmp TEGRA186_CLK_SOR0>, 745 <&bpmp TEGRA186_CLK_SOR0_OUT>, 746 <&bpmp TEGRA186_CLK_PLLD2>, 747 <&bpmp TEGRA186_CLK_PLLDP>, 748 <&bpmp TEGRA186_CLK_SOR_SAFE>, 749 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 750 clock-names = "sor", "out", "parent", "dp", "safe", 751 "pad"; 752 resets = <&bpmp TEGRA186_RESET_SOR0>; 753 reset-names = "sor"; 754 pinctrl-0 = <&state_dpaux_aux>; 755 pinctrl-1 = <&state_dpaux_i2c>; 756 pinctrl-2 = <&state_dpaux_off>; 757 pinctrl-names = "aux", "i2c", "off"; 758 status = "disabled"; 759 760 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 761 nvidia,interface = <0>; 762 }; 763 764 sor1: sor@15580000 { 765 compatible = "nvidia,tegra186-sor1"; 766 reg = <0x15580000 0x10000>; 767 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&bpmp TEGRA186_CLK_SOR1>, 769 <&bpmp TEGRA186_CLK_SOR1_OUT>, 770 <&bpmp TEGRA186_CLK_PLLD3>, 771 <&bpmp TEGRA186_CLK_PLLDP>, 772 <&bpmp TEGRA186_CLK_SOR_SAFE>, 773 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 774 clock-names = "sor", "out", "parent", "dp", "safe", 775 "pad"; 776 resets = <&bpmp TEGRA186_RESET_SOR1>; 777 reset-names = "sor"; 778 pinctrl-0 = <&state_dpaux1_aux>; 779 pinctrl-1 = <&state_dpaux1_i2c>; 780 pinctrl-2 = <&state_dpaux1_off>; 781 pinctrl-names = "aux", "i2c", "off"; 782 status = "disabled"; 783 784 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 785 nvidia,interface = <1>; 786 }; 787 788 dpaux: dpaux@155c0000 { 789 compatible = "nvidia,tegra186-dpaux"; 790 reg = <0x155c0000 0x10000>; 791 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 793 <&bpmp TEGRA186_CLK_PLLDP>; 794 clock-names = "dpaux", "parent"; 795 resets = <&bpmp TEGRA186_RESET_DPAUX>; 796 reset-names = "dpaux"; 797 status = "disabled"; 798 799 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 800 801 state_dpaux_aux: pinmux-aux { 802 groups = "dpaux-io"; 803 function = "aux"; 804 }; 805 806 state_dpaux_i2c: pinmux-i2c { 807 groups = "dpaux-io"; 808 function = "i2c"; 809 }; 810 811 state_dpaux_off: pinmux-off { 812 groups = "dpaux-io"; 813 function = "off"; 814 }; 815 816 i2c-bus { 817 #address-cells = <1>; 818 #size-cells = <0>; 819 }; 820 }; 821 822 padctl@15880000 { 823 compatible = "nvidia,tegra186-dsi-padctl"; 824 reg = <0x15880000 0x10000>; 825 resets = <&bpmp TEGRA186_RESET_DSI>; 826 reset-names = "dsi"; 827 status = "disabled"; 828 }; 829 830 dsic: dsi@15900000 { 831 compatible = "nvidia,tegra186-dsi"; 832 reg = <0x15900000 0x10000>; 833 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&bpmp TEGRA186_CLK_DSIC>, 835 <&bpmp TEGRA186_CLK_DSIC_LP>, 836 <&bpmp TEGRA186_CLK_PLLD>; 837 clock-names = "dsi", "lp", "parent"; 838 resets = <&bpmp TEGRA186_RESET_DSIC>; 839 reset-names = "dsi"; 840 status = "disabled"; 841 842 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 843 }; 844 845 dsid: dsi@15940000 { 846 compatible = "nvidia,tegra186-dsi"; 847 reg = <0x15940000 0x10000>; 848 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&bpmp TEGRA186_CLK_DSID>, 850 <&bpmp TEGRA186_CLK_DSID_LP>, 851 <&bpmp TEGRA186_CLK_PLLD>; 852 clock-names = "dsi", "lp", "parent"; 853 resets = <&bpmp TEGRA186_RESET_DSID>; 854 reset-names = "dsi"; 855 status = "disabled"; 856 857 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 858 }; 859 }; 860 861 gpu@17000000 { 862 compatible = "nvidia,gp10b"; 863 reg = <0x0 0x17000000 0x0 0x1000000>, 864 <0x0 0x18000000 0x0 0x1000000>; 865 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 866 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "stall", "nonstall"; 868 869 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 870 <&bpmp TEGRA186_CLK_GPU>; 871 clock-names = "gpu", "pwr"; 872 resets = <&bpmp TEGRA186_RESET_GPU>; 873 reset-names = "gpu"; 874 status = "disabled"; 875 876 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 877 }; 878 879 sysram@30000000 { 880 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 881 reg = <0x0 0x30000000 0x0 0x50000>; 882 #address-cells = <2>; 883 #size-cells = <2>; 884 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 885 886 cpu_bpmp_tx: shmem@4e000 { 887 compatible = "nvidia,tegra186-bpmp-shmem"; 888 reg = <0x0 0x4e000 0x0 0x1000>; 889 label = "cpu-bpmp-tx"; 890 pool; 891 }; 892 893 cpu_bpmp_rx: shmem@4f000 { 894 compatible = "nvidia,tegra186-bpmp-shmem"; 895 reg = <0x0 0x4f000 0x0 0x1000>; 896 label = "cpu-bpmp-rx"; 897 pool; 898 }; 899 }; 900 901 cpus { 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 cpu@0 { 906 compatible = "nvidia,tegra186-denver", "arm,armv8"; 907 device_type = "cpu"; 908 reg = <0x000>; 909 }; 910 911 cpu@1 { 912 compatible = "nvidia,tegra186-denver", "arm,armv8"; 913 device_type = "cpu"; 914 reg = <0x001>; 915 }; 916 917 cpu@2 { 918 compatible = "arm,cortex-a57", "arm,armv8"; 919 device_type = "cpu"; 920 reg = <0x100>; 921 }; 922 923 cpu@3 { 924 compatible = "arm,cortex-a57", "arm,armv8"; 925 device_type = "cpu"; 926 reg = <0x101>; 927 }; 928 929 cpu@4 { 930 compatible = "arm,cortex-a57", "arm,armv8"; 931 device_type = "cpu"; 932 reg = <0x102>; 933 }; 934 935 cpu@5 { 936 compatible = "arm,cortex-a57", "arm,armv8"; 937 device_type = "cpu"; 938 reg = <0x103>; 939 }; 940 }; 941 942 bpmp: bpmp { 943 compatible = "nvidia,tegra186-bpmp"; 944 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 945 TEGRA_HSP_DB_MASTER_BPMP>; 946 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 947 #clock-cells = <1>; 948 #reset-cells = <1>; 949 #power-domain-cells = <1>; 950 951 bpmp_i2c: i2c { 952 compatible = "nvidia,tegra186-bpmp-i2c"; 953 nvidia,bpmp-bus-id = <5>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 959 bpmp_thermal: thermal { 960 compatible = "nvidia,tegra186-bpmp-thermal"; 961 #thermal-sensor-cells = <1>; 962 }; 963 }; 964 965 thermal-zones { 966 a57 { 967 polling-delay = <0>; 968 polling-delay-passive = <1000>; 969 970 thermal-sensors = 971 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 972 973 trips { 974 critical { 975 temperature = <101000>; 976 hysteresis = <0>; 977 type = "critical"; 978 }; 979 }; 980 981 cooling-maps { 982 }; 983 }; 984 985 denver { 986 polling-delay = <0>; 987 polling-delay-passive = <1000>; 988 989 thermal-sensors = 990 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 991 992 trips { 993 critical { 994 temperature = <101000>; 995 hysteresis = <0>; 996 type = "critical"; 997 }; 998 }; 999 1000 cooling-maps { 1001 }; 1002 }; 1003 1004 gpu { 1005 polling-delay = <0>; 1006 polling-delay-passive = <1000>; 1007 1008 thermal-sensors = 1009 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1010 1011 trips { 1012 critical { 1013 temperature = <101000>; 1014 hysteresis = <0>; 1015 type = "critical"; 1016 }; 1017 }; 1018 1019 cooling-maps { 1020 }; 1021 }; 1022 1023 pll { 1024 polling-delay = <0>; 1025 polling-delay-passive = <1000>; 1026 1027 thermal-sensors = 1028 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1029 1030 trips { 1031 critical { 1032 temperature = <101000>; 1033 hysteresis = <0>; 1034 type = "critical"; 1035 }; 1036 }; 1037 1038 cooling-maps { 1039 }; 1040 }; 1041 1042 always_on { 1043 polling-delay = <0>; 1044 polling-delay-passive = <1000>; 1045 1046 thermal-sensors = 1047 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1048 1049 trips { 1050 critical { 1051 temperature = <101000>; 1052 hysteresis = <0>; 1053 type = "critical"; 1054 }; 1055 }; 1056 1057 cooling-maps { 1058 }; 1059 }; 1060 }; 1061 1062 timer { 1063 compatible = "arm,armv8-timer"; 1064 interrupts = <GIC_PPI 13 1065 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1066 <GIC_PPI 14 1067 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1068 <GIC_PPI 11 1069 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1070 <GIC_PPI 10 1071 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1072 interrupt-parent = <&gic>; 1073 }; 1074}; 1075