Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37 |
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#
dc6d5d85 |
| 29-Jun-2023 |
Sameer Pujar <spujar@nvidia.com> |
arm64: tegra: Update AHUB clock parent and rate
I2S data sanity test failures are seen at lower AHUB clock rates on Tegra234. The Tegra194 uses the same clock relationship for AHUB and it is likely
arm64: tegra: Update AHUB clock parent and rate
I2S data sanity test failures are seen at lower AHUB clock rates on Tegra234. The Tegra194 uses the same clock relationship for AHUB and it is likely that similar issues would be seen. Thus update the AHUB clock parent and rates here as well for Tegra194, Tegra186 and Tegra210.
Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components") Cc: stable@vger.kernel.org Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8 |
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#
71de0a05 |
| 23-Jan-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: tegra: Drop serial clock-names and reset-names
The serial node does not use clock-names and reset-names:
tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('cloc
arm64: tegra: Drop serial clock-names and reset-names
The serial node does not use clock-names and reset-names:
tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3 |
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#
682e1c49 |
| 17-Oct-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Drop I2C iommus and dma-coherent properties
Drop the iommus and dma-coherent properties for the I2C controller device tree nodes. These are only needed for the device tree nodes that r
arm64: tegra: Drop I2C iommus and dma-coherent properties
Drop the iommus and dma-coherent properties for the I2C controller device tree nodes. These are only needed for the device tree nodes that represent the GPC DMA controller, since that is the device performing the direct memory accesses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
79ed18d9 |
| 22-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance").
While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
dd0be827 |
| 10-Nov-2022 |
Akhil R <akhilrajeev@nvidia.com> |
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in kernel and reserve fe
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
b6e097df |
| 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove clock-names from PWM nodes
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+
arm64: tegra: Remove clock-names from PWM nodes
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66 |
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#
8e442805 |
| 06-Sep-2022 |
Akhil R <akhilrajeev@nvidia.com> |
arm64: tegra: Add GPCDMA support for Tegra I2C
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Redin
arm64: tegra: Add GPCDMA support for Tegra I2C
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.65 |
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#
b0c1a994 |
| 02-Sep-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fixup iommu-map property formatting
Make sure that each phandle-array is enclosed in a set of angular brackets and properly indent each entry.
Signed-off-by: Thierry Reding <treding@n
arm64: tegra: Fixup iommu-map property formatting
Make sure that each phandle-array is enclosed in a set of angular brackets and properly indent each entry.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51 |
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#
e30cf101 |
| 27-Jun-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add Host1x context stream IDs on Tegra186+
Add Host1x context stream IDs on systems that support Host1x context isolation. Host1x and attached engines can use these stream IDs to allow
arm64: tegra: Add Host1x context stream IDs on Tegra186+
Add Host1x context stream IDs on systems that support Host1x context isolation. Host1x and attached engines can use these stream IDs to allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor, if one is present.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
c710ac0b |
| 04-Jul-2022 |
Kartik <kkartik@nvidia.com> |
arm64: tegra: Enable native timers on Tegra186
Enable the native timers on Tegra186 chips to allow using the watchdog functionality to recover from system hangs.
Signed-off-by: Kartik <kkartik@nvid
arm64: tegra: Enable native timers on Tegra186
Enable the native timers on Tegra186 chips to allow using the watchdog functionality to recover from system hangs.
Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.50 |
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#
61192a9d |
| 22-Jun-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Mark BPMP channels as no-memory-wc
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will caus
arm64: tegra: Mark BPMP channels as no-memory-wc
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues.
Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map.
Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed.
As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory.
Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.49, v5.15.48, v5.15.47, v5.15.46 |
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#
4b6a1b7c |
| 06-Jun-2022 |
Sameer Pujar <spujar@nvidia.com> |
arm64: tegra: Add OPE device on Tegra210 and later
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant S
arm64: tegra: Add OPE device on Tegra210 and later
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files.
Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36 |
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#
000b99e5 |
| 26-Apr-2022 |
Ashish Mhetre <amhetre@nvidia.com> |
arm64: tegra: Add memory controller channels
From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be
arm64: tegra: Add memory controller channels
From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.35, v5.15.34, v5.15.33 |
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#
47a08153 |
| 31-Mar-2022 |
Sameer Pujar <spujar@nvidia.com> |
arm64: tegra: Add ASRC device on Tegra186 and later
Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is present on Tegra186 and later generations of Tegra SoC. Add this device on th
arm64: tegra: Add ASRC device on Tegra186 and later
Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is present on Tegra186 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files.
Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7 |
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#
f0a48120 |
| 07-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Drop arm,armv8-pmuv3 compatible string
The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific com
arm64: tegra: Drop arm,armv8-pmuv3 compatible string
The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific compatible strings instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
835553b3 |
| 07-Feb-2022 |
Akhil R <akhilrajeev@nvidia.com> |
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
2b14cbd6 |
| 07-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Adjust length of CCPLEX cluster MMIO region
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length
arm64: tegra: Adjust length of CCPLEX cluster MMIO region
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
548c9c5a |
| 07-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fix Tegra186 compatible string list
The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list.
Signe
arm64: tegra: Fix Tegra186 compatible string list
The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
fe57ff53 |
| 07-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename thermal zones nodes
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27 |
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#
bd1fefcb |
| 19-Mar-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add native timer support on Tegra186
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tre
arm64: tegra: Add native timer support on Tegra186
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
f7eb2785 |
| 17-Nov-2021 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194.
Signed-off-by: Jon Hunter <jonathanh@nv
arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
7fa30752 |
| 12-Nov-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fixup SYSRAM references
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM refere
arm64: tegra: Fixup SYSRAM references
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
848f3290 |
| 13-Sep-2021 |
Sameer Pujar <spujar@nvidia.com> |
arm64: tegra: Add few AHUB devices for Tegra210 and later
Add DT nodes for following AHUB devices: * SFC (Sampling Frequency Converter) * MVC (Master Volume Control) * AMX (Audio Multiplexer) *
arm64: tegra: Add few AHUB devices for Tegra210 and later
Add DT nodes for following AHUB devices: * SFC (Sampling Frequency Converter) * MVC (Master Volume Control) * AMX (Audio Multiplexer) * ADX (Audio Demultiplexer) * Mixer
Above devices are added for Tegra210, Tegra186 and Tegra194 generations of Tegra SoC.
Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
78a05873 |
| 16-Sep-2021 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add NVDEC to Tegra186/194 device trees
Add a device tree node for NVDEC on Tegra186, and device tree nodes for NVDEC and NVDEC1 on Tegra194.
Signed-off-by: Mikko Perttunen <mperttunen
arm64: tegra: Add NVDEC to Tegra186/194 device trees
Add a device tree node for NVDEC on Tegra186, and device tree nodes for NVDEC and NVDEC1 on Tegra194.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
a7f751d4 |
| 22-Jun-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Mark BPMP channels as no-memory-wc
[ Upstream commit 61192a9d8a6367ae1b8234876941b037910a2459 ]
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blo
arm64: tegra: Mark BPMP channels as no-memory-wc
[ Upstream commit 61192a9d8a6367ae1b8234876941b037910a2459 ]
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues.
Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map.
Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed.
As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory.
Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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