1#include <dt-bindings/clock/tegra186-clock.h> 2#include <dt-bindings/gpio/tegra186-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h> 5#include <dt-bindings/reset/tegra186-reset.h> 6 7/ { 8 compatible = "nvidia,tegra186"; 9 interrupt-parent = <&gic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 gpio: gpio@2200000 { 14 compatible = "nvidia,tegra186-gpio"; 15 reg-names = "security", "gpio"; 16 reg = <0x0 0x2200000 0x0 0x10000>, 17 <0x0 0x2210000 0x0 0x10000>; 18 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 19 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 24 #interrupt-cells = <2>; 25 interrupt-controller; 26 #gpio-cells = <2>; 27 gpio-controller; 28 }; 29 30 uarta: serial@3100000 { 31 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 32 reg = <0x0 0x03100000 0x0 0x40>; 33 reg-shift = <2>; 34 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 35 clocks = <&bpmp TEGRA186_CLK_UARTA>; 36 clock-names = "serial"; 37 resets = <&bpmp TEGRA186_RESET_UARTA>; 38 reset-names = "serial"; 39 status = "disabled"; 40 }; 41 42 uartb: serial@3110000 { 43 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 44 reg = <0x0 0x03110000 0x0 0x40>; 45 reg-shift = <2>; 46 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 47 clocks = <&bpmp TEGRA186_CLK_UARTB>; 48 clock-names = "serial"; 49 resets = <&bpmp TEGRA186_RESET_UARTB>; 50 reset-names = "serial"; 51 status = "disabled"; 52 }; 53 54 uartd: serial@3130000 { 55 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 56 reg = <0x0 0x03130000 0x0 0x40>; 57 reg-shift = <2>; 58 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 59 clocks = <&bpmp TEGRA186_CLK_UARTD>; 60 clock-names = "serial"; 61 resets = <&bpmp TEGRA186_RESET_UARTD>; 62 reset-names = "serial"; 63 status = "disabled"; 64 }; 65 66 uarte: serial@3140000 { 67 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 68 reg = <0x0 0x03140000 0x0 0x40>; 69 reg-shift = <2>; 70 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 71 clocks = <&bpmp TEGRA186_CLK_UARTE>; 72 clock-names = "serial"; 73 resets = <&bpmp TEGRA186_RESET_UARTE>; 74 reset-names = "serial"; 75 status = "disabled"; 76 }; 77 78 uartf: serial@3150000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03150000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTF>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTF>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 gen1_i2c: i2c@3160000 { 91 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 92 reg = <0x0 0x03160000 0x0 0x10000>; 93 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 clocks = <&bpmp TEGRA186_CLK_I2C1>; 97 clock-names = "div-clk"; 98 resets = <&bpmp TEGRA186_RESET_I2C1>; 99 reset-names = "i2c"; 100 status = "disabled"; 101 }; 102 103 cam_i2c: i2c@3180000 { 104 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 105 reg = <0x0 0x03180000 0x0 0x10000>; 106 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 clocks = <&bpmp TEGRA186_CLK_I2C3>; 110 clock-names = "div-clk"; 111 resets = <&bpmp TEGRA186_RESET_I2C3>; 112 reset-names = "i2c"; 113 status = "disabled"; 114 }; 115 116 /* shares pads with dpaux1 */ 117 dp_aux_ch1_i2c: i2c@3190000 { 118 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 119 reg = <0x0 0x03190000 0x0 0x10000>; 120 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 clocks = <&bpmp TEGRA186_CLK_I2C4>; 124 clock-names = "div-clk"; 125 resets = <&bpmp TEGRA186_RESET_I2C4>; 126 reset-names = "i2c"; 127 status = "disabled"; 128 }; 129 130 /* controlled by BPMP, should not be enabled */ 131 pwr_i2c: i2c@31a0000 { 132 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 133 reg = <0x0 0x031a0000 0x0 0x10000>; 134 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 clocks = <&bpmp TEGRA186_CLK_I2C5>; 138 clock-names = "div-clk"; 139 resets = <&bpmp TEGRA186_RESET_I2C5>; 140 reset-names = "i2c"; 141 status = "disabled"; 142 }; 143 144 /* shares pads with dpaux0 */ 145 dp_aux_ch0_i2c: i2c@31b0000 { 146 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 147 reg = <0x0 0x031b0000 0x0 0x10000>; 148 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 clocks = <&bpmp TEGRA186_CLK_I2C6>; 152 clock-names = "div-clk"; 153 resets = <&bpmp TEGRA186_RESET_I2C6>; 154 reset-names = "i2c"; 155 status = "disabled"; 156 }; 157 158 gen7_i2c: i2c@31c0000 { 159 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 160 reg = <0x0 0x031c0000 0x0 0x10000>; 161 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 clocks = <&bpmp TEGRA186_CLK_I2C7>; 165 clock-names = "div-clk"; 166 resets = <&bpmp TEGRA186_RESET_I2C7>; 167 reset-names = "i2c"; 168 status = "disabled"; 169 }; 170 171 gen9_i2c: i2c@31e0000 { 172 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 173 reg = <0x0 0x031e0000 0x0 0x10000>; 174 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clocks = <&bpmp TEGRA186_CLK_I2C9>; 178 clock-names = "div-clk"; 179 resets = <&bpmp TEGRA186_RESET_I2C9>; 180 reset-names = "i2c"; 181 status = "disabled"; 182 }; 183 184 sdmmc1: sdhci@3400000 { 185 compatible = "nvidia,tegra186-sdhci"; 186 reg = <0x0 0x03400000 0x0 0x10000>; 187 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 189 clock-names = "sdhci"; 190 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 191 reset-names = "sdhci"; 192 status = "disabled"; 193 }; 194 195 sdmmc2: sdhci@3420000 { 196 compatible = "nvidia,tegra186-sdhci"; 197 reg = <0x0 0x03420000 0x0 0x10000>; 198 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 200 clock-names = "sdhci"; 201 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 202 reset-names = "sdhci"; 203 status = "disabled"; 204 }; 205 206 sdmmc3: sdhci@3440000 { 207 compatible = "nvidia,tegra186-sdhci"; 208 reg = <0x0 0x03440000 0x0 0x10000>; 209 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 211 clock-names = "sdhci"; 212 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 213 reset-names = "sdhci"; 214 status = "disabled"; 215 }; 216 217 sdmmc4: sdhci@3460000 { 218 compatible = "nvidia,tegra186-sdhci"; 219 reg = <0x0 0x03460000 0x0 0x10000>; 220 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 222 clock-names = "sdhci"; 223 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 224 reset-names = "sdhci"; 225 status = "disabled"; 226 }; 227 228 gic: interrupt-controller@3881000 { 229 compatible = "arm,gic-400"; 230 #interrupt-cells = <3>; 231 interrupt-controller; 232 reg = <0x0 0x03881000 0x0 0x1000>, 233 <0x0 0x03882000 0x0 0x2000>; 234 interrupts = <GIC_PPI 9 235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 236 interrupt-parent = <&gic>; 237 }; 238 239 hsp_top0: hsp@3c00000 { 240 compatible = "nvidia,tegra186-hsp"; 241 reg = <0x0 0x03c00000 0x0 0xa0000>; 242 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-names = "doorbell"; 244 #mbox-cells = <2>; 245 status = "disabled"; 246 }; 247 248 gen2_i2c: i2c@c240000 { 249 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 250 reg = <0x0 0x0c240000 0x0 0x10000>; 251 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 clocks = <&bpmp TEGRA186_CLK_I2C2>; 255 clock-names = "div-clk"; 256 resets = <&bpmp TEGRA186_RESET_I2C2>; 257 reset-names = "i2c"; 258 status = "disabled"; 259 }; 260 261 gen8_i2c: i2c@c250000 { 262 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 263 reg = <0x0 0x0c250000 0x0 0x10000>; 264 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 clocks = <&bpmp TEGRA186_CLK_I2C8>; 268 clock-names = "div-clk"; 269 resets = <&bpmp TEGRA186_RESET_I2C8>; 270 reset-names = "i2c"; 271 status = "disabled"; 272 }; 273 274 uartc: serial@c280000 { 275 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 276 reg = <0x0 0x0c280000 0x0 0x40>; 277 reg-shift = <2>; 278 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&bpmp TEGRA186_CLK_UARTC>; 280 clock-names = "serial"; 281 resets = <&bpmp TEGRA186_RESET_UARTC>; 282 reset-names = "serial"; 283 status = "disabled"; 284 }; 285 286 uartg: serial@c290000 { 287 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 288 reg = <0x0 0x0c290000 0x0 0x40>; 289 reg-shift = <2>; 290 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&bpmp TEGRA186_CLK_UARTG>; 292 clock-names = "serial"; 293 resets = <&bpmp TEGRA186_RESET_UARTG>; 294 reset-names = "serial"; 295 status = "disabled"; 296 }; 297 298 gpio_aon: gpio@c2f0000 { 299 compatible = "nvidia,tegra186-gpio-aon"; 300 reg-names = "security", "gpio"; 301 reg = <0x0 0xc2f0000 0x0 0x1000>, 302 <0x0 0xc2f1000 0x0 0x1000>; 303 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupt-controller; 307 #interrupt-cells = <2>; 308 }; 309 310 pmc@c360000 { 311 compatible = "nvidia,tegra186-pmc"; 312 reg = <0 0x0c360000 0 0x10000>, 313 <0 0x0c370000 0 0x10000>, 314 <0 0x0c380000 0 0x10000>, 315 <0 0x0c390000 0 0x10000>; 316 reg-names = "pmc", "wake", "aotag", "scratch"; 317 }; 318 319 sysram@30000000 { 320 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 321 reg = <0x0 0x30000000 0x0 0x50000>; 322 #address-cells = <2>; 323 #size-cells = <2>; 324 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 325 326 cpu_bpmp_tx: shmem@4e000 { 327 compatible = "nvidia,tegra186-bpmp-shmem"; 328 reg = <0x0 0x4e000 0x0 0x1000>; 329 label = "cpu-bpmp-tx"; 330 pool; 331 }; 332 333 cpu_bpmp_rx: shmem@4f000 { 334 compatible = "nvidia,tegra186-bpmp-shmem"; 335 reg = <0x0 0x4f000 0x0 0x1000>; 336 label = "cpu-bpmp-rx"; 337 pool; 338 }; 339 }; 340 341 cpus { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 345 cpu@0 { 346 compatible = "nvidia,tegra186-denver", "arm,armv8"; 347 device_type = "cpu"; 348 reg = <0x000>; 349 }; 350 351 cpu@1 { 352 compatible = "nvidia,tegra186-denver", "arm,armv8"; 353 device_type = "cpu"; 354 reg = <0x001>; 355 }; 356 357 cpu@2 { 358 compatible = "arm,cortex-a57", "arm,armv8"; 359 device_type = "cpu"; 360 reg = <0x100>; 361 }; 362 363 cpu@3 { 364 compatible = "arm,cortex-a57", "arm,armv8"; 365 device_type = "cpu"; 366 reg = <0x101>; 367 }; 368 369 cpu@4 { 370 compatible = "arm,cortex-a57", "arm,armv8"; 371 device_type = "cpu"; 372 reg = <0x102>; 373 }; 374 375 cpu@5 { 376 compatible = "arm,cortex-a57", "arm,armv8"; 377 device_type = "cpu"; 378 reg = <0x103>; 379 }; 380 }; 381 382 bpmp: bpmp { 383 compatible = "nvidia,tegra186-bpmp"; 384 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 385 TEGRA_HSP_DB_MASTER_BPMP>; 386 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 387 #clock-cells = <1>; 388 #reset-cells = <1>; 389 390 bpmp_i2c: i2c { 391 compatible = "nvidia,tegra186-bpmp-i2c"; 392 nvidia,bpmp-bus-id = <5>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 status = "disabled"; 396 }; 397 }; 398 399 timer { 400 compatible = "arm,armv8-timer"; 401 interrupts = <GIC_PPI 13 402 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 403 <GIC_PPI 14 404 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 405 <GIC_PPI 11 406 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 407 <GIC_PPI 10 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 409 interrupt-parent = <&gic>; 410 }; 411}; 412