arm64: tegra: Add CPU and cache topology for Tegra194

Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the second-
and

arm64: tegra: Add CPU and cache topology for Tegra194

Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the second-
and third-level caches and associates them with the CPUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add configuration for PCIe C5 sideband signals

Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively which unlike oth

arm64: tegra: Add configuration for PCIe C5 sideband signals

Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively which unlike other
PCIe controllers sideband signals are not configured by default.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>

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arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT

Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instance

arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT

Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add ACONNECT, ADMA and AGIC nodes

Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon

arm64: tegra: Add ACONNECT, ADMA and AGIC nodes

Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Mark architected timer as always on

The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the timer as
alwa

arm64: tegra: Mark architected timer as always on

The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the timer as
always on.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Support 200 MHz for SDMMC on Tegra194

Change the SDMMC clock source to support a maximum frequency of 200 MHz
on Tegra194.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>

arm64: tegra: Support 200 MHz for SDMMC on Tegra194

Change the SDMMC clock source to support a maximum frequency of 200 MHz
on Tegra194.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CQE Support for SDMMC4

Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <tredi

arm64: tegra: Add CQE Support for SDMMC4

Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used

arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used when calibration timeouts.

Fixed drive strengths are based on Pre SI Analysis of the pads.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add nodes for TCU on Tegra194

Add nodes required for communication through the Tegra Combined UART.
This includes the AON HSP instance, addition of shared interrupts
for the TOP0 HSP i

arm64: tegra: Add nodes for TCU on Tegra194

Add nodes required for communication through the Tegra Combined UART.
This includes the AON HSP instance, addition of shared interrupts
for the TOP0 HSP instance, and finally the TCU node itself. Also
mark the HSP instances as compatible to tegra194-hsp, as the hardware
is not identical but is compatible to tegra186-hsp.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fal

arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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arm64: tegra: Set reg property for display-hub on Tegra194

Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
contro

arm64: tegra: Set reg property for display-hub on Tegra194

Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CEC controller on Tegra194

The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Add HDA controller on Tegra194

The HDA controller found on Tegra194 can be used for audio playback over
HDMI.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Re

arm64: tegra: Add HDA controller on Tegra194

The HDA controller found on Tegra194 can be used for audio playback over
HDMI.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add AON GPIO controller on Tegra194

The AON GPIO controller is in an always-on power partition and typically
provides pins for functions that need to always work, such as the power
key

arm64: tegra: Add AON GPIO controller on Tegra194

The AON GPIO controller is in an always-on power partition and typically
provides pins for functions that need to always work, such as the power
key for example.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add RTC support on Tegra194

The RTC on Tegra194 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a d

arm64: tegra: Add RTC support on Tegra194

The RTC on Tegra194 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable PMC wake events on Tegra194

Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
mon

arm64: tegra: Enable PMC wake events on Tegra194

Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add thermal zones on Tegra194

The NVIDIA Tegra194 SoC defines six thermal zones. Define all of them in
device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Add VIC support on Tegra194

Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.

Signed-off-by: Thierry

arm64: tegra: Add VIC support on Tegra194

Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add display support on Tegra194

Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output.

arm64: tegra: Add display support on Tegra194

Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add PWM controllers on Tegra194

Tegra194 has eight single-channel PWM controllers, one of them in the
AON partition.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: I2C on Tegra194 is not compatible with Tegra114

Tegra194 contains a version of the I2C controller that is no longer
compatible with the version found in Tegra114.

Signed-off-by: Thier

arm64: tegra: I2C on Tegra194 is not compatible with Tegra114

Tegra194 contains a version of the I2C controller that is no longer
compatible with the version found in Tegra114.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CPU nodes to Tegra194 device tree

Add CPU and PSCI nodes to device tree. The Tegra194 SoC contains
eight NVIDIA Carmel CPUs.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

arm64: tegra: Add CPU nodes to Tegra194 device tree

Add CPU and PSCI nodes to device tree. The Tegra194 SoC contains
eight NVIDIA Carmel CPUs.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add ethernet controller on Tegra194

The Tegra194 contains the same ethernet controller as the Tegra186.
Add the device tree node for it, and correspondingly the PHY node
on the board d

arm64: tegra: Add ethernet controller on Tegra194

The Tegra194 contains the same ethernet controller as the Tegra186.
Add the device tree node for it, and correspondingly the PHY node
on the board device tree.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add GPIO controller on Tegra194

Add the device tree node for the GPIO controller on Tegra194.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <tre

arm64: tegra: Add GPIO controller on Tegra194

Add the device tree node for the GPIO controller on Tegra194.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add Tegra194 chip device tree

Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially a

arm64: tegra: Add Tegra194 chip device tree

Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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