1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 aconnect { 63 compatible = "nvidia,tegra194-aconnect", 64 "nvidia,tegra210-aconnect"; 65 clocks = <&bpmp TEGRA194_CLK_APE>, 66 <&bpmp TEGRA194_CLK_APB2APE>; 67 clock-names = "ape", "apb2ape"; 68 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0x02900000 0x02900000 0x200000>; 72 status = "disabled"; 73 74 dma-controller@2930000 { 75 compatible = "nvidia,tegra194-adma", 76 "nvidia,tegra186-adma"; 77 reg = <0x02930000 0x20000>; 78 interrupt-parent = <&agic>; 79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 111 #dma-cells = <1>; 112 clocks = <&bpmp TEGRA194_CLK_AHUB>; 113 clock-names = "d_audio"; 114 status = "disabled"; 115 }; 116 117 agic: interrupt-controller@2a40000 { 118 compatible = "nvidia,tegra194-agic", 119 "nvidia,tegra210-agic"; 120 #interrupt-cells = <3>; 121 interrupt-controller; 122 reg = <0x02a41000 0x1000>, 123 <0x02a42000 0x2000>; 124 interrupts = <GIC_SPI 145 125 (GIC_CPU_MASK_SIMPLE(4) | 126 IRQ_TYPE_LEVEL_HIGH)>; 127 clocks = <&bpmp TEGRA194_CLK_APE>; 128 clock-names = "clk"; 129 status = "disabled"; 130 }; 131 }; 132 133 uarta: serial@3100000 { 134 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 135 reg = <0x03100000 0x40>; 136 reg-shift = <2>; 137 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&bpmp TEGRA194_CLK_UARTA>; 139 clock-names = "serial"; 140 resets = <&bpmp TEGRA194_RESET_UARTA>; 141 reset-names = "serial"; 142 status = "disabled"; 143 }; 144 145 uartb: serial@3110000 { 146 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 147 reg = <0x03110000 0x40>; 148 reg-shift = <2>; 149 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&bpmp TEGRA194_CLK_UARTB>; 151 clock-names = "serial"; 152 resets = <&bpmp TEGRA194_RESET_UARTB>; 153 reset-names = "serial"; 154 status = "disabled"; 155 }; 156 157 uartd: serial@3130000 { 158 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 159 reg = <0x03130000 0x40>; 160 reg-shift = <2>; 161 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&bpmp TEGRA194_CLK_UARTD>; 163 clock-names = "serial"; 164 resets = <&bpmp TEGRA194_RESET_UARTD>; 165 reset-names = "serial"; 166 status = "disabled"; 167 }; 168 169 uarte: serial@3140000 { 170 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 171 reg = <0x03140000 0x40>; 172 reg-shift = <2>; 173 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&bpmp TEGRA194_CLK_UARTE>; 175 clock-names = "serial"; 176 resets = <&bpmp TEGRA194_RESET_UARTE>; 177 reset-names = "serial"; 178 status = "disabled"; 179 }; 180 181 uartf: serial@3150000 { 182 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 183 reg = <0x03150000 0x40>; 184 reg-shift = <2>; 185 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&bpmp TEGRA194_CLK_UARTF>; 187 clock-names = "serial"; 188 resets = <&bpmp TEGRA194_RESET_UARTF>; 189 reset-names = "serial"; 190 status = "disabled"; 191 }; 192 193 gen1_i2c: i2c@3160000 { 194 compatible = "nvidia,tegra194-i2c"; 195 reg = <0x03160000 0x10000>; 196 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA194_CLK_I2C1>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA194_RESET_I2C1>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 uarth: serial@3170000 { 207 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 208 reg = <0x03170000 0x40>; 209 reg-shift = <2>; 210 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&bpmp TEGRA194_CLK_UARTH>; 212 clock-names = "serial"; 213 resets = <&bpmp TEGRA194_RESET_UARTH>; 214 reset-names = "serial"; 215 status = "disabled"; 216 }; 217 218 cam_i2c: i2c@3180000 { 219 compatible = "nvidia,tegra194-i2c"; 220 reg = <0x03180000 0x10000>; 221 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 clocks = <&bpmp TEGRA194_CLK_I2C3>; 225 clock-names = "div-clk"; 226 resets = <&bpmp TEGRA194_RESET_I2C3>; 227 reset-names = "i2c"; 228 status = "disabled"; 229 }; 230 231 /* shares pads with dpaux1 */ 232 dp_aux_ch1_i2c: i2c@3190000 { 233 compatible = "nvidia,tegra194-i2c"; 234 reg = <0x03190000 0x10000>; 235 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 clocks = <&bpmp TEGRA194_CLK_I2C4>; 239 clock-names = "div-clk"; 240 resets = <&bpmp TEGRA194_RESET_I2C4>; 241 reset-names = "i2c"; 242 status = "disabled"; 243 }; 244 245 /* shares pads with dpaux0 */ 246 dp_aux_ch0_i2c: i2c@31b0000 { 247 compatible = "nvidia,tegra194-i2c"; 248 reg = <0x031b0000 0x10000>; 249 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 clocks = <&bpmp TEGRA194_CLK_I2C6>; 253 clock-names = "div-clk"; 254 resets = <&bpmp TEGRA194_RESET_I2C6>; 255 reset-names = "i2c"; 256 status = "disabled"; 257 }; 258 259 gen7_i2c: i2c@31c0000 { 260 compatible = "nvidia,tegra194-i2c"; 261 reg = <0x031c0000 0x10000>; 262 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 clocks = <&bpmp TEGRA194_CLK_I2C7>; 266 clock-names = "div-clk"; 267 resets = <&bpmp TEGRA194_RESET_I2C7>; 268 reset-names = "i2c"; 269 status = "disabled"; 270 }; 271 272 gen9_i2c: i2c@31e0000 { 273 compatible = "nvidia,tegra194-i2c"; 274 reg = <0x031e0000 0x10000>; 275 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clocks = <&bpmp TEGRA194_CLK_I2C9>; 279 clock-names = "div-clk"; 280 resets = <&bpmp TEGRA194_RESET_I2C9>; 281 reset-names = "i2c"; 282 status = "disabled"; 283 }; 284 285 pwm1: pwm@3280000 { 286 compatible = "nvidia,tegra194-pwm", 287 "nvidia,tegra186-pwm"; 288 reg = <0x3280000 0x10000>; 289 clocks = <&bpmp TEGRA194_CLK_PWM1>; 290 clock-names = "pwm"; 291 resets = <&bpmp TEGRA194_RESET_PWM1>; 292 reset-names = "pwm"; 293 status = "disabled"; 294 #pwm-cells = <2>; 295 }; 296 297 pwm2: pwm@3290000 { 298 compatible = "nvidia,tegra194-pwm", 299 "nvidia,tegra186-pwm"; 300 reg = <0x3290000 0x10000>; 301 clocks = <&bpmp TEGRA194_CLK_PWM2>; 302 clock-names = "pwm"; 303 resets = <&bpmp TEGRA194_RESET_PWM2>; 304 reset-names = "pwm"; 305 status = "disabled"; 306 #pwm-cells = <2>; 307 }; 308 309 pwm3: pwm@32a0000 { 310 compatible = "nvidia,tegra194-pwm", 311 "nvidia,tegra186-pwm"; 312 reg = <0x32a0000 0x10000>; 313 clocks = <&bpmp TEGRA194_CLK_PWM3>; 314 clock-names = "pwm"; 315 resets = <&bpmp TEGRA194_RESET_PWM3>; 316 reset-names = "pwm"; 317 status = "disabled"; 318 #pwm-cells = <2>; 319 }; 320 321 pwm5: pwm@32c0000 { 322 compatible = "nvidia,tegra194-pwm", 323 "nvidia,tegra186-pwm"; 324 reg = <0x32c0000 0x10000>; 325 clocks = <&bpmp TEGRA194_CLK_PWM5>; 326 clock-names = "pwm"; 327 resets = <&bpmp TEGRA194_RESET_PWM5>; 328 reset-names = "pwm"; 329 status = "disabled"; 330 #pwm-cells = <2>; 331 }; 332 333 pwm6: pwm@32d0000 { 334 compatible = "nvidia,tegra194-pwm", 335 "nvidia,tegra186-pwm"; 336 reg = <0x32d0000 0x10000>; 337 clocks = <&bpmp TEGRA194_CLK_PWM6>; 338 clock-names = "pwm"; 339 resets = <&bpmp TEGRA194_RESET_PWM6>; 340 reset-names = "pwm"; 341 status = "disabled"; 342 #pwm-cells = <2>; 343 }; 344 345 pwm7: pwm@32e0000 { 346 compatible = "nvidia,tegra194-pwm", 347 "nvidia,tegra186-pwm"; 348 reg = <0x32e0000 0x10000>; 349 clocks = <&bpmp TEGRA194_CLK_PWM7>; 350 clock-names = "pwm"; 351 resets = <&bpmp TEGRA194_RESET_PWM7>; 352 reset-names = "pwm"; 353 status = "disabled"; 354 #pwm-cells = <2>; 355 }; 356 357 pwm8: pwm@32f0000 { 358 compatible = "nvidia,tegra194-pwm", 359 "nvidia,tegra186-pwm"; 360 reg = <0x32f0000 0x10000>; 361 clocks = <&bpmp TEGRA194_CLK_PWM8>; 362 clock-names = "pwm"; 363 resets = <&bpmp TEGRA194_RESET_PWM8>; 364 reset-names = "pwm"; 365 status = "disabled"; 366 #pwm-cells = <2>; 367 }; 368 369 sdmmc1: sdhci@3400000 { 370 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 371 reg = <0x03400000 0x10000>; 372 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 374 clock-names = "sdhci"; 375 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 376 reset-names = "sdhci"; 377 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 378 <0x07>; 379 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 380 <0x07>; 381 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 382 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 383 <0x07>; 384 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 385 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 386 nvidia,default-tap = <0x9>; 387 nvidia,default-trim = <0x5>; 388 status = "disabled"; 389 }; 390 391 sdmmc3: sdhci@3440000 { 392 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 393 reg = <0x03440000 0x10000>; 394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 396 clock-names = "sdhci"; 397 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 398 reset-names = "sdhci"; 399 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 400 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 401 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 402 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 403 <0x07>; 404 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 405 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 406 <0x07>; 407 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 408 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 409 nvidia,default-tap = <0x9>; 410 nvidia,default-trim = <0x5>; 411 status = "disabled"; 412 }; 413 414 sdmmc4: sdhci@3460000 { 415 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 416 reg = <0x03460000 0x10000>; 417 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 419 clock-names = "sdhci"; 420 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 421 <&bpmp TEGRA194_CLK_PLLC4>; 422 assigned-clock-parents = 423 <&bpmp TEGRA194_CLK_PLLC4>; 424 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 425 reset-names = "sdhci"; 426 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 427 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 428 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 429 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 430 <0x0a>; 431 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 432 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 433 <0x0a>; 434 nvidia,default-tap = <0x8>; 435 nvidia,default-trim = <0x14>; 436 nvidia,dqs-trim = <40>; 437 supports-cqe; 438 status = "disabled"; 439 }; 440 441 hda@3510000 { 442 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 443 reg = <0x3510000 0x10000>; 444 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&bpmp TEGRA194_CLK_HDA>, 446 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 447 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 448 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 449 resets = <&bpmp TEGRA194_RESET_HDA>, 450 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 451 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 452 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 453 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 454 status = "disabled"; 455 }; 456 457 gic: interrupt-controller@3881000 { 458 compatible = "arm,gic-400"; 459 #interrupt-cells = <3>; 460 interrupt-controller; 461 reg = <0x03881000 0x1000>, 462 <0x03882000 0x2000>, 463 <0x03884000 0x2000>, 464 <0x03886000 0x2000>; 465 interrupts = <GIC_PPI 9 466 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 467 interrupt-parent = <&gic>; 468 }; 469 470 cec@3960000 { 471 compatible = "nvidia,tegra194-cec"; 472 reg = <0x03960000 0x10000>; 473 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&bpmp TEGRA194_CLK_CEC>; 475 clock-names = "cec"; 476 status = "disabled"; 477 }; 478 479 hsp_top0: hsp@3c00000 { 480 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 481 reg = <0x03c00000 0xa0000>; 482 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 492 "shared3", "shared4", "shared5", "shared6", 493 "shared7"; 494 #mbox-cells = <2>; 495 }; 496 497 p2u_hsio_0: phy@3e10000 { 498 compatible = "nvidia,tegra194-p2u"; 499 reg = <0x03e10000 0x10000>; 500 reg-names = "ctl"; 501 502 #phy-cells = <0>; 503 }; 504 505 p2u_hsio_1: phy@3e20000 { 506 compatible = "nvidia,tegra194-p2u"; 507 reg = <0x03e20000 0x10000>; 508 reg-names = "ctl"; 509 510 #phy-cells = <0>; 511 }; 512 513 p2u_hsio_2: phy@3e30000 { 514 compatible = "nvidia,tegra194-p2u"; 515 reg = <0x03e30000 0x10000>; 516 reg-names = "ctl"; 517 518 #phy-cells = <0>; 519 }; 520 521 p2u_hsio_3: phy@3e40000 { 522 compatible = "nvidia,tegra194-p2u"; 523 reg = <0x03e40000 0x10000>; 524 reg-names = "ctl"; 525 526 #phy-cells = <0>; 527 }; 528 529 p2u_hsio_4: phy@3e50000 { 530 compatible = "nvidia,tegra194-p2u"; 531 reg = <0x03e50000 0x10000>; 532 reg-names = "ctl"; 533 534 #phy-cells = <0>; 535 }; 536 537 p2u_hsio_5: phy@3e60000 { 538 compatible = "nvidia,tegra194-p2u"; 539 reg = <0x03e60000 0x10000>; 540 reg-names = "ctl"; 541 542 #phy-cells = <0>; 543 }; 544 545 p2u_hsio_6: phy@3e70000 { 546 compatible = "nvidia,tegra194-p2u"; 547 reg = <0x03e70000 0x10000>; 548 reg-names = "ctl"; 549 550 #phy-cells = <0>; 551 }; 552 553 p2u_hsio_7: phy@3e80000 { 554 compatible = "nvidia,tegra194-p2u"; 555 reg = <0x03e80000 0x10000>; 556 reg-names = "ctl"; 557 558 #phy-cells = <0>; 559 }; 560 561 p2u_hsio_8: phy@3e90000 { 562 compatible = "nvidia,tegra194-p2u"; 563 reg = <0x03e90000 0x10000>; 564 reg-names = "ctl"; 565 566 #phy-cells = <0>; 567 }; 568 569 p2u_hsio_9: phy@3ea0000 { 570 compatible = "nvidia,tegra194-p2u"; 571 reg = <0x03ea0000 0x10000>; 572 reg-names = "ctl"; 573 574 #phy-cells = <0>; 575 }; 576 577 p2u_nvhs_0: phy@3eb0000 { 578 compatible = "nvidia,tegra194-p2u"; 579 reg = <0x03eb0000 0x10000>; 580 reg-names = "ctl"; 581 582 #phy-cells = <0>; 583 }; 584 585 p2u_nvhs_1: phy@3ec0000 { 586 compatible = "nvidia,tegra194-p2u"; 587 reg = <0x03ec0000 0x10000>; 588 reg-names = "ctl"; 589 590 #phy-cells = <0>; 591 }; 592 593 p2u_nvhs_2: phy@3ed0000 { 594 compatible = "nvidia,tegra194-p2u"; 595 reg = <0x03ed0000 0x10000>; 596 reg-names = "ctl"; 597 598 #phy-cells = <0>; 599 }; 600 601 p2u_nvhs_3: phy@3ee0000 { 602 compatible = "nvidia,tegra194-p2u"; 603 reg = <0x03ee0000 0x10000>; 604 reg-names = "ctl"; 605 606 #phy-cells = <0>; 607 }; 608 609 p2u_nvhs_4: phy@3ef0000 { 610 compatible = "nvidia,tegra194-p2u"; 611 reg = <0x03ef0000 0x10000>; 612 reg-names = "ctl"; 613 614 #phy-cells = <0>; 615 }; 616 617 p2u_nvhs_5: phy@3f00000 { 618 compatible = "nvidia,tegra194-p2u"; 619 reg = <0x03f00000 0x10000>; 620 reg-names = "ctl"; 621 622 #phy-cells = <0>; 623 }; 624 625 p2u_nvhs_6: phy@3f10000 { 626 compatible = "nvidia,tegra194-p2u"; 627 reg = <0x03f10000 0x10000>; 628 reg-names = "ctl"; 629 630 #phy-cells = <0>; 631 }; 632 633 p2u_nvhs_7: phy@3f20000 { 634 compatible = "nvidia,tegra194-p2u"; 635 reg = <0x03f20000 0x10000>; 636 reg-names = "ctl"; 637 638 #phy-cells = <0>; 639 }; 640 641 p2u_hsio_10: phy@3f30000 { 642 compatible = "nvidia,tegra194-p2u"; 643 reg = <0x03f30000 0x10000>; 644 reg-names = "ctl"; 645 646 #phy-cells = <0>; 647 }; 648 649 p2u_hsio_11: phy@3f40000 { 650 compatible = "nvidia,tegra194-p2u"; 651 reg = <0x03f40000 0x10000>; 652 reg-names = "ctl"; 653 654 #phy-cells = <0>; 655 }; 656 657 hsp_aon: hsp@c150000 { 658 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 659 reg = <0x0c150000 0xa0000>; 660 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 664 /* 665 * Shared interrupt 0 is routed only to AON/SPE, so 666 * we only have 4 shared interrupts for the CCPLEX. 667 */ 668 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 669 #mbox-cells = <2>; 670 }; 671 672 gen2_i2c: i2c@c240000 { 673 compatible = "nvidia,tegra194-i2c"; 674 reg = <0x0c240000 0x10000>; 675 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 clocks = <&bpmp TEGRA194_CLK_I2C2>; 679 clock-names = "div-clk"; 680 resets = <&bpmp TEGRA194_RESET_I2C2>; 681 reset-names = "i2c"; 682 status = "disabled"; 683 }; 684 685 gen8_i2c: i2c@c250000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0c250000 0x10000>; 688 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 clocks = <&bpmp TEGRA194_CLK_I2C8>; 692 clock-names = "div-clk"; 693 resets = <&bpmp TEGRA194_RESET_I2C8>; 694 reset-names = "i2c"; 695 status = "disabled"; 696 }; 697 698 uartc: serial@c280000 { 699 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 700 reg = <0x0c280000 0x40>; 701 reg-shift = <2>; 702 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&bpmp TEGRA194_CLK_UARTC>; 704 clock-names = "serial"; 705 resets = <&bpmp TEGRA194_RESET_UARTC>; 706 reset-names = "serial"; 707 status = "disabled"; 708 }; 709 710 uartg: serial@c290000 { 711 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 712 reg = <0x0c290000 0x40>; 713 reg-shift = <2>; 714 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&bpmp TEGRA194_CLK_UARTG>; 716 clock-names = "serial"; 717 resets = <&bpmp TEGRA194_RESET_UARTG>; 718 reset-names = "serial"; 719 status = "disabled"; 720 }; 721 722 rtc: rtc@c2a0000 { 723 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 724 reg = <0x0c2a0000 0x10000>; 725 interrupt-parent = <&pmc>; 726 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 728 clock-names = "rtc"; 729 status = "disabled"; 730 }; 731 732 gpio_aon: gpio@c2f0000 { 733 compatible = "nvidia,tegra194-gpio-aon"; 734 reg-names = "security", "gpio"; 735 reg = <0xc2f0000 0x1000>, 736 <0xc2f1000 0x1000>; 737 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 741 gpio-controller; 742 #gpio-cells = <2>; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 pwm4: pwm@c340000 { 748 compatible = "nvidia,tegra194-pwm", 749 "nvidia,tegra186-pwm"; 750 reg = <0xc340000 0x10000>; 751 clocks = <&bpmp TEGRA194_CLK_PWM4>; 752 clock-names = "pwm"; 753 resets = <&bpmp TEGRA194_RESET_PWM4>; 754 reset-names = "pwm"; 755 status = "disabled"; 756 #pwm-cells = <2>; 757 }; 758 759 pmc: pmc@c360000 { 760 compatible = "nvidia,tegra194-pmc"; 761 reg = <0x0c360000 0x10000>, 762 <0x0c370000 0x10000>, 763 <0x0c380000 0x10000>, 764 <0x0c390000 0x10000>, 765 <0x0c3a0000 0x10000>; 766 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 767 768 #interrupt-cells = <2>; 769 interrupt-controller; 770 }; 771 772 host1x@13e00000 { 773 compatible = "nvidia,tegra194-host1x", "simple-bus"; 774 reg = <0x13e00000 0x10000>, 775 <0x13e10000 0x10000>; 776 reg-names = "hypervisor", "vm"; 777 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 780 clock-names = "host1x"; 781 resets = <&bpmp TEGRA194_RESET_HOST1X>; 782 reset-names = "host1x"; 783 784 #address-cells = <1>; 785 #size-cells = <1>; 786 787 ranges = <0x15000000 0x15000000 0x01000000>; 788 789 display-hub@15200000 { 790 compatible = "nvidia,tegra194-display", "simple-bus"; 791 reg = <0x15200000 0x00040000>; 792 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 793 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 794 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 795 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 796 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 797 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 798 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 799 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 800 "wgrp3", "wgrp4", "wgrp5"; 801 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 802 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 803 clock-names = "disp", "hub"; 804 status = "disabled"; 805 806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 807 808 #address-cells = <1>; 809 #size-cells = <1>; 810 811 ranges = <0x15200000 0x15200000 0x40000>; 812 813 display@15200000 { 814 compatible = "nvidia,tegra194-dc"; 815 reg = <0x15200000 0x10000>; 816 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 818 clock-names = "dc"; 819 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 820 reset-names = "dc"; 821 822 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 823 824 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 825 nvidia,head = <0>; 826 }; 827 828 display@15210000 { 829 compatible = "nvidia,tegra194-dc"; 830 reg = <0x15210000 0x10000>; 831 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 833 clock-names = "dc"; 834 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 835 reset-names = "dc"; 836 837 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 838 839 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 840 nvidia,head = <1>; 841 }; 842 843 display@15220000 { 844 compatible = "nvidia,tegra194-dc"; 845 reg = <0x15220000 0x10000>; 846 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 848 clock-names = "dc"; 849 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 850 reset-names = "dc"; 851 852 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 853 854 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 855 nvidia,head = <2>; 856 }; 857 858 display@15230000 { 859 compatible = "nvidia,tegra194-dc"; 860 reg = <0x15230000 0x10000>; 861 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 863 clock-names = "dc"; 864 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 865 reset-names = "dc"; 866 867 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 868 869 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 870 nvidia,head = <3>; 871 }; 872 }; 873 874 vic@15340000 { 875 compatible = "nvidia,tegra194-vic"; 876 reg = <0x15340000 0x00040000>; 877 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&bpmp TEGRA194_CLK_VIC>; 879 clock-names = "vic"; 880 resets = <&bpmp TEGRA194_RESET_VIC>; 881 reset-names = "vic"; 882 883 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 884 }; 885 886 dpaux0: dpaux@155c0000 { 887 compatible = "nvidia,tegra194-dpaux"; 888 reg = <0x155c0000 0x10000>; 889 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 891 <&bpmp TEGRA194_CLK_PLLDP>; 892 clock-names = "dpaux", "parent"; 893 resets = <&bpmp TEGRA194_RESET_DPAUX>; 894 reset-names = "dpaux"; 895 status = "disabled"; 896 897 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 898 899 state_dpaux0_aux: pinmux-aux { 900 groups = "dpaux-io"; 901 function = "aux"; 902 }; 903 904 state_dpaux0_i2c: pinmux-i2c { 905 groups = "dpaux-io"; 906 function = "i2c"; 907 }; 908 909 state_dpaux0_off: pinmux-off { 910 groups = "dpaux-io"; 911 function = "off"; 912 }; 913 914 i2c-bus { 915 #address-cells = <1>; 916 #size-cells = <0>; 917 }; 918 }; 919 920 dpaux1: dpaux@155d0000 { 921 compatible = "nvidia,tegra194-dpaux"; 922 reg = <0x155d0000 0x10000>; 923 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 925 <&bpmp TEGRA194_CLK_PLLDP>; 926 clock-names = "dpaux", "parent"; 927 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 928 reset-names = "dpaux"; 929 status = "disabled"; 930 931 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 932 933 state_dpaux1_aux: pinmux-aux { 934 groups = "dpaux-io"; 935 function = "aux"; 936 }; 937 938 state_dpaux1_i2c: pinmux-i2c { 939 groups = "dpaux-io"; 940 function = "i2c"; 941 }; 942 943 state_dpaux1_off: pinmux-off { 944 groups = "dpaux-io"; 945 function = "off"; 946 }; 947 948 i2c-bus { 949 #address-cells = <1>; 950 #size-cells = <0>; 951 }; 952 }; 953 954 dpaux2: dpaux@155e0000 { 955 compatible = "nvidia,tegra194-dpaux"; 956 reg = <0x155e0000 0x10000>; 957 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 959 <&bpmp TEGRA194_CLK_PLLDP>; 960 clock-names = "dpaux", "parent"; 961 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 962 reset-names = "dpaux"; 963 status = "disabled"; 964 965 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 966 967 state_dpaux2_aux: pinmux-aux { 968 groups = "dpaux-io"; 969 function = "aux"; 970 }; 971 972 state_dpaux2_i2c: pinmux-i2c { 973 groups = "dpaux-io"; 974 function = "i2c"; 975 }; 976 977 state_dpaux2_off: pinmux-off { 978 groups = "dpaux-io"; 979 function = "off"; 980 }; 981 982 i2c-bus { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 }; 986 }; 987 988 dpaux3: dpaux@155f0000 { 989 compatible = "nvidia,tegra194-dpaux"; 990 reg = <0x155f0000 0x10000>; 991 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 993 <&bpmp TEGRA194_CLK_PLLDP>; 994 clock-names = "dpaux", "parent"; 995 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 996 reset-names = "dpaux"; 997 status = "disabled"; 998 999 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1000 1001 state_dpaux3_aux: pinmux-aux { 1002 groups = "dpaux-io"; 1003 function = "aux"; 1004 }; 1005 1006 state_dpaux3_i2c: pinmux-i2c { 1007 groups = "dpaux-io"; 1008 function = "i2c"; 1009 }; 1010 1011 state_dpaux3_off: pinmux-off { 1012 groups = "dpaux-io"; 1013 function = "off"; 1014 }; 1015 1016 i2c-bus { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 }; 1020 }; 1021 1022 sor0: sor@15b00000 { 1023 compatible = "nvidia,tegra194-sor"; 1024 reg = <0x15b00000 0x40000>; 1025 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1027 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1028 <&bpmp TEGRA194_CLK_PLLD>, 1029 <&bpmp TEGRA194_CLK_PLLDP>, 1030 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1031 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1032 clock-names = "sor", "out", "parent", "dp", "safe", 1033 "pad"; 1034 resets = <&bpmp TEGRA194_RESET_SOR0>; 1035 reset-names = "sor"; 1036 pinctrl-0 = <&state_dpaux0_aux>; 1037 pinctrl-1 = <&state_dpaux0_i2c>; 1038 pinctrl-2 = <&state_dpaux0_off>; 1039 pinctrl-names = "aux", "i2c", "off"; 1040 status = "disabled"; 1041 1042 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1043 nvidia,interface = <0>; 1044 }; 1045 1046 sor1: sor@15b40000 { 1047 compatible = "nvidia,tegra194-sor"; 1048 reg = <0x155c0000 0x40000>; 1049 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1051 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1052 <&bpmp TEGRA194_CLK_PLLD2>, 1053 <&bpmp TEGRA194_CLK_PLLDP>, 1054 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1055 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1056 clock-names = "sor", "out", "parent", "dp", "safe", 1057 "pad"; 1058 resets = <&bpmp TEGRA194_RESET_SOR1>; 1059 reset-names = "sor"; 1060 pinctrl-0 = <&state_dpaux1_aux>; 1061 pinctrl-1 = <&state_dpaux1_i2c>; 1062 pinctrl-2 = <&state_dpaux1_off>; 1063 pinctrl-names = "aux", "i2c", "off"; 1064 status = "disabled"; 1065 1066 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1067 nvidia,interface = <1>; 1068 }; 1069 1070 sor2: sor@15b80000 { 1071 compatible = "nvidia,tegra194-sor"; 1072 reg = <0x15b80000 0x40000>; 1073 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1075 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1076 <&bpmp TEGRA194_CLK_PLLD3>, 1077 <&bpmp TEGRA194_CLK_PLLDP>, 1078 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1079 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1080 clock-names = "sor", "out", "parent", "dp", "safe", 1081 "pad"; 1082 resets = <&bpmp TEGRA194_RESET_SOR2>; 1083 reset-names = "sor"; 1084 pinctrl-0 = <&state_dpaux2_aux>; 1085 pinctrl-1 = <&state_dpaux2_i2c>; 1086 pinctrl-2 = <&state_dpaux2_off>; 1087 pinctrl-names = "aux", "i2c", "off"; 1088 status = "disabled"; 1089 1090 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1091 nvidia,interface = <2>; 1092 }; 1093 1094 sor3: sor@15bc0000 { 1095 compatible = "nvidia,tegra194-sor"; 1096 reg = <0x15bc0000 0x40000>; 1097 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1099 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1100 <&bpmp TEGRA194_CLK_PLLD4>, 1101 <&bpmp TEGRA194_CLK_PLLDP>, 1102 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1103 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1104 clock-names = "sor", "out", "parent", "dp", "safe", 1105 "pad"; 1106 resets = <&bpmp TEGRA194_RESET_SOR3>; 1107 reset-names = "sor"; 1108 pinctrl-0 = <&state_dpaux3_aux>; 1109 pinctrl-1 = <&state_dpaux3_i2c>; 1110 pinctrl-2 = <&state_dpaux3_off>; 1111 pinctrl-names = "aux", "i2c", "off"; 1112 status = "disabled"; 1113 1114 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1115 nvidia,interface = <3>; 1116 }; 1117 }; 1118 }; 1119 1120 pcie@14100000 { 1121 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1122 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1123 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 1124 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 1125 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1126 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1127 reg-names = "appl", "config", "atu_dma", "dbi"; 1128 1129 status = "disabled"; 1130 1131 #address-cells = <3>; 1132 #size-cells = <2>; 1133 device_type = "pci"; 1134 num-lanes = <1>; 1135 num-viewport = <8>; 1136 linux,pci-domain = <1>; 1137 1138 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1139 clock-names = "core"; 1140 1141 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1142 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1143 reset-names = "apb", "core"; 1144 1145 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1146 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1147 interrupt-names = "intr", "msi"; 1148 1149 #interrupt-cells = <1>; 1150 interrupt-map-mask = <0 0 0 0>; 1151 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1152 1153 nvidia,bpmp = <&bpmp 1>; 1154 1155 supports-clkreq; 1156 nvidia,aspm-cmrt-us = <60>; 1157 nvidia,aspm-pwr-on-t-us = <20>; 1158 nvidia,aspm-l0s-entrance-latency-us = <3>; 1159 1160 bus-range = <0x0 0xff>; 1161 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1162 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1163 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1164 }; 1165 1166 pcie@14120000 { 1167 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1168 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1169 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 1170 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 1171 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1172 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1173 reg-names = "appl", "config", "atu_dma", "dbi"; 1174 1175 status = "disabled"; 1176 1177 #address-cells = <3>; 1178 #size-cells = <2>; 1179 device_type = "pci"; 1180 num-lanes = <1>; 1181 num-viewport = <8>; 1182 linux,pci-domain = <2>; 1183 1184 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1185 clock-names = "core"; 1186 1187 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1188 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1189 reset-names = "apb", "core"; 1190 1191 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1192 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1193 interrupt-names = "intr", "msi"; 1194 1195 #interrupt-cells = <1>; 1196 interrupt-map-mask = <0 0 0 0>; 1197 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1198 1199 nvidia,bpmp = <&bpmp 2>; 1200 1201 supports-clkreq; 1202 nvidia,aspm-cmrt-us = <60>; 1203 nvidia,aspm-pwr-on-t-us = <20>; 1204 nvidia,aspm-l0s-entrance-latency-us = <3>; 1205 1206 bus-range = <0x0 0xff>; 1207 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1208 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1209 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1210 }; 1211 1212 pcie@14140000 { 1213 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1214 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1215 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 1216 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 1217 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1218 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1219 reg-names = "appl", "config", "atu_dma", "dbi"; 1220 1221 status = "disabled"; 1222 1223 #address-cells = <3>; 1224 #size-cells = <2>; 1225 device_type = "pci"; 1226 num-lanes = <1>; 1227 num-viewport = <8>; 1228 linux,pci-domain = <3>; 1229 1230 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1231 clock-names = "core"; 1232 1233 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1234 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1235 reset-names = "apb", "core"; 1236 1237 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1238 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1239 interrupt-names = "intr", "msi"; 1240 1241 #interrupt-cells = <1>; 1242 interrupt-map-mask = <0 0 0 0>; 1243 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1244 1245 nvidia,bpmp = <&bpmp 3>; 1246 1247 supports-clkreq; 1248 nvidia,aspm-cmrt-us = <60>; 1249 nvidia,aspm-pwr-on-t-us = <20>; 1250 nvidia,aspm-l0s-entrance-latency-us = <3>; 1251 1252 bus-range = <0x0 0xff>; 1253 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1254 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1255 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1256 }; 1257 1258 pcie@14160000 { 1259 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1260 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1261 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1262 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 1263 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1264 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1265 reg-names = "appl", "config", "atu_dma", "dbi"; 1266 1267 status = "disabled"; 1268 1269 #address-cells = <3>; 1270 #size-cells = <2>; 1271 device_type = "pci"; 1272 num-lanes = <4>; 1273 num-viewport = <8>; 1274 linux,pci-domain = <4>; 1275 1276 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1277 clock-names = "core"; 1278 1279 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1280 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1281 reset-names = "apb", "core"; 1282 1283 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1284 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1285 interrupt-names = "intr", "msi"; 1286 1287 #interrupt-cells = <1>; 1288 interrupt-map-mask = <0 0 0 0>; 1289 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1290 1291 nvidia,bpmp = <&bpmp 4>; 1292 1293 supports-clkreq; 1294 nvidia,aspm-cmrt-us = <60>; 1295 nvidia,aspm-pwr-on-t-us = <20>; 1296 nvidia,aspm-l0s-entrance-latency-us = <3>; 1297 1298 bus-range = <0x0 0xff>; 1299 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1300 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1301 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1302 }; 1303 1304 pcie@14180000 { 1305 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1306 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1307 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1308 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 1309 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1310 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1311 reg-names = "appl", "config", "atu_dma", "dbi"; 1312 1313 status = "disabled"; 1314 1315 #address-cells = <3>; 1316 #size-cells = <2>; 1317 device_type = "pci"; 1318 num-lanes = <8>; 1319 num-viewport = <8>; 1320 linux,pci-domain = <0>; 1321 1322 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1323 clock-names = "core"; 1324 1325 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1326 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1327 reset-names = "apb", "core"; 1328 1329 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1330 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1331 interrupt-names = "intr", "msi"; 1332 1333 #interrupt-cells = <1>; 1334 interrupt-map-mask = <0 0 0 0>; 1335 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1336 1337 nvidia,bpmp = <&bpmp 0>; 1338 1339 supports-clkreq; 1340 nvidia,aspm-cmrt-us = <60>; 1341 nvidia,aspm-pwr-on-t-us = <20>; 1342 nvidia,aspm-l0s-entrance-latency-us = <3>; 1343 1344 bus-range = <0x0 0xff>; 1345 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1346 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1347 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1348 }; 1349 1350 pcie@141a0000 { 1351 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1352 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1353 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1354 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 1355 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1356 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1357 reg-names = "appl", "config", "atu_dma", "dbi"; 1358 1359 status = "disabled"; 1360 1361 #address-cells = <3>; 1362 #size-cells = <2>; 1363 device_type = "pci"; 1364 num-lanes = <8>; 1365 num-viewport = <8>; 1366 linux,pci-domain = <5>; 1367 1368 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1369 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1370 clock-names = "core", "core_m"; 1371 1372 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1373 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1374 reset-names = "apb", "core"; 1375 1376 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1377 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1378 interrupt-names = "intr", "msi"; 1379 1380 nvidia,bpmp = <&bpmp 5>; 1381 1382 #interrupt-cells = <1>; 1383 interrupt-map-mask = <0 0 0 0>; 1384 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1385 1386 supports-clkreq; 1387 nvidia,aspm-cmrt-us = <60>; 1388 nvidia,aspm-pwr-on-t-us = <20>; 1389 nvidia,aspm-l0s-entrance-latency-us = <3>; 1390 1391 bus-range = <0x0 0xff>; 1392 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1393 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1394 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1395 }; 1396 1397 sysram@40000000 { 1398 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1399 reg = <0x0 0x40000000 0x0 0x50000>; 1400 #address-cells = <1>; 1401 #size-cells = <1>; 1402 ranges = <0x0 0x0 0x40000000 0x50000>; 1403 1404 cpu_bpmp_tx: shmem@4e000 { 1405 compatible = "nvidia,tegra194-bpmp-shmem"; 1406 reg = <0x4e000 0x1000>; 1407 label = "cpu-bpmp-tx"; 1408 pool; 1409 }; 1410 1411 cpu_bpmp_rx: shmem@4f000 { 1412 compatible = "nvidia,tegra194-bpmp-shmem"; 1413 reg = <0x4f000 0x1000>; 1414 label = "cpu-bpmp-rx"; 1415 pool; 1416 }; 1417 }; 1418 1419 bpmp: bpmp { 1420 compatible = "nvidia,tegra186-bpmp"; 1421 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1422 TEGRA_HSP_DB_MASTER_BPMP>; 1423 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1424 #clock-cells = <1>; 1425 #reset-cells = <1>; 1426 #power-domain-cells = <1>; 1427 1428 bpmp_i2c: i2c { 1429 compatible = "nvidia,tegra186-bpmp-i2c"; 1430 nvidia,bpmp-bus-id = <5>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 }; 1434 1435 bpmp_thermal: thermal { 1436 compatible = "nvidia,tegra186-bpmp-thermal"; 1437 #thermal-sensor-cells = <1>; 1438 }; 1439 }; 1440 1441 cpus { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 cpu@0 { 1446 compatible = "nvidia,tegra194-carmel"; 1447 device_type = "cpu"; 1448 reg = <0x10000>; 1449 enable-method = "psci"; 1450 }; 1451 1452 cpu@1 { 1453 compatible = "nvidia,tegra194-carmel"; 1454 device_type = "cpu"; 1455 reg = <0x10001>; 1456 enable-method = "psci"; 1457 }; 1458 1459 cpu@2 { 1460 compatible = "nvidia,tegra194-carmel"; 1461 device_type = "cpu"; 1462 reg = <0x100>; 1463 enable-method = "psci"; 1464 }; 1465 1466 cpu@3 { 1467 compatible = "nvidia,tegra194-carmel"; 1468 device_type = "cpu"; 1469 reg = <0x101>; 1470 enable-method = "psci"; 1471 }; 1472 1473 cpu@4 { 1474 compatible = "nvidia,tegra194-carmel"; 1475 device_type = "cpu"; 1476 reg = <0x200>; 1477 enable-method = "psci"; 1478 }; 1479 1480 cpu@5 { 1481 compatible = "nvidia,tegra194-carmel"; 1482 device_type = "cpu"; 1483 reg = <0x201>; 1484 enable-method = "psci"; 1485 }; 1486 1487 cpu@6 { 1488 compatible = "nvidia,tegra194-carmel"; 1489 device_type = "cpu"; 1490 reg = <0x10300>; 1491 enable-method = "psci"; 1492 }; 1493 1494 cpu@7 { 1495 compatible = "nvidia,tegra194-carmel"; 1496 device_type = "cpu"; 1497 reg = <0x10301>; 1498 enable-method = "psci"; 1499 }; 1500 }; 1501 1502 psci { 1503 compatible = "arm,psci-1.0"; 1504 status = "okay"; 1505 method = "smc"; 1506 }; 1507 1508 tcu: tcu { 1509 compatible = "nvidia,tegra194-tcu"; 1510 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1511 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1512 mbox-names = "rx", "tx"; 1513 }; 1514 1515 thermal-zones { 1516 cpu { 1517 thermal-sensors = <&{/bpmp/thermal} 1518 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1519 status = "disabled"; 1520 }; 1521 1522 gpu { 1523 thermal-sensors = <&{/bpmp/thermal} 1524 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1525 status = "disabled"; 1526 }; 1527 1528 aux { 1529 thermal-sensors = <&{/bpmp/thermal} 1530 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1531 status = "disabled"; 1532 }; 1533 1534 pllx { 1535 thermal-sensors = <&{/bpmp/thermal} 1536 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1537 status = "disabled"; 1538 }; 1539 1540 ao { 1541 thermal-sensors = <&{/bpmp/thermal} 1542 TEGRA194_BPMP_THERMAL_ZONE_AO>; 1543 status = "disabled"; 1544 }; 1545 1546 tj { 1547 thermal-sensors = <&{/bpmp/thermal} 1548 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1549 status = "disabled"; 1550 }; 1551 }; 1552 1553 timer { 1554 compatible = "arm,armv8-timer"; 1555 interrupts = <GIC_PPI 13 1556 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1557 <GIC_PPI 14 1558 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1559 <GIC_PPI 11 1560 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1561 <GIC_PPI 10 1562 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1563 interrupt-parent = <&gic>; 1564 always-on; 1565 }; 1566}; 1567