1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7 8/ { 9 compatible = "nvidia,tegra194"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 /* control backbone */ 15 cbb { 16 compatible = "simple-bus"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 ranges = <0x0 0x0 0x0 0x40000000>; 20 21 gpio: gpio@2200000 { 22 compatible = "nvidia,tegra194-gpio"; 23 reg-names = "security", "gpio"; 24 reg = <0x2200000 0x10000>, 25 <0x2210000 0x10000>; 26 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 32 #interrupt-cells = <2>; 33 interrupt-controller; 34 #gpio-cells = <2>; 35 gpio-controller; 36 }; 37 38 uarta: serial@3100000 { 39 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 40 reg = <0x03100000 0x40>; 41 reg-shift = <2>; 42 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 43 clocks = <&bpmp TEGRA194_CLK_UARTA>; 44 clock-names = "serial"; 45 resets = <&bpmp TEGRA194_RESET_UARTA>; 46 reset-names = "serial"; 47 status = "disabled"; 48 }; 49 50 uartb: serial@3110000 { 51 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 52 reg = <0x03110000 0x40>; 53 reg-shift = <2>; 54 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 55 clocks = <&bpmp TEGRA194_CLK_UARTB>; 56 clock-names = "serial"; 57 resets = <&bpmp TEGRA194_RESET_UARTB>; 58 reset-names = "serial"; 59 status = "disabled"; 60 }; 61 62 uartd: serial@3130000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03130000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTD>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTD>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uarte: serial@3140000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03140000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTE>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTE>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartf: serial@3150000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03150000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTF>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTF>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 gen1_i2c: i2c@3160000 { 99 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 100 reg = <0x03160000 0x10000>; 101 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 clocks = <&bpmp TEGRA194_CLK_I2C1>; 105 clock-names = "div-clk"; 106 resets = <&bpmp TEGRA194_RESET_I2C1>; 107 reset-names = "i2c"; 108 status = "disabled"; 109 }; 110 111 uarth: serial@3170000 { 112 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 113 reg = <0x03170000 0x40>; 114 reg-shift = <2>; 115 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&bpmp TEGRA194_CLK_UARTH>; 117 clock-names = "serial"; 118 resets = <&bpmp TEGRA194_RESET_UARTH>; 119 reset-names = "serial"; 120 status = "disabled"; 121 }; 122 123 cam_i2c: i2c@3180000 { 124 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 125 reg = <0x03180000 0x10000>; 126 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 clocks = <&bpmp TEGRA194_CLK_I2C3>; 130 clock-names = "div-clk"; 131 resets = <&bpmp TEGRA194_RESET_I2C3>; 132 reset-names = "i2c"; 133 status = "disabled"; 134 }; 135 136 /* shares pads with dpaux1 */ 137 dp_aux_ch1_i2c: i2c@3190000 { 138 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 139 reg = <0x03190000 0x10000>; 140 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 clocks = <&bpmp TEGRA194_CLK_I2C4>; 144 clock-names = "div-clk"; 145 resets = <&bpmp TEGRA194_RESET_I2C4>; 146 reset-names = "i2c"; 147 status = "disabled"; 148 }; 149 150 /* shares pads with dpaux0 */ 151 dp_aux_ch0_i2c: i2c@31b0000 { 152 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x031b0000 0x10000>; 154 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA194_CLK_I2C6>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA194_RESET_I2C6>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 gen7_i2c: i2c@31c0000 { 165 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 166 reg = <0x031c0000 0x10000>; 167 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clocks = <&bpmp TEGRA194_CLK_I2C7>; 171 clock-names = "div-clk"; 172 resets = <&bpmp TEGRA194_RESET_I2C7>; 173 reset-names = "i2c"; 174 status = "disabled"; 175 }; 176 177 gen9_i2c: i2c@31e0000 { 178 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 179 reg = <0x031e0000 0x10000>; 180 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 clocks = <&bpmp TEGRA194_CLK_I2C9>; 184 clock-names = "div-clk"; 185 resets = <&bpmp TEGRA194_RESET_I2C9>; 186 reset-names = "i2c"; 187 status = "disabled"; 188 }; 189 190 sdmmc1: sdhci@3400000 { 191 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 192 reg = <0x03400000 0x10000>; 193 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 195 clock-names = "sdhci"; 196 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 197 reset-names = "sdhci"; 198 status = "disabled"; 199 }; 200 201 sdmmc3: sdhci@3440000 { 202 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 203 reg = <0x03440000 0x10000>; 204 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 206 clock-names = "sdhci"; 207 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 208 reset-names = "sdhci"; 209 status = "disabled"; 210 }; 211 212 sdmmc4: sdhci@3460000 { 213 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 214 reg = <0x03460000 0x10000>; 215 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 217 clock-names = "sdhci"; 218 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 219 reset-names = "sdhci"; 220 status = "disabled"; 221 }; 222 223 gic: interrupt-controller@3881000 { 224 compatible = "arm,gic-400"; 225 #interrupt-cells = <3>; 226 interrupt-controller; 227 reg = <0x03881000 0x1000>, 228 <0x03882000 0x2000>, 229 <0x03884000 0x2000>, 230 <0x03886000 0x2000>; 231 interrupts = <GIC_PPI 9 232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 233 interrupt-parent = <&gic>; 234 }; 235 236 hsp_top0: hsp@3c00000 { 237 compatible = "nvidia,tegra186-hsp"; 238 reg = <0x03c00000 0xa0000>; 239 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 240 interrupt-names = "doorbell"; 241 #mbox-cells = <2>; 242 }; 243 244 gen2_i2c: i2c@c240000 { 245 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 246 reg = <0x0c240000 0x10000>; 247 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 clocks = <&bpmp TEGRA194_CLK_I2C2>; 251 clock-names = "div-clk"; 252 resets = <&bpmp TEGRA194_RESET_I2C2>; 253 reset-names = "i2c"; 254 status = "disabled"; 255 }; 256 257 gen8_i2c: i2c@c250000 { 258 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c"; 259 reg = <0x0c250000 0x10000>; 260 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 clocks = <&bpmp TEGRA194_CLK_I2C8>; 264 clock-names = "div-clk"; 265 resets = <&bpmp TEGRA194_RESET_I2C8>; 266 reset-names = "i2c"; 267 status = "disabled"; 268 }; 269 270 uartc: serial@c280000 { 271 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 272 reg = <0x0c280000 0x40>; 273 reg-shift = <2>; 274 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&bpmp TEGRA194_CLK_UARTC>; 276 clock-names = "serial"; 277 resets = <&bpmp TEGRA194_RESET_UARTC>; 278 reset-names = "serial"; 279 status = "disabled"; 280 }; 281 282 uartg: serial@c290000 { 283 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 284 reg = <0x0c290000 0x40>; 285 reg-shift = <2>; 286 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&bpmp TEGRA194_CLK_UARTG>; 288 clock-names = "serial"; 289 resets = <&bpmp TEGRA194_RESET_UARTG>; 290 reset-names = "serial"; 291 status = "disabled"; 292 }; 293 294 pmc@c360000 { 295 compatible = "nvidia,tegra194-pmc"; 296 reg = <0x0c360000 0x10000>, 297 <0x0c370000 0x10000>, 298 <0x0c380000 0x10000>, 299 <0x0c390000 0x10000>, 300 <0x0c3a0000 0x10000>; 301 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 302 }; 303 }; 304 305 sysram@40000000 { 306 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 307 reg = <0x0 0x40000000 0x0 0x50000>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0x0 0x0 0x40000000 0x50000>; 311 312 cpu_bpmp_tx: shmem@4e000 { 313 compatible = "nvidia,tegra194-bpmp-shmem"; 314 reg = <0x4e000 0x1000>; 315 label = "cpu-bpmp-tx"; 316 pool; 317 }; 318 319 cpu_bpmp_rx: shmem@4f000 { 320 compatible = "nvidia,tegra194-bpmp-shmem"; 321 reg = <0x4f000 0x1000>; 322 label = "cpu-bpmp-rx"; 323 pool; 324 }; 325 }; 326 327 bpmp: bpmp { 328 compatible = "nvidia,tegra186-bpmp"; 329 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 330 TEGRA_HSP_DB_MASTER_BPMP>; 331 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 332 #clock-cells = <1>; 333 #reset-cells = <1>; 334 #power-domain-cells = <1>; 335 336 bpmp_i2c: i2c { 337 compatible = "nvidia,tegra186-bpmp-i2c"; 338 nvidia,bpmp-bus-id = <5>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 }; 342 343 bpmp_thermal: thermal { 344 compatible = "nvidia,tegra186-bpmp-thermal"; 345 #thermal-sensor-cells = <1>; 346 }; 347 }; 348 349 timer { 350 compatible = "arm,armv8-timer"; 351 interrupts = <GIC_PPI 13 352 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 353 <GIC_PPI 14 354 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 355 <GIC_PPI 11 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 357 <GIC_PPI 10 358 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 359 interrupt-parent = <&gic>; 360 }; 361}; 362