1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7 8/ { 9 compatible = "nvidia,tegra194"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 /* control backbone */ 15 cbb { 16 compatible = "simple-bus"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 ranges = <0x0 0x0 0x0 0x40000000>; 20 21 gpio: gpio@2200000 { 22 compatible = "nvidia,tegra194-gpio"; 23 reg-names = "security", "gpio"; 24 reg = <0x2200000 0x10000>, 25 <0x2210000 0x10000>; 26 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 32 #interrupt-cells = <2>; 33 interrupt-controller; 34 #gpio-cells = <2>; 35 gpio-controller; 36 }; 37 38 ethernet@2490000 { 39 compatible = "nvidia,tegra186-eqos", 40 "snps,dwc-qos-ethernet-4.10"; 41 reg = <0x02490000 0x10000>; 42 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 43 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 44 <&bpmp TEGRA194_CLK_EQOS_AXI>, 45 <&bpmp TEGRA194_CLK_EQOS_RX>, 46 <&bpmp TEGRA194_CLK_EQOS_TX>, 47 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 48 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 49 resets = <&bpmp TEGRA194_RESET_EQOS>; 50 reset-names = "eqos"; 51 status = "disabled"; 52 53 snps,write-requests = <1>; 54 snps,read-requests = <3>; 55 snps,burst-map = <0x7>; 56 snps,txpbl = <16>; 57 snps,rxpbl = <8>; 58 }; 59 60 uarta: serial@3100000 { 61 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 62 reg = <0x03100000 0x40>; 63 reg-shift = <2>; 64 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 65 clocks = <&bpmp TEGRA194_CLK_UARTA>; 66 clock-names = "serial"; 67 resets = <&bpmp TEGRA194_RESET_UARTA>; 68 reset-names = "serial"; 69 status = "disabled"; 70 }; 71 72 uartb: serial@3110000 { 73 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 74 reg = <0x03110000 0x40>; 75 reg-shift = <2>; 76 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 77 clocks = <&bpmp TEGRA194_CLK_UARTB>; 78 clock-names = "serial"; 79 resets = <&bpmp TEGRA194_RESET_UARTB>; 80 reset-names = "serial"; 81 status = "disabled"; 82 }; 83 84 uartd: serial@3130000 { 85 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 86 reg = <0x03130000 0x40>; 87 reg-shift = <2>; 88 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&bpmp TEGRA194_CLK_UARTD>; 90 clock-names = "serial"; 91 resets = <&bpmp TEGRA194_RESET_UARTD>; 92 reset-names = "serial"; 93 status = "disabled"; 94 }; 95 96 uarte: serial@3140000 { 97 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 98 reg = <0x03140000 0x40>; 99 reg-shift = <2>; 100 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&bpmp TEGRA194_CLK_UARTE>; 102 clock-names = "serial"; 103 resets = <&bpmp TEGRA194_RESET_UARTE>; 104 reset-names = "serial"; 105 status = "disabled"; 106 }; 107 108 uartf: serial@3150000 { 109 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 110 reg = <0x03150000 0x40>; 111 reg-shift = <2>; 112 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&bpmp TEGRA194_CLK_UARTF>; 114 clock-names = "serial"; 115 resets = <&bpmp TEGRA194_RESET_UARTF>; 116 reset-names = "serial"; 117 status = "disabled"; 118 }; 119 120 gen1_i2c: i2c@3160000 { 121 compatible = "nvidia,tegra194-i2c"; 122 reg = <0x03160000 0x10000>; 123 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 clocks = <&bpmp TEGRA194_CLK_I2C1>; 127 clock-names = "div-clk"; 128 resets = <&bpmp TEGRA194_RESET_I2C1>; 129 reset-names = "i2c"; 130 status = "disabled"; 131 }; 132 133 uarth: serial@3170000 { 134 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 135 reg = <0x03170000 0x40>; 136 reg-shift = <2>; 137 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&bpmp TEGRA194_CLK_UARTH>; 139 clock-names = "serial"; 140 resets = <&bpmp TEGRA194_RESET_UARTH>; 141 reset-names = "serial"; 142 status = "disabled"; 143 }; 144 145 cam_i2c: i2c@3180000 { 146 compatible = "nvidia,tegra194-i2c"; 147 reg = <0x03180000 0x10000>; 148 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 clocks = <&bpmp TEGRA194_CLK_I2C3>; 152 clock-names = "div-clk"; 153 resets = <&bpmp TEGRA194_RESET_I2C3>; 154 reset-names = "i2c"; 155 status = "disabled"; 156 }; 157 158 /* shares pads with dpaux1 */ 159 dp_aux_ch1_i2c: i2c@3190000 { 160 compatible = "nvidia,tegra194-i2c"; 161 reg = <0x03190000 0x10000>; 162 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 clocks = <&bpmp TEGRA194_CLK_I2C4>; 166 clock-names = "div-clk"; 167 resets = <&bpmp TEGRA194_RESET_I2C4>; 168 reset-names = "i2c"; 169 status = "disabled"; 170 }; 171 172 /* shares pads with dpaux0 */ 173 dp_aux_ch0_i2c: i2c@31b0000 { 174 compatible = "nvidia,tegra194-i2c"; 175 reg = <0x031b0000 0x10000>; 176 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 clocks = <&bpmp TEGRA194_CLK_I2C6>; 180 clock-names = "div-clk"; 181 resets = <&bpmp TEGRA194_RESET_I2C6>; 182 reset-names = "i2c"; 183 status = "disabled"; 184 }; 185 186 gen7_i2c: i2c@31c0000 { 187 compatible = "nvidia,tegra194-i2c"; 188 reg = <0x031c0000 0x10000>; 189 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 clocks = <&bpmp TEGRA194_CLK_I2C7>; 193 clock-names = "div-clk"; 194 resets = <&bpmp TEGRA194_RESET_I2C7>; 195 reset-names = "i2c"; 196 status = "disabled"; 197 }; 198 199 gen9_i2c: i2c@31e0000 { 200 compatible = "nvidia,tegra194-i2c"; 201 reg = <0x031e0000 0x10000>; 202 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 clocks = <&bpmp TEGRA194_CLK_I2C9>; 206 clock-names = "div-clk"; 207 resets = <&bpmp TEGRA194_RESET_I2C9>; 208 reset-names = "i2c"; 209 status = "disabled"; 210 }; 211 212 pwm1: pwm@3280000 { 213 compatible = "nvidia,tegra194-pwm", 214 "nvidia,tegra186-pwm"; 215 reg = <0x3280000 0x10000>; 216 clocks = <&bpmp TEGRA194_CLK_PWM1>; 217 clock-names = "pwm"; 218 resets = <&bpmp TEGRA194_RESET_PWM1>; 219 reset-names = "pwm"; 220 status = "disabled"; 221 #pwm-cells = <2>; 222 }; 223 224 pwm2: pwm@3290000 { 225 compatible = "nvidia,tegra194-pwm", 226 "nvidia,tegra186-pwm"; 227 reg = <0x3290000 0x10000>; 228 clocks = <&bpmp TEGRA194_CLK_PWM2>; 229 clock-names = "pwm"; 230 resets = <&bpmp TEGRA194_RESET_PWM2>; 231 reset-names = "pwm"; 232 status = "disabled"; 233 #pwm-cells = <2>; 234 }; 235 236 pwm3: pwm@32a0000 { 237 compatible = "nvidia,tegra194-pwm", 238 "nvidia,tegra186-pwm"; 239 reg = <0x32a0000 0x10000>; 240 clocks = <&bpmp TEGRA194_CLK_PWM3>; 241 clock-names = "pwm"; 242 resets = <&bpmp TEGRA194_RESET_PWM3>; 243 reset-names = "pwm"; 244 status = "disabled"; 245 #pwm-cells = <2>; 246 }; 247 248 pwm5: pwm@32c0000 { 249 compatible = "nvidia,tegra194-pwm", 250 "nvidia,tegra186-pwm"; 251 reg = <0x32c0000 0x10000>; 252 clocks = <&bpmp TEGRA194_CLK_PWM5>; 253 clock-names = "pwm"; 254 resets = <&bpmp TEGRA194_RESET_PWM5>; 255 reset-names = "pwm"; 256 status = "disabled"; 257 #pwm-cells = <2>; 258 }; 259 260 pwm6: pwm@32d0000 { 261 compatible = "nvidia,tegra194-pwm", 262 "nvidia,tegra186-pwm"; 263 reg = <0x32d0000 0x10000>; 264 clocks = <&bpmp TEGRA194_CLK_PWM6>; 265 clock-names = "pwm"; 266 resets = <&bpmp TEGRA194_RESET_PWM6>; 267 reset-names = "pwm"; 268 status = "disabled"; 269 #pwm-cells = <2>; 270 }; 271 272 pwm7: pwm@32e0000 { 273 compatible = "nvidia,tegra194-pwm", 274 "nvidia,tegra186-pwm"; 275 reg = <0x32e0000 0x10000>; 276 clocks = <&bpmp TEGRA194_CLK_PWM7>; 277 clock-names = "pwm"; 278 resets = <&bpmp TEGRA194_RESET_PWM7>; 279 reset-names = "pwm"; 280 status = "disabled"; 281 #pwm-cells = <2>; 282 }; 283 284 pwm8: pwm@32f0000 { 285 compatible = "nvidia,tegra194-pwm", 286 "nvidia,tegra186-pwm"; 287 reg = <0x32f0000 0x10000>; 288 clocks = <&bpmp TEGRA194_CLK_PWM8>; 289 clock-names = "pwm"; 290 resets = <&bpmp TEGRA194_RESET_PWM8>; 291 reset-names = "pwm"; 292 status = "disabled"; 293 #pwm-cells = <2>; 294 }; 295 296 sdmmc1: sdhci@3400000 { 297 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 298 reg = <0x03400000 0x10000>; 299 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 301 clock-names = "sdhci"; 302 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 303 reset-names = "sdhci"; 304 status = "disabled"; 305 }; 306 307 sdmmc3: sdhci@3440000 { 308 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 309 reg = <0x03440000 0x10000>; 310 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 312 clock-names = "sdhci"; 313 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 314 reset-names = "sdhci"; 315 status = "disabled"; 316 }; 317 318 sdmmc4: sdhci@3460000 { 319 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 320 reg = <0x03460000 0x10000>; 321 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 323 clock-names = "sdhci"; 324 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 325 reset-names = "sdhci"; 326 status = "disabled"; 327 }; 328 329 gic: interrupt-controller@3881000 { 330 compatible = "arm,gic-400"; 331 #interrupt-cells = <3>; 332 interrupt-controller; 333 reg = <0x03881000 0x1000>, 334 <0x03882000 0x2000>, 335 <0x03884000 0x2000>, 336 <0x03886000 0x2000>; 337 interrupts = <GIC_PPI 9 338 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 339 interrupt-parent = <&gic>; 340 }; 341 342 hsp_top0: hsp@3c00000 { 343 compatible = "nvidia,tegra186-hsp"; 344 reg = <0x03c00000 0xa0000>; 345 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-names = "doorbell"; 347 #mbox-cells = <2>; 348 }; 349 350 gen2_i2c: i2c@c240000 { 351 compatible = "nvidia,tegra194-i2c"; 352 reg = <0x0c240000 0x10000>; 353 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clocks = <&bpmp TEGRA194_CLK_I2C2>; 357 clock-names = "div-clk"; 358 resets = <&bpmp TEGRA194_RESET_I2C2>; 359 reset-names = "i2c"; 360 status = "disabled"; 361 }; 362 363 gen8_i2c: i2c@c250000 { 364 compatible = "nvidia,tegra194-i2c"; 365 reg = <0x0c250000 0x10000>; 366 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 clocks = <&bpmp TEGRA194_CLK_I2C8>; 370 clock-names = "div-clk"; 371 resets = <&bpmp TEGRA194_RESET_I2C8>; 372 reset-names = "i2c"; 373 status = "disabled"; 374 }; 375 376 uartc: serial@c280000 { 377 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 378 reg = <0x0c280000 0x40>; 379 reg-shift = <2>; 380 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&bpmp TEGRA194_CLK_UARTC>; 382 clock-names = "serial"; 383 resets = <&bpmp TEGRA194_RESET_UARTC>; 384 reset-names = "serial"; 385 status = "disabled"; 386 }; 387 388 uartg: serial@c290000 { 389 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 390 reg = <0x0c290000 0x40>; 391 reg-shift = <2>; 392 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&bpmp TEGRA194_CLK_UARTG>; 394 clock-names = "serial"; 395 resets = <&bpmp TEGRA194_RESET_UARTG>; 396 reset-names = "serial"; 397 status = "disabled"; 398 }; 399 400 pwm4: pwm@c340000 { 401 compatible = "nvidia,tegra194-pwm", 402 "nvidia,tegra186-pwm"; 403 reg = <0xc340000 0x10000>; 404 clocks = <&bpmp TEGRA194_CLK_PWM4>; 405 clock-names = "pwm"; 406 resets = <&bpmp TEGRA194_RESET_PWM4>; 407 reset-names = "pwm"; 408 status = "disabled"; 409 #pwm-cells = <2>; 410 }; 411 412 pmc@c360000 { 413 compatible = "nvidia,tegra194-pmc"; 414 reg = <0x0c360000 0x10000>, 415 <0x0c370000 0x10000>, 416 <0x0c380000 0x10000>, 417 <0x0c390000 0x10000>, 418 <0x0c3a0000 0x10000>; 419 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 420 }; 421 }; 422 423 sysram@40000000 { 424 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 425 reg = <0x0 0x40000000 0x0 0x50000>; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 ranges = <0x0 0x0 0x40000000 0x50000>; 429 430 cpu_bpmp_tx: shmem@4e000 { 431 compatible = "nvidia,tegra194-bpmp-shmem"; 432 reg = <0x4e000 0x1000>; 433 label = "cpu-bpmp-tx"; 434 pool; 435 }; 436 437 cpu_bpmp_rx: shmem@4f000 { 438 compatible = "nvidia,tegra194-bpmp-shmem"; 439 reg = <0x4f000 0x1000>; 440 label = "cpu-bpmp-rx"; 441 pool; 442 }; 443 }; 444 445 bpmp: bpmp { 446 compatible = "nvidia,tegra186-bpmp"; 447 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 448 TEGRA_HSP_DB_MASTER_BPMP>; 449 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 450 #clock-cells = <1>; 451 #reset-cells = <1>; 452 #power-domain-cells = <1>; 453 454 bpmp_i2c: i2c { 455 compatible = "nvidia,tegra186-bpmp-i2c"; 456 nvidia,bpmp-bus-id = <5>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 }; 460 461 bpmp_thermal: thermal { 462 compatible = "nvidia,tegra186-bpmp-thermal"; 463 #thermal-sensor-cells = <1>; 464 }; 465 }; 466 467 cpus { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 471 cpu@0 { 472 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 473 device_type = "cpu"; 474 reg = <0x10000>; 475 enable-method = "psci"; 476 }; 477 478 cpu@1 { 479 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 480 device_type = "cpu"; 481 reg = <0x10001>; 482 enable-method = "psci"; 483 }; 484 485 cpu@2 { 486 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 487 device_type = "cpu"; 488 reg = <0x100>; 489 enable-method = "psci"; 490 }; 491 492 cpu@3 { 493 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 494 device_type = "cpu"; 495 reg = <0x101>; 496 enable-method = "psci"; 497 }; 498 499 cpu@4 { 500 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 501 device_type = "cpu"; 502 reg = <0x200>; 503 enable-method = "psci"; 504 }; 505 506 cpu@5 { 507 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 508 device_type = "cpu"; 509 reg = <0x201>; 510 enable-method = "psci"; 511 }; 512 513 cpu@6 { 514 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 515 device_type = "cpu"; 516 reg = <0x10300>; 517 enable-method = "psci"; 518 }; 519 520 cpu@7 { 521 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 522 device_type = "cpu"; 523 reg = <0x10301>; 524 enable-method = "psci"; 525 }; 526 }; 527 528 psci { 529 compatible = "arm,psci-1.0"; 530 status = "okay"; 531 method = "smc"; 532 }; 533 534 timer { 535 compatible = "arm,armv8-timer"; 536 interrupts = <GIC_PPI 13 537 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 538 <GIC_PPI 14 539 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 540 <GIC_PPI 11 541 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 542 <GIC_PPI 10 543 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 544 interrupt-parent = <&gic>; 545 }; 546}; 547