1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 307 <0x07>; 308 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 309 <0x07>; 310 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 311 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 312 <0x07>; 313 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 314 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 315 nvidia,default-tap = <0x9>; 316 nvidia,default-trim = <0x5>; 317 status = "disabled"; 318 }; 319 320 sdmmc3: sdhci@3440000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03440000 0x10000>; 323 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 327 reset-names = "sdhci"; 328 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 329 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 330 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 331 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 332 <0x07>; 333 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 334 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 335 <0x07>; 336 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 337 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 338 nvidia,default-tap = <0x9>; 339 nvidia,default-trim = <0x5>; 340 status = "disabled"; 341 }; 342 343 sdmmc4: sdhci@3460000 { 344 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 345 reg = <0x03460000 0x10000>; 346 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 348 clock-names = "sdhci"; 349 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 350 reset-names = "sdhci"; 351 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 352 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 353 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 354 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 355 <0x0a>; 356 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 357 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 358 <0x0a>; 359 nvidia,default-tap = <0x8>; 360 nvidia,default-trim = <0x14>; 361 nvidia,dqs-trim = <40>; 362 status = "disabled"; 363 }; 364 365 hda@3510000 { 366 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 367 reg = <0x3510000 0x10000>; 368 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&bpmp TEGRA194_CLK_HDA>, 370 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 371 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 372 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 373 resets = <&bpmp TEGRA194_RESET_HDA>, 374 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 375 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 376 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 377 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 378 status = "disabled"; 379 }; 380 381 gic: interrupt-controller@3881000 { 382 compatible = "arm,gic-400"; 383 #interrupt-cells = <3>; 384 interrupt-controller; 385 reg = <0x03881000 0x1000>, 386 <0x03882000 0x2000>, 387 <0x03884000 0x2000>, 388 <0x03886000 0x2000>; 389 interrupts = <GIC_PPI 9 390 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 391 interrupt-parent = <&gic>; 392 }; 393 394 cec@3960000 { 395 compatible = "nvidia,tegra194-cec"; 396 reg = <0x03960000 0x10000>; 397 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&bpmp TEGRA194_CLK_CEC>; 399 clock-names = "cec"; 400 status = "disabled"; 401 }; 402 403 hsp_top0: hsp@3c00000 { 404 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 405 reg = <0x03c00000 0xa0000>; 406 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 416 "shared3", "shared4", "shared5", "shared6", 417 "shared7"; 418 #mbox-cells = <2>; 419 }; 420 421 hsp_aon: hsp@c150000 { 422 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 423 reg = <0x0c150000 0xa0000>; 424 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 428 /* 429 * Shared interrupt 0 is routed only to AON/SPE, so 430 * we only have 4 shared interrupts for the CCPLEX. 431 */ 432 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 433 #mbox-cells = <2>; 434 }; 435 436 gen2_i2c: i2c@c240000 { 437 compatible = "nvidia,tegra194-i2c"; 438 reg = <0x0c240000 0x10000>; 439 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&bpmp TEGRA194_CLK_I2C2>; 443 clock-names = "div-clk"; 444 resets = <&bpmp TEGRA194_RESET_I2C2>; 445 reset-names = "i2c"; 446 status = "disabled"; 447 }; 448 449 gen8_i2c: i2c@c250000 { 450 compatible = "nvidia,tegra194-i2c"; 451 reg = <0x0c250000 0x10000>; 452 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clocks = <&bpmp TEGRA194_CLK_I2C8>; 456 clock-names = "div-clk"; 457 resets = <&bpmp TEGRA194_RESET_I2C8>; 458 reset-names = "i2c"; 459 status = "disabled"; 460 }; 461 462 uartc: serial@c280000 { 463 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 464 reg = <0x0c280000 0x40>; 465 reg-shift = <2>; 466 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&bpmp TEGRA194_CLK_UARTC>; 468 clock-names = "serial"; 469 resets = <&bpmp TEGRA194_RESET_UARTC>; 470 reset-names = "serial"; 471 status = "disabled"; 472 }; 473 474 uartg: serial@c290000 { 475 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 476 reg = <0x0c290000 0x40>; 477 reg-shift = <2>; 478 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&bpmp TEGRA194_CLK_UARTG>; 480 clock-names = "serial"; 481 resets = <&bpmp TEGRA194_RESET_UARTG>; 482 reset-names = "serial"; 483 status = "disabled"; 484 }; 485 486 rtc: rtc@c2a0000 { 487 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 488 reg = <0x0c2a0000 0x10000>; 489 interrupt-parent = <&pmc>; 490 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 492 clock-names = "rtc"; 493 status = "disabled"; 494 }; 495 496 gpio_aon: gpio@c2f0000 { 497 compatible = "nvidia,tegra194-gpio-aon"; 498 reg-names = "security", "gpio"; 499 reg = <0xc2f0000 0x1000>, 500 <0xc2f1000 0x1000>; 501 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 511 pwm4: pwm@c340000 { 512 compatible = "nvidia,tegra194-pwm", 513 "nvidia,tegra186-pwm"; 514 reg = <0xc340000 0x10000>; 515 clocks = <&bpmp TEGRA194_CLK_PWM4>; 516 clock-names = "pwm"; 517 resets = <&bpmp TEGRA194_RESET_PWM4>; 518 reset-names = "pwm"; 519 status = "disabled"; 520 #pwm-cells = <2>; 521 }; 522 523 pmc: pmc@c360000 { 524 compatible = "nvidia,tegra194-pmc"; 525 reg = <0x0c360000 0x10000>, 526 <0x0c370000 0x10000>, 527 <0x0c380000 0x10000>, 528 <0x0c390000 0x10000>, 529 <0x0c3a0000 0x10000>; 530 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 531 532 #interrupt-cells = <2>; 533 interrupt-controller; 534 }; 535 536 host1x@13e00000 { 537 compatible = "nvidia,tegra194-host1x", "simple-bus"; 538 reg = <0x13e00000 0x10000>, 539 <0x13e10000 0x10000>; 540 reg-names = "hypervisor", "vm"; 541 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 544 clock-names = "host1x"; 545 resets = <&bpmp TEGRA194_RESET_HOST1X>; 546 reset-names = "host1x"; 547 548 #address-cells = <1>; 549 #size-cells = <1>; 550 551 ranges = <0x15000000 0x15000000 0x01000000>; 552 553 display-hub@15200000 { 554 compatible = "nvidia,tegra194-display", "simple-bus"; 555 reg = <0x15200000 0x00040000>; 556 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 557 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 558 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 559 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 560 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 561 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 562 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 563 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 564 "wgrp3", "wgrp4", "wgrp5"; 565 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 566 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 567 clock-names = "disp", "hub"; 568 status = "disabled"; 569 570 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 571 572 #address-cells = <1>; 573 #size-cells = <1>; 574 575 ranges = <0x15200000 0x15200000 0x40000>; 576 577 display@15200000 { 578 compatible = "nvidia,tegra194-dc"; 579 reg = <0x15200000 0x10000>; 580 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 582 clock-names = "dc"; 583 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 584 reset-names = "dc"; 585 586 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 587 588 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 589 nvidia,head = <0>; 590 }; 591 592 display@15210000 { 593 compatible = "nvidia,tegra194-dc"; 594 reg = <0x15210000 0x10000>; 595 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 597 clock-names = "dc"; 598 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 599 reset-names = "dc"; 600 601 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 602 603 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 604 nvidia,head = <1>; 605 }; 606 607 display@15220000 { 608 compatible = "nvidia,tegra194-dc"; 609 reg = <0x15220000 0x10000>; 610 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 612 clock-names = "dc"; 613 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 614 reset-names = "dc"; 615 616 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 617 618 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 619 nvidia,head = <2>; 620 }; 621 622 display@15230000 { 623 compatible = "nvidia,tegra194-dc"; 624 reg = <0x15230000 0x10000>; 625 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 627 clock-names = "dc"; 628 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 629 reset-names = "dc"; 630 631 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 632 633 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 634 nvidia,head = <3>; 635 }; 636 }; 637 638 vic@15340000 { 639 compatible = "nvidia,tegra194-vic"; 640 reg = <0x15340000 0x00040000>; 641 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&bpmp TEGRA194_CLK_VIC>; 643 clock-names = "vic"; 644 resets = <&bpmp TEGRA194_RESET_VIC>; 645 reset-names = "vic"; 646 647 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 648 }; 649 650 dpaux0: dpaux@155c0000 { 651 compatible = "nvidia,tegra194-dpaux"; 652 reg = <0x155c0000 0x10000>; 653 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 655 <&bpmp TEGRA194_CLK_PLLDP>; 656 clock-names = "dpaux", "parent"; 657 resets = <&bpmp TEGRA194_RESET_DPAUX>; 658 reset-names = "dpaux"; 659 status = "disabled"; 660 661 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 662 663 state_dpaux0_aux: pinmux-aux { 664 groups = "dpaux-io"; 665 function = "aux"; 666 }; 667 668 state_dpaux0_i2c: pinmux-i2c { 669 groups = "dpaux-io"; 670 function = "i2c"; 671 }; 672 673 state_dpaux0_off: pinmux-off { 674 groups = "dpaux-io"; 675 function = "off"; 676 }; 677 678 i2c-bus { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 }; 682 }; 683 684 dpaux1: dpaux@155d0000 { 685 compatible = "nvidia,tegra194-dpaux"; 686 reg = <0x155d0000 0x10000>; 687 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 689 <&bpmp TEGRA194_CLK_PLLDP>; 690 clock-names = "dpaux", "parent"; 691 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 692 reset-names = "dpaux"; 693 status = "disabled"; 694 695 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 696 697 state_dpaux1_aux: pinmux-aux { 698 groups = "dpaux-io"; 699 function = "aux"; 700 }; 701 702 state_dpaux1_i2c: pinmux-i2c { 703 groups = "dpaux-io"; 704 function = "i2c"; 705 }; 706 707 state_dpaux1_off: pinmux-off { 708 groups = "dpaux-io"; 709 function = "off"; 710 }; 711 712 i2c-bus { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 }; 716 }; 717 718 dpaux2: dpaux@155e0000 { 719 compatible = "nvidia,tegra194-dpaux"; 720 reg = <0x155e0000 0x10000>; 721 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 723 <&bpmp TEGRA194_CLK_PLLDP>; 724 clock-names = "dpaux", "parent"; 725 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 726 reset-names = "dpaux"; 727 status = "disabled"; 728 729 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 730 731 state_dpaux2_aux: pinmux-aux { 732 groups = "dpaux-io"; 733 function = "aux"; 734 }; 735 736 state_dpaux2_i2c: pinmux-i2c { 737 groups = "dpaux-io"; 738 function = "i2c"; 739 }; 740 741 state_dpaux2_off: pinmux-off { 742 groups = "dpaux-io"; 743 function = "off"; 744 }; 745 746 i2c-bus { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 }; 750 }; 751 752 dpaux3: dpaux@155f0000 { 753 compatible = "nvidia,tegra194-dpaux"; 754 reg = <0x155f0000 0x10000>; 755 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 757 <&bpmp TEGRA194_CLK_PLLDP>; 758 clock-names = "dpaux", "parent"; 759 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 760 reset-names = "dpaux"; 761 status = "disabled"; 762 763 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 764 765 state_dpaux3_aux: pinmux-aux { 766 groups = "dpaux-io"; 767 function = "aux"; 768 }; 769 770 state_dpaux3_i2c: pinmux-i2c { 771 groups = "dpaux-io"; 772 function = "i2c"; 773 }; 774 775 state_dpaux3_off: pinmux-off { 776 groups = "dpaux-io"; 777 function = "off"; 778 }; 779 780 i2c-bus { 781 #address-cells = <1>; 782 #size-cells = <0>; 783 }; 784 }; 785 786 sor0: sor@15b00000 { 787 compatible = "nvidia,tegra194-sor"; 788 reg = <0x15b00000 0x40000>; 789 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 791 <&bpmp TEGRA194_CLK_SOR0_OUT>, 792 <&bpmp TEGRA194_CLK_PLLD>, 793 <&bpmp TEGRA194_CLK_PLLDP>, 794 <&bpmp TEGRA194_CLK_SOR_SAFE>, 795 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 796 clock-names = "sor", "out", "parent", "dp", "safe", 797 "pad"; 798 resets = <&bpmp TEGRA194_RESET_SOR0>; 799 reset-names = "sor"; 800 pinctrl-0 = <&state_dpaux0_aux>; 801 pinctrl-1 = <&state_dpaux0_i2c>; 802 pinctrl-2 = <&state_dpaux0_off>; 803 pinctrl-names = "aux", "i2c", "off"; 804 status = "disabled"; 805 806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 807 nvidia,interface = <0>; 808 }; 809 810 sor1: sor@15b40000 { 811 compatible = "nvidia,tegra194-sor"; 812 reg = <0x155c0000 0x40000>; 813 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 815 <&bpmp TEGRA194_CLK_SOR1_OUT>, 816 <&bpmp TEGRA194_CLK_PLLD2>, 817 <&bpmp TEGRA194_CLK_PLLDP>, 818 <&bpmp TEGRA194_CLK_SOR_SAFE>, 819 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 820 clock-names = "sor", "out", "parent", "dp", "safe", 821 "pad"; 822 resets = <&bpmp TEGRA194_RESET_SOR1>; 823 reset-names = "sor"; 824 pinctrl-0 = <&state_dpaux1_aux>; 825 pinctrl-1 = <&state_dpaux1_i2c>; 826 pinctrl-2 = <&state_dpaux1_off>; 827 pinctrl-names = "aux", "i2c", "off"; 828 status = "disabled"; 829 830 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 831 nvidia,interface = <1>; 832 }; 833 834 sor2: sor@15b80000 { 835 compatible = "nvidia,tegra194-sor"; 836 reg = <0x15b80000 0x40000>; 837 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 839 <&bpmp TEGRA194_CLK_SOR2_OUT>, 840 <&bpmp TEGRA194_CLK_PLLD3>, 841 <&bpmp TEGRA194_CLK_PLLDP>, 842 <&bpmp TEGRA194_CLK_SOR_SAFE>, 843 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 844 clock-names = "sor", "out", "parent", "dp", "safe", 845 "pad"; 846 resets = <&bpmp TEGRA194_RESET_SOR2>; 847 reset-names = "sor"; 848 pinctrl-0 = <&state_dpaux2_aux>; 849 pinctrl-1 = <&state_dpaux2_i2c>; 850 pinctrl-2 = <&state_dpaux2_off>; 851 pinctrl-names = "aux", "i2c", "off"; 852 status = "disabled"; 853 854 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 855 nvidia,interface = <2>; 856 }; 857 858 sor3: sor@15bc0000 { 859 compatible = "nvidia,tegra194-sor"; 860 reg = <0x15bc0000 0x40000>; 861 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 863 <&bpmp TEGRA194_CLK_SOR3_OUT>, 864 <&bpmp TEGRA194_CLK_PLLD4>, 865 <&bpmp TEGRA194_CLK_PLLDP>, 866 <&bpmp TEGRA194_CLK_SOR_SAFE>, 867 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 868 clock-names = "sor", "out", "parent", "dp", "safe", 869 "pad"; 870 resets = <&bpmp TEGRA194_RESET_SOR3>; 871 reset-names = "sor"; 872 pinctrl-0 = <&state_dpaux3_aux>; 873 pinctrl-1 = <&state_dpaux3_i2c>; 874 pinctrl-2 = <&state_dpaux3_off>; 875 pinctrl-names = "aux", "i2c", "off"; 876 status = "disabled"; 877 878 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 879 nvidia,interface = <3>; 880 }; 881 }; 882 }; 883 884 sysram@40000000 { 885 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 886 reg = <0x0 0x40000000 0x0 0x50000>; 887 #address-cells = <1>; 888 #size-cells = <1>; 889 ranges = <0x0 0x0 0x40000000 0x50000>; 890 891 cpu_bpmp_tx: shmem@4e000 { 892 compatible = "nvidia,tegra194-bpmp-shmem"; 893 reg = <0x4e000 0x1000>; 894 label = "cpu-bpmp-tx"; 895 pool; 896 }; 897 898 cpu_bpmp_rx: shmem@4f000 { 899 compatible = "nvidia,tegra194-bpmp-shmem"; 900 reg = <0x4f000 0x1000>; 901 label = "cpu-bpmp-rx"; 902 pool; 903 }; 904 }; 905 906 bpmp: bpmp { 907 compatible = "nvidia,tegra186-bpmp"; 908 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 909 TEGRA_HSP_DB_MASTER_BPMP>; 910 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 911 #clock-cells = <1>; 912 #reset-cells = <1>; 913 #power-domain-cells = <1>; 914 915 bpmp_i2c: i2c { 916 compatible = "nvidia,tegra186-bpmp-i2c"; 917 nvidia,bpmp-bus-id = <5>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 }; 921 922 bpmp_thermal: thermal { 923 compatible = "nvidia,tegra186-bpmp-thermal"; 924 #thermal-sensor-cells = <1>; 925 }; 926 }; 927 928 cpus { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 cpu@0 { 933 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 934 device_type = "cpu"; 935 reg = <0x10000>; 936 enable-method = "psci"; 937 }; 938 939 cpu@1 { 940 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 941 device_type = "cpu"; 942 reg = <0x10001>; 943 enable-method = "psci"; 944 }; 945 946 cpu@2 { 947 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 948 device_type = "cpu"; 949 reg = <0x100>; 950 enable-method = "psci"; 951 }; 952 953 cpu@3 { 954 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 955 device_type = "cpu"; 956 reg = <0x101>; 957 enable-method = "psci"; 958 }; 959 960 cpu@4 { 961 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 962 device_type = "cpu"; 963 reg = <0x200>; 964 enable-method = "psci"; 965 }; 966 967 cpu@5 { 968 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 969 device_type = "cpu"; 970 reg = <0x201>; 971 enable-method = "psci"; 972 }; 973 974 cpu@6 { 975 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 976 device_type = "cpu"; 977 reg = <0x10300>; 978 enable-method = "psci"; 979 }; 980 981 cpu@7 { 982 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 983 device_type = "cpu"; 984 reg = <0x10301>; 985 enable-method = "psci"; 986 }; 987 }; 988 989 psci { 990 compatible = "arm,psci-1.0"; 991 status = "okay"; 992 method = "smc"; 993 }; 994 995 tcu: tcu { 996 compatible = "nvidia,tegra194-tcu"; 997 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 998 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 999 mbox-names = "rx", "tx"; 1000 }; 1001 1002 thermal-zones { 1003 cpu { 1004 thermal-sensors = <&{/bpmp/thermal} 1005 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1006 status = "disabled"; 1007 }; 1008 1009 gpu { 1010 thermal-sensors = <&{/bpmp/thermal} 1011 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1012 status = "disabled"; 1013 }; 1014 1015 aux { 1016 thermal-sensors = <&{/bpmp/thermal} 1017 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1018 status = "disabled"; 1019 }; 1020 1021 pllx { 1022 thermal-sensors = <&{/bpmp/thermal} 1023 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1024 status = "disabled"; 1025 }; 1026 1027 ao { 1028 thermal-sensors = <&{/bpmp/thermal} 1029 TEGRA194_BPMP_THERMAL_ZONE_AO>; 1030 status = "disabled"; 1031 }; 1032 1033 tj { 1034 thermal-sensors = <&{/bpmp/thermal} 1035 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1036 status = "disabled"; 1037 }; 1038 }; 1039 1040 timer { 1041 compatible = "arm,armv8-timer"; 1042 interrupts = <GIC_PPI 13 1043 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1044 <GIC_PPI 14 1045 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1046 <GIC_PPI 11 1047 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1048 <GIC_PPI 10 1049 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1050 interrupt-parent = <&gic>; 1051 }; 1052}; 1053