1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@3881000 { 332 compatible = "arm,gic-400"; 333 #interrupt-cells = <3>; 334 interrupt-controller; 335 reg = <0x03881000 0x1000>, 336 <0x03882000 0x2000>, 337 <0x03884000 0x2000>, 338 <0x03886000 0x2000>; 339 interrupts = <GIC_PPI 9 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 341 interrupt-parent = <&gic>; 342 }; 343 344 hsp_top0: hsp@3c00000 { 345 compatible = "nvidia,tegra186-hsp"; 346 reg = <0x03c00000 0xa0000>; 347 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "doorbell"; 349 #mbox-cells = <2>; 350 }; 351 352 gen2_i2c: i2c@c240000 { 353 compatible = "nvidia,tegra194-i2c"; 354 reg = <0x0c240000 0x10000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&bpmp TEGRA194_CLK_I2C2>; 359 clock-names = "div-clk"; 360 resets = <&bpmp TEGRA194_RESET_I2C2>; 361 reset-names = "i2c"; 362 status = "disabled"; 363 }; 364 365 gen8_i2c: i2c@c250000 { 366 compatible = "nvidia,tegra194-i2c"; 367 reg = <0x0c250000 0x10000>; 368 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&bpmp TEGRA194_CLK_I2C8>; 372 clock-names = "div-clk"; 373 resets = <&bpmp TEGRA194_RESET_I2C8>; 374 reset-names = "i2c"; 375 status = "disabled"; 376 }; 377 378 uartc: serial@c280000 { 379 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 380 reg = <0x0c280000 0x40>; 381 reg-shift = <2>; 382 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&bpmp TEGRA194_CLK_UARTC>; 384 clock-names = "serial"; 385 resets = <&bpmp TEGRA194_RESET_UARTC>; 386 reset-names = "serial"; 387 status = "disabled"; 388 }; 389 390 uartg: serial@c290000 { 391 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 392 reg = <0x0c290000 0x40>; 393 reg-shift = <2>; 394 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA194_CLK_UARTG>; 396 clock-names = "serial"; 397 resets = <&bpmp TEGRA194_RESET_UARTG>; 398 reset-names = "serial"; 399 status = "disabled"; 400 }; 401 402 pwm4: pwm@c340000 { 403 compatible = "nvidia,tegra194-pwm", 404 "nvidia,tegra186-pwm"; 405 reg = <0xc340000 0x10000>; 406 clocks = <&bpmp TEGRA194_CLK_PWM4>; 407 clock-names = "pwm"; 408 resets = <&bpmp TEGRA194_RESET_PWM4>; 409 reset-names = "pwm"; 410 status = "disabled"; 411 #pwm-cells = <2>; 412 }; 413 414 pmc@c360000 { 415 compatible = "nvidia,tegra194-pmc"; 416 reg = <0x0c360000 0x10000>, 417 <0x0c370000 0x10000>, 418 <0x0c380000 0x10000>, 419 <0x0c390000 0x10000>, 420 <0x0c3a0000 0x10000>; 421 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 422 }; 423 424 host1x@13e00000 { 425 compatible = "nvidia,tegra194-host1x", "simple-bus"; 426 reg = <0x13e00000 0x10000>, 427 <0x13e10000 0x10000>; 428 reg-names = "hypervisor", "vm"; 429 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 432 clock-names = "host1x"; 433 resets = <&bpmp TEGRA194_RESET_HOST1X>; 434 reset-names = "host1x"; 435 436 #address-cells = <1>; 437 #size-cells = <1>; 438 439 ranges = <0x15000000 0x15000000 0x01000000>; 440 441 display-hub@15200000 { 442 compatible = "nvidia,tegra194-display", "simple-bus"; 443 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 444 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 445 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 446 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 447 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 448 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 449 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 450 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 451 "wgrp3", "wgrp4", "wgrp5"; 452 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 453 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 454 clock-names = "disp", "hub"; 455 status = "disabled"; 456 457 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 458 459 #address-cells = <1>; 460 #size-cells = <1>; 461 462 ranges = <0x15200000 0x15200000 0x40000>; 463 464 display@15200000 { 465 compatible = "nvidia,tegra194-dc"; 466 reg = <0x15200000 0x10000>; 467 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 469 clock-names = "dc"; 470 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 471 reset-names = "dc"; 472 473 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 474 475 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 476 nvidia,head = <0>; 477 }; 478 479 display@15210000 { 480 compatible = "nvidia,tegra194-dc"; 481 reg = <0x15210000 0x10000>; 482 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 484 clock-names = "dc"; 485 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 486 reset-names = "dc"; 487 488 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 489 490 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 491 nvidia,head = <1>; 492 }; 493 494 display@15220000 { 495 compatible = "nvidia,tegra194-dc"; 496 reg = <0x15220000 0x10000>; 497 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 499 clock-names = "dc"; 500 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 501 reset-names = "dc"; 502 503 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 504 505 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 506 nvidia,head = <2>; 507 }; 508 509 display@15230000 { 510 compatible = "nvidia,tegra194-dc"; 511 reg = <0x15230000 0x10000>; 512 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 514 clock-names = "dc"; 515 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 516 reset-names = "dc"; 517 518 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 519 520 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 521 nvidia,head = <3>; 522 }; 523 }; 524 525 vic@15340000 { 526 compatible = "nvidia,tegra194-vic"; 527 reg = <0x15340000 0x00040000>; 528 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&bpmp TEGRA194_CLK_VIC>; 530 clock-names = "vic"; 531 resets = <&bpmp TEGRA194_RESET_VIC>; 532 reset-names = "vic"; 533 534 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 535 }; 536 537 dpaux0: dpaux@155c0000 { 538 compatible = "nvidia,tegra194-dpaux"; 539 reg = <0x155c0000 0x10000>; 540 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 542 <&bpmp TEGRA194_CLK_PLLDP>; 543 clock-names = "dpaux", "parent"; 544 resets = <&bpmp TEGRA194_RESET_DPAUX>; 545 reset-names = "dpaux"; 546 status = "disabled"; 547 548 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 549 550 state_dpaux0_aux: pinmux-aux { 551 groups = "dpaux-io"; 552 function = "aux"; 553 }; 554 555 state_dpaux0_i2c: pinmux-i2c { 556 groups = "dpaux-io"; 557 function = "i2c"; 558 }; 559 560 state_dpaux0_off: pinmux-off { 561 groups = "dpaux-io"; 562 function = "off"; 563 }; 564 565 i2c-bus { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 }; 569 }; 570 571 dpaux1: dpaux@155d0000 { 572 compatible = "nvidia,tegra194-dpaux"; 573 reg = <0x155d0000 0x10000>; 574 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 576 <&bpmp TEGRA194_CLK_PLLDP>; 577 clock-names = "dpaux", "parent"; 578 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 579 reset-names = "dpaux"; 580 status = "disabled"; 581 582 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 583 584 state_dpaux1_aux: pinmux-aux { 585 groups = "dpaux-io"; 586 function = "aux"; 587 }; 588 589 state_dpaux1_i2c: pinmux-i2c { 590 groups = "dpaux-io"; 591 function = "i2c"; 592 }; 593 594 state_dpaux1_off: pinmux-off { 595 groups = "dpaux-io"; 596 function = "off"; 597 }; 598 599 i2c-bus { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 }; 603 }; 604 605 dpaux2: dpaux@155e0000 { 606 compatible = "nvidia,tegra194-dpaux"; 607 reg = <0x155e0000 0x10000>; 608 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 610 <&bpmp TEGRA194_CLK_PLLDP>; 611 clock-names = "dpaux", "parent"; 612 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 613 reset-names = "dpaux"; 614 status = "disabled"; 615 616 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 617 618 state_dpaux2_aux: pinmux-aux { 619 groups = "dpaux-io"; 620 function = "aux"; 621 }; 622 623 state_dpaux2_i2c: pinmux-i2c { 624 groups = "dpaux-io"; 625 function = "i2c"; 626 }; 627 628 state_dpaux2_off: pinmux-off { 629 groups = "dpaux-io"; 630 function = "off"; 631 }; 632 633 i2c-bus { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 }; 637 }; 638 639 dpaux3: dpaux@155f0000 { 640 compatible = "nvidia,tegra194-dpaux"; 641 reg = <0x155f0000 0x10000>; 642 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 644 <&bpmp TEGRA194_CLK_PLLDP>; 645 clock-names = "dpaux", "parent"; 646 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 647 reset-names = "dpaux"; 648 status = "disabled"; 649 650 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 651 652 state_dpaux3_aux: pinmux-aux { 653 groups = "dpaux-io"; 654 function = "aux"; 655 }; 656 657 state_dpaux3_i2c: pinmux-i2c { 658 groups = "dpaux-io"; 659 function = "i2c"; 660 }; 661 662 state_dpaux3_off: pinmux-off { 663 groups = "dpaux-io"; 664 function = "off"; 665 }; 666 667 i2c-bus { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 }; 671 }; 672 673 sor0: sor@15b00000 { 674 compatible = "nvidia,tegra194-sor"; 675 reg = <0x15b00000 0x40000>; 676 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 678 <&bpmp TEGRA194_CLK_SOR0_OUT>, 679 <&bpmp TEGRA194_CLK_PLLD>, 680 <&bpmp TEGRA194_CLK_PLLDP>, 681 <&bpmp TEGRA194_CLK_SOR_SAFE>, 682 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 683 clock-names = "sor", "out", "parent", "dp", "safe", 684 "pad"; 685 resets = <&bpmp TEGRA194_RESET_SOR0>; 686 reset-names = "sor"; 687 pinctrl-0 = <&state_dpaux0_aux>; 688 pinctrl-1 = <&state_dpaux0_i2c>; 689 pinctrl-2 = <&state_dpaux0_off>; 690 pinctrl-names = "aux", "i2c", "off"; 691 status = "disabled"; 692 693 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 694 nvidia,interface = <0>; 695 }; 696 697 sor1: sor@15b40000 { 698 compatible = "nvidia,tegra194-sor"; 699 reg = <0x155c0000 0x40000>; 700 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 702 <&bpmp TEGRA194_CLK_SOR1_OUT>, 703 <&bpmp TEGRA194_CLK_PLLD2>, 704 <&bpmp TEGRA194_CLK_PLLDP>, 705 <&bpmp TEGRA194_CLK_SOR_SAFE>, 706 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 707 clock-names = "sor", "out", "parent", "dp", "safe", 708 "pad"; 709 resets = <&bpmp TEGRA194_RESET_SOR1>; 710 reset-names = "sor"; 711 pinctrl-0 = <&state_dpaux1_aux>; 712 pinctrl-1 = <&state_dpaux1_i2c>; 713 pinctrl-2 = <&state_dpaux1_off>; 714 pinctrl-names = "aux", "i2c", "off"; 715 status = "disabled"; 716 717 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 718 nvidia,interface = <1>; 719 }; 720 721 sor2: sor@15b80000 { 722 compatible = "nvidia,tegra194-sor"; 723 reg = <0x15b80000 0x40000>; 724 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 726 <&bpmp TEGRA194_CLK_SOR2_OUT>, 727 <&bpmp TEGRA194_CLK_PLLD3>, 728 <&bpmp TEGRA194_CLK_PLLDP>, 729 <&bpmp TEGRA194_CLK_SOR_SAFE>, 730 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 731 clock-names = "sor", "out", "parent", "dp", "safe", 732 "pad"; 733 resets = <&bpmp TEGRA194_RESET_SOR2>; 734 reset-names = "sor"; 735 pinctrl-0 = <&state_dpaux2_aux>; 736 pinctrl-1 = <&state_dpaux2_i2c>; 737 pinctrl-2 = <&state_dpaux2_off>; 738 pinctrl-names = "aux", "i2c", "off"; 739 status = "disabled"; 740 741 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 742 nvidia,interface = <2>; 743 }; 744 745 sor3: sor@15bc0000 { 746 compatible = "nvidia,tegra194-sor"; 747 reg = <0x15bc0000 0x40000>; 748 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 750 <&bpmp TEGRA194_CLK_SOR3_OUT>, 751 <&bpmp TEGRA194_CLK_PLLD4>, 752 <&bpmp TEGRA194_CLK_PLLDP>, 753 <&bpmp TEGRA194_CLK_SOR_SAFE>, 754 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 755 clock-names = "sor", "out", "parent", "dp", "safe", 756 "pad"; 757 resets = <&bpmp TEGRA194_RESET_SOR3>; 758 reset-names = "sor"; 759 pinctrl-0 = <&state_dpaux3_aux>; 760 pinctrl-1 = <&state_dpaux3_i2c>; 761 pinctrl-2 = <&state_dpaux3_off>; 762 pinctrl-names = "aux", "i2c", "off"; 763 status = "disabled"; 764 765 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 766 nvidia,interface = <3>; 767 }; 768 }; 769 }; 770 771 sysram@40000000 { 772 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 773 reg = <0x0 0x40000000 0x0 0x50000>; 774 #address-cells = <1>; 775 #size-cells = <1>; 776 ranges = <0x0 0x0 0x40000000 0x50000>; 777 778 cpu_bpmp_tx: shmem@4e000 { 779 compatible = "nvidia,tegra194-bpmp-shmem"; 780 reg = <0x4e000 0x1000>; 781 label = "cpu-bpmp-tx"; 782 pool; 783 }; 784 785 cpu_bpmp_rx: shmem@4f000 { 786 compatible = "nvidia,tegra194-bpmp-shmem"; 787 reg = <0x4f000 0x1000>; 788 label = "cpu-bpmp-rx"; 789 pool; 790 }; 791 }; 792 793 bpmp: bpmp { 794 compatible = "nvidia,tegra186-bpmp"; 795 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 796 TEGRA_HSP_DB_MASTER_BPMP>; 797 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 798 #clock-cells = <1>; 799 #reset-cells = <1>; 800 #power-domain-cells = <1>; 801 802 bpmp_i2c: i2c { 803 compatible = "nvidia,tegra186-bpmp-i2c"; 804 nvidia,bpmp-bus-id = <5>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 }; 808 809 bpmp_thermal: thermal { 810 compatible = "nvidia,tegra186-bpmp-thermal"; 811 #thermal-sensor-cells = <1>; 812 }; 813 }; 814 815 cpus { 816 #address-cells = <1>; 817 #size-cells = <0>; 818 819 cpu@0 { 820 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 821 device_type = "cpu"; 822 reg = <0x10000>; 823 enable-method = "psci"; 824 }; 825 826 cpu@1 { 827 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 828 device_type = "cpu"; 829 reg = <0x10001>; 830 enable-method = "psci"; 831 }; 832 833 cpu@2 { 834 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 835 device_type = "cpu"; 836 reg = <0x100>; 837 enable-method = "psci"; 838 }; 839 840 cpu@3 { 841 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 842 device_type = "cpu"; 843 reg = <0x101>; 844 enable-method = "psci"; 845 }; 846 847 cpu@4 { 848 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 849 device_type = "cpu"; 850 reg = <0x200>; 851 enable-method = "psci"; 852 }; 853 854 cpu@5 { 855 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 856 device_type = "cpu"; 857 reg = <0x201>; 858 enable-method = "psci"; 859 }; 860 861 cpu@6 { 862 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 863 device_type = "cpu"; 864 reg = <0x10300>; 865 enable-method = "psci"; 866 }; 867 868 cpu@7 { 869 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 870 device_type = "cpu"; 871 reg = <0x10301>; 872 enable-method = "psci"; 873 }; 874 }; 875 876 psci { 877 compatible = "arm,psci-1.0"; 878 status = "okay"; 879 method = "smc"; 880 }; 881 882 thermal-zones { 883 cpu { 884 thermal-sensors = <&{/bpmp/thermal} 885 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 886 status = "disabled"; 887 }; 888 889 gpu { 890 thermal-sensors = <&{/bpmp/thermal} 891 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 892 status = "disabled"; 893 }; 894 895 aux { 896 thermal-sensors = <&{/bpmp/thermal} 897 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 898 status = "disabled"; 899 }; 900 901 pllx { 902 thermal-sensors = <&{/bpmp/thermal} 903 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 904 status = "disabled"; 905 }; 906 907 ao { 908 thermal-sensors = <&{/bpmp/thermal} 909 TEGRA194_BPMP_THERMAL_ZONE_AO>; 910 status = "disabled"; 911 }; 912 913 tj { 914 thermal-sensors = <&{/bpmp/thermal} 915 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 916 status = "disabled"; 917 }; 918 }; 919 920 timer { 921 compatible = "arm,armv8-timer"; 922 interrupts = <GIC_PPI 13 923 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 924 <GIC_PPI 14 925 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 926 <GIC_PPI 11 927 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 928 <GIC_PPI 10 929 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 930 interrupt-parent = <&gic>; 931 }; 932}; 933