1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@3881000 { 332 compatible = "arm,gic-400"; 333 #interrupt-cells = <3>; 334 interrupt-controller; 335 reg = <0x03881000 0x1000>, 336 <0x03882000 0x2000>, 337 <0x03884000 0x2000>, 338 <0x03886000 0x2000>; 339 interrupts = <GIC_PPI 9 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 341 interrupt-parent = <&gic>; 342 }; 343 344 hsp_top0: hsp@3c00000 { 345 compatible = "nvidia,tegra186-hsp"; 346 reg = <0x03c00000 0xa0000>; 347 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "doorbell"; 349 #mbox-cells = <2>; 350 }; 351 352 gen2_i2c: i2c@c240000 { 353 compatible = "nvidia,tegra194-i2c"; 354 reg = <0x0c240000 0x10000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&bpmp TEGRA194_CLK_I2C2>; 359 clock-names = "div-clk"; 360 resets = <&bpmp TEGRA194_RESET_I2C2>; 361 reset-names = "i2c"; 362 status = "disabled"; 363 }; 364 365 gen8_i2c: i2c@c250000 { 366 compatible = "nvidia,tegra194-i2c"; 367 reg = <0x0c250000 0x10000>; 368 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&bpmp TEGRA194_CLK_I2C8>; 372 clock-names = "div-clk"; 373 resets = <&bpmp TEGRA194_RESET_I2C8>; 374 reset-names = "i2c"; 375 status = "disabled"; 376 }; 377 378 uartc: serial@c280000 { 379 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 380 reg = <0x0c280000 0x40>; 381 reg-shift = <2>; 382 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&bpmp TEGRA194_CLK_UARTC>; 384 clock-names = "serial"; 385 resets = <&bpmp TEGRA194_RESET_UARTC>; 386 reset-names = "serial"; 387 status = "disabled"; 388 }; 389 390 uartg: serial@c290000 { 391 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 392 reg = <0x0c290000 0x40>; 393 reg-shift = <2>; 394 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA194_CLK_UARTG>; 396 clock-names = "serial"; 397 resets = <&bpmp TEGRA194_RESET_UARTG>; 398 reset-names = "serial"; 399 status = "disabled"; 400 }; 401 402 rtc: rtc@c2a0000 { 403 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 404 reg = <0x0c2a0000 0x10000>; 405 interrupt-parent = <&pmc>; 406 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 408 clock-names = "rtc"; 409 status = "disabled"; 410 }; 411 412 pwm4: pwm@c340000 { 413 compatible = "nvidia,tegra194-pwm", 414 "nvidia,tegra186-pwm"; 415 reg = <0xc340000 0x10000>; 416 clocks = <&bpmp TEGRA194_CLK_PWM4>; 417 clock-names = "pwm"; 418 resets = <&bpmp TEGRA194_RESET_PWM4>; 419 reset-names = "pwm"; 420 status = "disabled"; 421 #pwm-cells = <2>; 422 }; 423 424 pmc: pmc@c360000 { 425 compatible = "nvidia,tegra194-pmc"; 426 reg = <0x0c360000 0x10000>, 427 <0x0c370000 0x10000>, 428 <0x0c380000 0x10000>, 429 <0x0c390000 0x10000>, 430 <0x0c3a0000 0x10000>; 431 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 432 433 #interrupt-cells = <2>; 434 interrupt-controller; 435 }; 436 437 host1x@13e00000 { 438 compatible = "nvidia,tegra194-host1x", "simple-bus"; 439 reg = <0x13e00000 0x10000>, 440 <0x13e10000 0x10000>; 441 reg-names = "hypervisor", "vm"; 442 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 445 clock-names = "host1x"; 446 resets = <&bpmp TEGRA194_RESET_HOST1X>; 447 reset-names = "host1x"; 448 449 #address-cells = <1>; 450 #size-cells = <1>; 451 452 ranges = <0x15000000 0x15000000 0x01000000>; 453 454 display-hub@15200000 { 455 compatible = "nvidia,tegra194-display", "simple-bus"; 456 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 457 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 458 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 459 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 460 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 461 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 462 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 463 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 464 "wgrp3", "wgrp4", "wgrp5"; 465 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 466 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 467 clock-names = "disp", "hub"; 468 status = "disabled"; 469 470 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 471 472 #address-cells = <1>; 473 #size-cells = <1>; 474 475 ranges = <0x15200000 0x15200000 0x40000>; 476 477 display@15200000 { 478 compatible = "nvidia,tegra194-dc"; 479 reg = <0x15200000 0x10000>; 480 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 482 clock-names = "dc"; 483 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 484 reset-names = "dc"; 485 486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 487 488 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 489 nvidia,head = <0>; 490 }; 491 492 display@15210000 { 493 compatible = "nvidia,tegra194-dc"; 494 reg = <0x15210000 0x10000>; 495 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 497 clock-names = "dc"; 498 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 499 reset-names = "dc"; 500 501 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 502 503 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 504 nvidia,head = <1>; 505 }; 506 507 display@15220000 { 508 compatible = "nvidia,tegra194-dc"; 509 reg = <0x15220000 0x10000>; 510 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 512 clock-names = "dc"; 513 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 514 reset-names = "dc"; 515 516 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 517 518 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 519 nvidia,head = <2>; 520 }; 521 522 display@15230000 { 523 compatible = "nvidia,tegra194-dc"; 524 reg = <0x15230000 0x10000>; 525 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 527 clock-names = "dc"; 528 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 529 reset-names = "dc"; 530 531 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 532 533 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 534 nvidia,head = <3>; 535 }; 536 }; 537 538 vic@15340000 { 539 compatible = "nvidia,tegra194-vic"; 540 reg = <0x15340000 0x00040000>; 541 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&bpmp TEGRA194_CLK_VIC>; 543 clock-names = "vic"; 544 resets = <&bpmp TEGRA194_RESET_VIC>; 545 reset-names = "vic"; 546 547 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 548 }; 549 550 dpaux0: dpaux@155c0000 { 551 compatible = "nvidia,tegra194-dpaux"; 552 reg = <0x155c0000 0x10000>; 553 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 555 <&bpmp TEGRA194_CLK_PLLDP>; 556 clock-names = "dpaux", "parent"; 557 resets = <&bpmp TEGRA194_RESET_DPAUX>; 558 reset-names = "dpaux"; 559 status = "disabled"; 560 561 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 562 563 state_dpaux0_aux: pinmux-aux { 564 groups = "dpaux-io"; 565 function = "aux"; 566 }; 567 568 state_dpaux0_i2c: pinmux-i2c { 569 groups = "dpaux-io"; 570 function = "i2c"; 571 }; 572 573 state_dpaux0_off: pinmux-off { 574 groups = "dpaux-io"; 575 function = "off"; 576 }; 577 578 i2c-bus { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 }; 582 }; 583 584 dpaux1: dpaux@155d0000 { 585 compatible = "nvidia,tegra194-dpaux"; 586 reg = <0x155d0000 0x10000>; 587 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 589 <&bpmp TEGRA194_CLK_PLLDP>; 590 clock-names = "dpaux", "parent"; 591 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 592 reset-names = "dpaux"; 593 status = "disabled"; 594 595 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 596 597 state_dpaux1_aux: pinmux-aux { 598 groups = "dpaux-io"; 599 function = "aux"; 600 }; 601 602 state_dpaux1_i2c: pinmux-i2c { 603 groups = "dpaux-io"; 604 function = "i2c"; 605 }; 606 607 state_dpaux1_off: pinmux-off { 608 groups = "dpaux-io"; 609 function = "off"; 610 }; 611 612 i2c-bus { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 }; 616 }; 617 618 dpaux2: dpaux@155e0000 { 619 compatible = "nvidia,tegra194-dpaux"; 620 reg = <0x155e0000 0x10000>; 621 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 623 <&bpmp TEGRA194_CLK_PLLDP>; 624 clock-names = "dpaux", "parent"; 625 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 626 reset-names = "dpaux"; 627 status = "disabled"; 628 629 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 630 631 state_dpaux2_aux: pinmux-aux { 632 groups = "dpaux-io"; 633 function = "aux"; 634 }; 635 636 state_dpaux2_i2c: pinmux-i2c { 637 groups = "dpaux-io"; 638 function = "i2c"; 639 }; 640 641 state_dpaux2_off: pinmux-off { 642 groups = "dpaux-io"; 643 function = "off"; 644 }; 645 646 i2c-bus { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 }; 650 }; 651 652 dpaux3: dpaux@155f0000 { 653 compatible = "nvidia,tegra194-dpaux"; 654 reg = <0x155f0000 0x10000>; 655 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 657 <&bpmp TEGRA194_CLK_PLLDP>; 658 clock-names = "dpaux", "parent"; 659 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 660 reset-names = "dpaux"; 661 status = "disabled"; 662 663 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 664 665 state_dpaux3_aux: pinmux-aux { 666 groups = "dpaux-io"; 667 function = "aux"; 668 }; 669 670 state_dpaux3_i2c: pinmux-i2c { 671 groups = "dpaux-io"; 672 function = "i2c"; 673 }; 674 675 state_dpaux3_off: pinmux-off { 676 groups = "dpaux-io"; 677 function = "off"; 678 }; 679 680 i2c-bus { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 }; 684 }; 685 686 sor0: sor@15b00000 { 687 compatible = "nvidia,tegra194-sor"; 688 reg = <0x15b00000 0x40000>; 689 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 691 <&bpmp TEGRA194_CLK_SOR0_OUT>, 692 <&bpmp TEGRA194_CLK_PLLD>, 693 <&bpmp TEGRA194_CLK_PLLDP>, 694 <&bpmp TEGRA194_CLK_SOR_SAFE>, 695 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 696 clock-names = "sor", "out", "parent", "dp", "safe", 697 "pad"; 698 resets = <&bpmp TEGRA194_RESET_SOR0>; 699 reset-names = "sor"; 700 pinctrl-0 = <&state_dpaux0_aux>; 701 pinctrl-1 = <&state_dpaux0_i2c>; 702 pinctrl-2 = <&state_dpaux0_off>; 703 pinctrl-names = "aux", "i2c", "off"; 704 status = "disabled"; 705 706 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 707 nvidia,interface = <0>; 708 }; 709 710 sor1: sor@15b40000 { 711 compatible = "nvidia,tegra194-sor"; 712 reg = <0x155c0000 0x40000>; 713 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 715 <&bpmp TEGRA194_CLK_SOR1_OUT>, 716 <&bpmp TEGRA194_CLK_PLLD2>, 717 <&bpmp TEGRA194_CLK_PLLDP>, 718 <&bpmp TEGRA194_CLK_SOR_SAFE>, 719 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 720 clock-names = "sor", "out", "parent", "dp", "safe", 721 "pad"; 722 resets = <&bpmp TEGRA194_RESET_SOR1>; 723 reset-names = "sor"; 724 pinctrl-0 = <&state_dpaux1_aux>; 725 pinctrl-1 = <&state_dpaux1_i2c>; 726 pinctrl-2 = <&state_dpaux1_off>; 727 pinctrl-names = "aux", "i2c", "off"; 728 status = "disabled"; 729 730 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 731 nvidia,interface = <1>; 732 }; 733 734 sor2: sor@15b80000 { 735 compatible = "nvidia,tegra194-sor"; 736 reg = <0x15b80000 0x40000>; 737 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 739 <&bpmp TEGRA194_CLK_SOR2_OUT>, 740 <&bpmp TEGRA194_CLK_PLLD3>, 741 <&bpmp TEGRA194_CLK_PLLDP>, 742 <&bpmp TEGRA194_CLK_SOR_SAFE>, 743 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 744 clock-names = "sor", "out", "parent", "dp", "safe", 745 "pad"; 746 resets = <&bpmp TEGRA194_RESET_SOR2>; 747 reset-names = "sor"; 748 pinctrl-0 = <&state_dpaux2_aux>; 749 pinctrl-1 = <&state_dpaux2_i2c>; 750 pinctrl-2 = <&state_dpaux2_off>; 751 pinctrl-names = "aux", "i2c", "off"; 752 status = "disabled"; 753 754 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 755 nvidia,interface = <2>; 756 }; 757 758 sor3: sor@15bc0000 { 759 compatible = "nvidia,tegra194-sor"; 760 reg = <0x15bc0000 0x40000>; 761 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 763 <&bpmp TEGRA194_CLK_SOR3_OUT>, 764 <&bpmp TEGRA194_CLK_PLLD4>, 765 <&bpmp TEGRA194_CLK_PLLDP>, 766 <&bpmp TEGRA194_CLK_SOR_SAFE>, 767 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 768 clock-names = "sor", "out", "parent", "dp", "safe", 769 "pad"; 770 resets = <&bpmp TEGRA194_RESET_SOR3>; 771 reset-names = "sor"; 772 pinctrl-0 = <&state_dpaux3_aux>; 773 pinctrl-1 = <&state_dpaux3_i2c>; 774 pinctrl-2 = <&state_dpaux3_off>; 775 pinctrl-names = "aux", "i2c", "off"; 776 status = "disabled"; 777 778 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 779 nvidia,interface = <3>; 780 }; 781 }; 782 }; 783 784 sysram@40000000 { 785 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 786 reg = <0x0 0x40000000 0x0 0x50000>; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 ranges = <0x0 0x0 0x40000000 0x50000>; 790 791 cpu_bpmp_tx: shmem@4e000 { 792 compatible = "nvidia,tegra194-bpmp-shmem"; 793 reg = <0x4e000 0x1000>; 794 label = "cpu-bpmp-tx"; 795 pool; 796 }; 797 798 cpu_bpmp_rx: shmem@4f000 { 799 compatible = "nvidia,tegra194-bpmp-shmem"; 800 reg = <0x4f000 0x1000>; 801 label = "cpu-bpmp-rx"; 802 pool; 803 }; 804 }; 805 806 bpmp: bpmp { 807 compatible = "nvidia,tegra186-bpmp"; 808 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 809 TEGRA_HSP_DB_MASTER_BPMP>; 810 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 811 #clock-cells = <1>; 812 #reset-cells = <1>; 813 #power-domain-cells = <1>; 814 815 bpmp_i2c: i2c { 816 compatible = "nvidia,tegra186-bpmp-i2c"; 817 nvidia,bpmp-bus-id = <5>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 }; 821 822 bpmp_thermal: thermal { 823 compatible = "nvidia,tegra186-bpmp-thermal"; 824 #thermal-sensor-cells = <1>; 825 }; 826 }; 827 828 cpus { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 cpu@0 { 833 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 834 device_type = "cpu"; 835 reg = <0x10000>; 836 enable-method = "psci"; 837 }; 838 839 cpu@1 { 840 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 841 device_type = "cpu"; 842 reg = <0x10001>; 843 enable-method = "psci"; 844 }; 845 846 cpu@2 { 847 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 848 device_type = "cpu"; 849 reg = <0x100>; 850 enable-method = "psci"; 851 }; 852 853 cpu@3 { 854 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 855 device_type = "cpu"; 856 reg = <0x101>; 857 enable-method = "psci"; 858 }; 859 860 cpu@4 { 861 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 862 device_type = "cpu"; 863 reg = <0x200>; 864 enable-method = "psci"; 865 }; 866 867 cpu@5 { 868 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 869 device_type = "cpu"; 870 reg = <0x201>; 871 enable-method = "psci"; 872 }; 873 874 cpu@6 { 875 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 876 device_type = "cpu"; 877 reg = <0x10300>; 878 enable-method = "psci"; 879 }; 880 881 cpu@7 { 882 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 883 device_type = "cpu"; 884 reg = <0x10301>; 885 enable-method = "psci"; 886 }; 887 }; 888 889 psci { 890 compatible = "arm,psci-1.0"; 891 status = "okay"; 892 method = "smc"; 893 }; 894 895 thermal-zones { 896 cpu { 897 thermal-sensors = <&{/bpmp/thermal} 898 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 899 status = "disabled"; 900 }; 901 902 gpu { 903 thermal-sensors = <&{/bpmp/thermal} 904 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 905 status = "disabled"; 906 }; 907 908 aux { 909 thermal-sensors = <&{/bpmp/thermal} 910 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 911 status = "disabled"; 912 }; 913 914 pllx { 915 thermal-sensors = <&{/bpmp/thermal} 916 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 917 status = "disabled"; 918 }; 919 920 ao { 921 thermal-sensors = <&{/bpmp/thermal} 922 TEGRA194_BPMP_THERMAL_ZONE_AO>; 923 status = "disabled"; 924 }; 925 926 tj { 927 thermal-sensors = <&{/bpmp/thermal} 928 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 929 status = "disabled"; 930 }; 931 }; 932 933 timer { 934 compatible = "arm,armv8-timer"; 935 interrupts = <GIC_PPI 13 936 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 937 <GIC_PPI 14 938 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 939 <GIC_PPI 11 940 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 941 <GIC_PPI 10 942 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 943 interrupt-parent = <&gic>; 944 }; 945}; 946