1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8 9/ { 10 compatible = "nvidia,tegra194"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 /* control backbone */ 16 cbb { 17 compatible = "simple-bus"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges = <0x0 0x0 0x0 0x40000000>; 21 22 gpio: gpio@2200000 { 23 compatible = "nvidia,tegra194-gpio"; 24 reg-names = "security", "gpio"; 25 reg = <0x2200000 0x10000>, 26 <0x2210000 0x10000>; 27 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 33 #interrupt-cells = <2>; 34 interrupt-controller; 35 #gpio-cells = <2>; 36 gpio-controller; 37 }; 38 39 ethernet@2490000 { 40 compatible = "nvidia,tegra186-eqos", 41 "snps,dwc-qos-ethernet-4.10"; 42 reg = <0x02490000 0x10000>; 43 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 44 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 45 <&bpmp TEGRA194_CLK_EQOS_AXI>, 46 <&bpmp TEGRA194_CLK_EQOS_RX>, 47 <&bpmp TEGRA194_CLK_EQOS_TX>, 48 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 49 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 50 resets = <&bpmp TEGRA194_RESET_EQOS>; 51 reset-names = "eqos"; 52 status = "disabled"; 53 54 snps,write-requests = <1>; 55 snps,read-requests = <3>; 56 snps,burst-map = <0x7>; 57 snps,txpbl = <16>; 58 snps,rxpbl = <8>; 59 }; 60 61 uarta: serial@3100000 { 62 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 63 reg = <0x03100000 0x40>; 64 reg-shift = <2>; 65 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&bpmp TEGRA194_CLK_UARTA>; 67 clock-names = "serial"; 68 resets = <&bpmp TEGRA194_RESET_UARTA>; 69 reset-names = "serial"; 70 status = "disabled"; 71 }; 72 73 uartb: serial@3110000 { 74 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 75 reg = <0x03110000 0x40>; 76 reg-shift = <2>; 77 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&bpmp TEGRA194_CLK_UARTB>; 79 clock-names = "serial"; 80 resets = <&bpmp TEGRA194_RESET_UARTB>; 81 reset-names = "serial"; 82 status = "disabled"; 83 }; 84 85 uartd: serial@3130000 { 86 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 87 reg = <0x03130000 0x40>; 88 reg-shift = <2>; 89 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&bpmp TEGRA194_CLK_UARTD>; 91 clock-names = "serial"; 92 resets = <&bpmp TEGRA194_RESET_UARTD>; 93 reset-names = "serial"; 94 status = "disabled"; 95 }; 96 97 uarte: serial@3140000 { 98 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 99 reg = <0x03140000 0x40>; 100 reg-shift = <2>; 101 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&bpmp TEGRA194_CLK_UARTE>; 103 clock-names = "serial"; 104 resets = <&bpmp TEGRA194_RESET_UARTE>; 105 reset-names = "serial"; 106 status = "disabled"; 107 }; 108 109 uartf: serial@3150000 { 110 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 111 reg = <0x03150000 0x40>; 112 reg-shift = <2>; 113 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&bpmp TEGRA194_CLK_UARTF>; 115 clock-names = "serial"; 116 resets = <&bpmp TEGRA194_RESET_UARTF>; 117 reset-names = "serial"; 118 status = "disabled"; 119 }; 120 121 gen1_i2c: i2c@3160000 { 122 compatible = "nvidia,tegra194-i2c"; 123 reg = <0x03160000 0x10000>; 124 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 clocks = <&bpmp TEGRA194_CLK_I2C1>; 128 clock-names = "div-clk"; 129 resets = <&bpmp TEGRA194_RESET_I2C1>; 130 reset-names = "i2c"; 131 status = "disabled"; 132 }; 133 134 uarth: serial@3170000 { 135 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 136 reg = <0x03170000 0x40>; 137 reg-shift = <2>; 138 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&bpmp TEGRA194_CLK_UARTH>; 140 clock-names = "serial"; 141 resets = <&bpmp TEGRA194_RESET_UARTH>; 142 reset-names = "serial"; 143 status = "disabled"; 144 }; 145 146 cam_i2c: i2c@3180000 { 147 compatible = "nvidia,tegra194-i2c"; 148 reg = <0x03180000 0x10000>; 149 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 clocks = <&bpmp TEGRA194_CLK_I2C3>; 153 clock-names = "div-clk"; 154 resets = <&bpmp TEGRA194_RESET_I2C3>; 155 reset-names = "i2c"; 156 status = "disabled"; 157 }; 158 159 /* shares pads with dpaux1 */ 160 dp_aux_ch1_i2c: i2c@3190000 { 161 compatible = "nvidia,tegra194-i2c"; 162 reg = <0x03190000 0x10000>; 163 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clocks = <&bpmp TEGRA194_CLK_I2C4>; 167 clock-names = "div-clk"; 168 resets = <&bpmp TEGRA194_RESET_I2C4>; 169 reset-names = "i2c"; 170 status = "disabled"; 171 }; 172 173 /* shares pads with dpaux0 */ 174 dp_aux_ch0_i2c: i2c@31b0000 { 175 compatible = "nvidia,tegra194-i2c"; 176 reg = <0x031b0000 0x10000>; 177 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clocks = <&bpmp TEGRA194_CLK_I2C6>; 181 clock-names = "div-clk"; 182 resets = <&bpmp TEGRA194_RESET_I2C6>; 183 reset-names = "i2c"; 184 status = "disabled"; 185 }; 186 187 gen7_i2c: i2c@31c0000 { 188 compatible = "nvidia,tegra194-i2c"; 189 reg = <0x031c0000 0x10000>; 190 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 clocks = <&bpmp TEGRA194_CLK_I2C7>; 194 clock-names = "div-clk"; 195 resets = <&bpmp TEGRA194_RESET_I2C7>; 196 reset-names = "i2c"; 197 status = "disabled"; 198 }; 199 200 gen9_i2c: i2c@31e0000 { 201 compatible = "nvidia,tegra194-i2c"; 202 reg = <0x031e0000 0x10000>; 203 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 clocks = <&bpmp TEGRA194_CLK_I2C9>; 207 clock-names = "div-clk"; 208 resets = <&bpmp TEGRA194_RESET_I2C9>; 209 reset-names = "i2c"; 210 status = "disabled"; 211 }; 212 213 pwm1: pwm@3280000 { 214 compatible = "nvidia,tegra194-pwm", 215 "nvidia,tegra186-pwm"; 216 reg = <0x3280000 0x10000>; 217 clocks = <&bpmp TEGRA194_CLK_PWM1>; 218 clock-names = "pwm"; 219 resets = <&bpmp TEGRA194_RESET_PWM1>; 220 reset-names = "pwm"; 221 status = "disabled"; 222 #pwm-cells = <2>; 223 }; 224 225 pwm2: pwm@3290000 { 226 compatible = "nvidia,tegra194-pwm", 227 "nvidia,tegra186-pwm"; 228 reg = <0x3290000 0x10000>; 229 clocks = <&bpmp TEGRA194_CLK_PWM2>; 230 clock-names = "pwm"; 231 resets = <&bpmp TEGRA194_RESET_PWM2>; 232 reset-names = "pwm"; 233 status = "disabled"; 234 #pwm-cells = <2>; 235 }; 236 237 pwm3: pwm@32a0000 { 238 compatible = "nvidia,tegra194-pwm", 239 "nvidia,tegra186-pwm"; 240 reg = <0x32a0000 0x10000>; 241 clocks = <&bpmp TEGRA194_CLK_PWM3>; 242 clock-names = "pwm"; 243 resets = <&bpmp TEGRA194_RESET_PWM3>; 244 reset-names = "pwm"; 245 status = "disabled"; 246 #pwm-cells = <2>; 247 }; 248 249 pwm5: pwm@32c0000 { 250 compatible = "nvidia,tegra194-pwm", 251 "nvidia,tegra186-pwm"; 252 reg = <0x32c0000 0x10000>; 253 clocks = <&bpmp TEGRA194_CLK_PWM5>; 254 clock-names = "pwm"; 255 resets = <&bpmp TEGRA194_RESET_PWM5>; 256 reset-names = "pwm"; 257 status = "disabled"; 258 #pwm-cells = <2>; 259 }; 260 261 pwm6: pwm@32d0000 { 262 compatible = "nvidia,tegra194-pwm", 263 "nvidia,tegra186-pwm"; 264 reg = <0x32d0000 0x10000>; 265 clocks = <&bpmp TEGRA194_CLK_PWM6>; 266 clock-names = "pwm"; 267 resets = <&bpmp TEGRA194_RESET_PWM6>; 268 reset-names = "pwm"; 269 status = "disabled"; 270 #pwm-cells = <2>; 271 }; 272 273 pwm7: pwm@32e0000 { 274 compatible = "nvidia,tegra194-pwm", 275 "nvidia,tegra186-pwm"; 276 reg = <0x32e0000 0x10000>; 277 clocks = <&bpmp TEGRA194_CLK_PWM7>; 278 clock-names = "pwm"; 279 resets = <&bpmp TEGRA194_RESET_PWM7>; 280 reset-names = "pwm"; 281 status = "disabled"; 282 #pwm-cells = <2>; 283 }; 284 285 pwm8: pwm@32f0000 { 286 compatible = "nvidia,tegra194-pwm", 287 "nvidia,tegra186-pwm"; 288 reg = <0x32f0000 0x10000>; 289 clocks = <&bpmp TEGRA194_CLK_PWM8>; 290 clock-names = "pwm"; 291 resets = <&bpmp TEGRA194_RESET_PWM8>; 292 reset-names = "pwm"; 293 status = "disabled"; 294 #pwm-cells = <2>; 295 }; 296 297 sdmmc1: sdhci@3400000 { 298 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 299 reg = <0x03400000 0x10000>; 300 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 302 clock-names = "sdhci"; 303 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 304 reset-names = "sdhci"; 305 status = "disabled"; 306 }; 307 308 sdmmc3: sdhci@3440000 { 309 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 310 reg = <0x03440000 0x10000>; 311 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 313 clock-names = "sdhci"; 314 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 315 reset-names = "sdhci"; 316 status = "disabled"; 317 }; 318 319 sdmmc4: sdhci@3460000 { 320 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 321 reg = <0x03460000 0x10000>; 322 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 324 clock-names = "sdhci"; 325 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 326 reset-names = "sdhci"; 327 status = "disabled"; 328 }; 329 330 gic: interrupt-controller@3881000 { 331 compatible = "arm,gic-400"; 332 #interrupt-cells = <3>; 333 interrupt-controller; 334 reg = <0x03881000 0x1000>, 335 <0x03882000 0x2000>, 336 <0x03884000 0x2000>, 337 <0x03886000 0x2000>; 338 interrupts = <GIC_PPI 9 339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 340 interrupt-parent = <&gic>; 341 }; 342 343 hsp_top0: hsp@3c00000 { 344 compatible = "nvidia,tegra186-hsp"; 345 reg = <0x03c00000 0xa0000>; 346 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 347 interrupt-names = "doorbell"; 348 #mbox-cells = <2>; 349 }; 350 351 gen2_i2c: i2c@c240000 { 352 compatible = "nvidia,tegra194-i2c"; 353 reg = <0x0c240000 0x10000>; 354 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 clocks = <&bpmp TEGRA194_CLK_I2C2>; 358 clock-names = "div-clk"; 359 resets = <&bpmp TEGRA194_RESET_I2C2>; 360 reset-names = "i2c"; 361 status = "disabled"; 362 }; 363 364 gen8_i2c: i2c@c250000 { 365 compatible = "nvidia,tegra194-i2c"; 366 reg = <0x0c250000 0x10000>; 367 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 clocks = <&bpmp TEGRA194_CLK_I2C8>; 371 clock-names = "div-clk"; 372 resets = <&bpmp TEGRA194_RESET_I2C8>; 373 reset-names = "i2c"; 374 status = "disabled"; 375 }; 376 377 uartc: serial@c280000 { 378 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 379 reg = <0x0c280000 0x40>; 380 reg-shift = <2>; 381 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&bpmp TEGRA194_CLK_UARTC>; 383 clock-names = "serial"; 384 resets = <&bpmp TEGRA194_RESET_UARTC>; 385 reset-names = "serial"; 386 status = "disabled"; 387 }; 388 389 uartg: serial@c290000 { 390 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 391 reg = <0x0c290000 0x40>; 392 reg-shift = <2>; 393 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&bpmp TEGRA194_CLK_UARTG>; 395 clock-names = "serial"; 396 resets = <&bpmp TEGRA194_RESET_UARTG>; 397 reset-names = "serial"; 398 status = "disabled"; 399 }; 400 401 pwm4: pwm@c340000 { 402 compatible = "nvidia,tegra194-pwm", 403 "nvidia,tegra186-pwm"; 404 reg = <0xc340000 0x10000>; 405 clocks = <&bpmp TEGRA194_CLK_PWM4>; 406 clock-names = "pwm"; 407 resets = <&bpmp TEGRA194_RESET_PWM4>; 408 reset-names = "pwm"; 409 status = "disabled"; 410 #pwm-cells = <2>; 411 }; 412 413 pmc@c360000 { 414 compatible = "nvidia,tegra194-pmc"; 415 reg = <0x0c360000 0x10000>, 416 <0x0c370000 0x10000>, 417 <0x0c380000 0x10000>, 418 <0x0c390000 0x10000>, 419 <0x0c3a0000 0x10000>; 420 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 421 }; 422 423 host1x@13e00000 { 424 compatible = "nvidia,tegra194-host1x", "simple-bus"; 425 reg = <0x13e00000 0x10000>, 426 <0x13e10000 0x10000>; 427 reg-names = "hypervisor", "vm"; 428 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 431 clock-names = "host1x"; 432 resets = <&bpmp TEGRA194_RESET_HOST1X>; 433 reset-names = "host1x"; 434 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 ranges = <0x15000000 0x15000000 0x01000000>; 439 440 display-hub@15200000 { 441 compatible = "nvidia,tegra194-display", "simple-bus"; 442 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 443 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 444 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 445 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 446 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 447 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 448 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 449 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 450 "wgrp3", "wgrp4", "wgrp5"; 451 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 452 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 453 clock-names = "disp", "hub"; 454 status = "disabled"; 455 456 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 457 458 #address-cells = <1>; 459 #size-cells = <1>; 460 461 ranges = <0x15200000 0x15200000 0x40000>; 462 463 display@15200000 { 464 compatible = "nvidia,tegra194-dc"; 465 reg = <0x15200000 0x10000>; 466 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 468 clock-names = "dc"; 469 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 470 reset-names = "dc"; 471 472 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 473 474 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 475 nvidia,head = <0>; 476 }; 477 478 display@15210000 { 479 compatible = "nvidia,tegra194-dc"; 480 reg = <0x15210000 0x10000>; 481 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 483 clock-names = "dc"; 484 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 485 reset-names = "dc"; 486 487 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 488 489 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 490 nvidia,head = <1>; 491 }; 492 493 display@15220000 { 494 compatible = "nvidia,tegra194-dc"; 495 reg = <0x15220000 0x10000>; 496 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 498 clock-names = "dc"; 499 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 500 reset-names = "dc"; 501 502 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 503 504 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 505 nvidia,head = <2>; 506 }; 507 508 display@15230000 { 509 compatible = "nvidia,tegra194-dc"; 510 reg = <0x15230000 0x10000>; 511 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 513 clock-names = "dc"; 514 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 515 reset-names = "dc"; 516 517 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 518 519 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 520 nvidia,head = <3>; 521 }; 522 }; 523 524 dpaux0: dpaux@155c0000 { 525 compatible = "nvidia,tegra194-dpaux"; 526 reg = <0x155c0000 0x10000>; 527 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 529 <&bpmp TEGRA194_CLK_PLLDP>; 530 clock-names = "dpaux", "parent"; 531 resets = <&bpmp TEGRA194_RESET_DPAUX>; 532 reset-names = "dpaux"; 533 status = "disabled"; 534 535 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 536 537 state_dpaux0_aux: pinmux-aux { 538 groups = "dpaux-io"; 539 function = "aux"; 540 }; 541 542 state_dpaux0_i2c: pinmux-i2c { 543 groups = "dpaux-io"; 544 function = "i2c"; 545 }; 546 547 state_dpaux0_off: pinmux-off { 548 groups = "dpaux-io"; 549 function = "off"; 550 }; 551 552 i2c-bus { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 }; 556 }; 557 558 dpaux1: dpaux@155d0000 { 559 compatible = "nvidia,tegra194-dpaux"; 560 reg = <0x155d0000 0x10000>; 561 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 563 <&bpmp TEGRA194_CLK_PLLDP>; 564 clock-names = "dpaux", "parent"; 565 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 566 reset-names = "dpaux"; 567 status = "disabled"; 568 569 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 570 571 state_dpaux1_aux: pinmux-aux { 572 groups = "dpaux-io"; 573 function = "aux"; 574 }; 575 576 state_dpaux1_i2c: pinmux-i2c { 577 groups = "dpaux-io"; 578 function = "i2c"; 579 }; 580 581 state_dpaux1_off: pinmux-off { 582 groups = "dpaux-io"; 583 function = "off"; 584 }; 585 586 i2c-bus { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 }; 590 }; 591 592 dpaux2: dpaux@155e0000 { 593 compatible = "nvidia,tegra194-dpaux"; 594 reg = <0x155e0000 0x10000>; 595 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 597 <&bpmp TEGRA194_CLK_PLLDP>; 598 clock-names = "dpaux", "parent"; 599 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 600 reset-names = "dpaux"; 601 status = "disabled"; 602 603 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 604 605 state_dpaux2_aux: pinmux-aux { 606 groups = "dpaux-io"; 607 function = "aux"; 608 }; 609 610 state_dpaux2_i2c: pinmux-i2c { 611 groups = "dpaux-io"; 612 function = "i2c"; 613 }; 614 615 state_dpaux2_off: pinmux-off { 616 groups = "dpaux-io"; 617 function = "off"; 618 }; 619 620 i2c-bus { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 }; 624 }; 625 626 dpaux3: dpaux@155f0000 { 627 compatible = "nvidia,tegra194-dpaux"; 628 reg = <0x155f0000 0x10000>; 629 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 631 <&bpmp TEGRA194_CLK_PLLDP>; 632 clock-names = "dpaux", "parent"; 633 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 634 reset-names = "dpaux"; 635 status = "disabled"; 636 637 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 638 639 state_dpaux3_aux: pinmux-aux { 640 groups = "dpaux-io"; 641 function = "aux"; 642 }; 643 644 state_dpaux3_i2c: pinmux-i2c { 645 groups = "dpaux-io"; 646 function = "i2c"; 647 }; 648 649 state_dpaux3_off: pinmux-off { 650 groups = "dpaux-io"; 651 function = "off"; 652 }; 653 654 i2c-bus { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 }; 658 }; 659 660 sor0: sor@15b00000 { 661 compatible = "nvidia,tegra194-sor"; 662 reg = <0x15b00000 0x40000>; 663 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 665 <&bpmp TEGRA194_CLK_SOR0_OUT>, 666 <&bpmp TEGRA194_CLK_PLLD>, 667 <&bpmp TEGRA194_CLK_PLLDP>, 668 <&bpmp TEGRA194_CLK_SOR_SAFE>, 669 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 670 clock-names = "sor", "out", "parent", "dp", "safe", 671 "pad"; 672 resets = <&bpmp TEGRA194_RESET_SOR0>; 673 reset-names = "sor"; 674 pinctrl-0 = <&state_dpaux0_aux>; 675 pinctrl-1 = <&state_dpaux0_i2c>; 676 pinctrl-2 = <&state_dpaux0_off>; 677 pinctrl-names = "aux", "i2c", "off"; 678 status = "disabled"; 679 680 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 681 nvidia,interface = <0>; 682 }; 683 684 sor1: sor@15b40000 { 685 compatible = "nvidia,tegra194-sor"; 686 reg = <0x155c0000 0x40000>; 687 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 689 <&bpmp TEGRA194_CLK_SOR1_OUT>, 690 <&bpmp TEGRA194_CLK_PLLD2>, 691 <&bpmp TEGRA194_CLK_PLLDP>, 692 <&bpmp TEGRA194_CLK_SOR_SAFE>, 693 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 694 clock-names = "sor", "out", "parent", "dp", "safe", 695 "pad"; 696 resets = <&bpmp TEGRA194_RESET_SOR1>; 697 reset-names = "sor"; 698 pinctrl-0 = <&state_dpaux1_aux>; 699 pinctrl-1 = <&state_dpaux1_i2c>; 700 pinctrl-2 = <&state_dpaux1_off>; 701 pinctrl-names = "aux", "i2c", "off"; 702 status = "disabled"; 703 704 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 705 nvidia,interface = <1>; 706 }; 707 708 sor2: sor@15b80000 { 709 compatible = "nvidia,tegra194-sor"; 710 reg = <0x15b80000 0x40000>; 711 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 713 <&bpmp TEGRA194_CLK_SOR2_OUT>, 714 <&bpmp TEGRA194_CLK_PLLD3>, 715 <&bpmp TEGRA194_CLK_PLLDP>, 716 <&bpmp TEGRA194_CLK_SOR_SAFE>, 717 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 718 clock-names = "sor", "out", "parent", "dp", "safe", 719 "pad"; 720 resets = <&bpmp TEGRA194_RESET_SOR2>; 721 reset-names = "sor"; 722 pinctrl-0 = <&state_dpaux2_aux>; 723 pinctrl-1 = <&state_dpaux2_i2c>; 724 pinctrl-2 = <&state_dpaux2_off>; 725 pinctrl-names = "aux", "i2c", "off"; 726 status = "disabled"; 727 728 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 729 nvidia,interface = <2>; 730 }; 731 732 sor3: sor@15bc0000 { 733 compatible = "nvidia,tegra194-sor"; 734 reg = <0x15bc0000 0x40000>; 735 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 737 <&bpmp TEGRA194_CLK_SOR3_OUT>, 738 <&bpmp TEGRA194_CLK_PLLD4>, 739 <&bpmp TEGRA194_CLK_PLLDP>, 740 <&bpmp TEGRA194_CLK_SOR_SAFE>, 741 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 742 clock-names = "sor", "out", "parent", "dp", "safe", 743 "pad"; 744 resets = <&bpmp TEGRA194_RESET_SOR3>; 745 reset-names = "sor"; 746 pinctrl-0 = <&state_dpaux3_aux>; 747 pinctrl-1 = <&state_dpaux3_i2c>; 748 pinctrl-2 = <&state_dpaux3_off>; 749 pinctrl-names = "aux", "i2c", "off"; 750 status = "disabled"; 751 752 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 753 nvidia,interface = <3>; 754 }; 755 }; 756 }; 757 758 sysram@40000000 { 759 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 760 reg = <0x0 0x40000000 0x0 0x50000>; 761 #address-cells = <1>; 762 #size-cells = <1>; 763 ranges = <0x0 0x0 0x40000000 0x50000>; 764 765 cpu_bpmp_tx: shmem@4e000 { 766 compatible = "nvidia,tegra194-bpmp-shmem"; 767 reg = <0x4e000 0x1000>; 768 label = "cpu-bpmp-tx"; 769 pool; 770 }; 771 772 cpu_bpmp_rx: shmem@4f000 { 773 compatible = "nvidia,tegra194-bpmp-shmem"; 774 reg = <0x4f000 0x1000>; 775 label = "cpu-bpmp-rx"; 776 pool; 777 }; 778 }; 779 780 bpmp: bpmp { 781 compatible = "nvidia,tegra186-bpmp"; 782 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 783 TEGRA_HSP_DB_MASTER_BPMP>; 784 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 785 #clock-cells = <1>; 786 #reset-cells = <1>; 787 #power-domain-cells = <1>; 788 789 bpmp_i2c: i2c { 790 compatible = "nvidia,tegra186-bpmp-i2c"; 791 nvidia,bpmp-bus-id = <5>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 }; 795 796 bpmp_thermal: thermal { 797 compatible = "nvidia,tegra186-bpmp-thermal"; 798 #thermal-sensor-cells = <1>; 799 }; 800 }; 801 802 cpus { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 806 cpu@0 { 807 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 808 device_type = "cpu"; 809 reg = <0x10000>; 810 enable-method = "psci"; 811 }; 812 813 cpu@1 { 814 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 815 device_type = "cpu"; 816 reg = <0x10001>; 817 enable-method = "psci"; 818 }; 819 820 cpu@2 { 821 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 822 device_type = "cpu"; 823 reg = <0x100>; 824 enable-method = "psci"; 825 }; 826 827 cpu@3 { 828 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 829 device_type = "cpu"; 830 reg = <0x101>; 831 enable-method = "psci"; 832 }; 833 834 cpu@4 { 835 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 836 device_type = "cpu"; 837 reg = <0x200>; 838 enable-method = "psci"; 839 }; 840 841 cpu@5 { 842 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 843 device_type = "cpu"; 844 reg = <0x201>; 845 enable-method = "psci"; 846 }; 847 848 cpu@6 { 849 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 850 device_type = "cpu"; 851 reg = <0x10300>; 852 enable-method = "psci"; 853 }; 854 855 cpu@7 { 856 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 857 device_type = "cpu"; 858 reg = <0x10301>; 859 enable-method = "psci"; 860 }; 861 }; 862 863 psci { 864 compatible = "arm,psci-1.0"; 865 status = "okay"; 866 method = "smc"; 867 }; 868 869 timer { 870 compatible = "arm,armv8-timer"; 871 interrupts = <GIC_PPI 13 872 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 873 <GIC_PPI 14 874 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 875 <GIC_PPI 11 876 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 877 <GIC_PPI 10 878 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 879 interrupt-parent = <&gic>; 880 }; 881}; 882