1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8 9/ { 10 compatible = "nvidia,tegra194"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 /* control backbone */ 16 cbb { 17 compatible = "simple-bus"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges = <0x0 0x0 0x0 0x40000000>; 21 22 gpio: gpio@2200000 { 23 compatible = "nvidia,tegra194-gpio"; 24 reg-names = "security", "gpio"; 25 reg = <0x2200000 0x10000>, 26 <0x2210000 0x10000>; 27 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 33 #interrupt-cells = <2>; 34 interrupt-controller; 35 #gpio-cells = <2>; 36 gpio-controller; 37 }; 38 39 ethernet@2490000 { 40 compatible = "nvidia,tegra186-eqos", 41 "snps,dwc-qos-ethernet-4.10"; 42 reg = <0x02490000 0x10000>; 43 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 44 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 45 <&bpmp TEGRA194_CLK_EQOS_AXI>, 46 <&bpmp TEGRA194_CLK_EQOS_RX>, 47 <&bpmp TEGRA194_CLK_EQOS_TX>, 48 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 49 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 50 resets = <&bpmp TEGRA194_RESET_EQOS>; 51 reset-names = "eqos"; 52 status = "disabled"; 53 54 snps,write-requests = <1>; 55 snps,read-requests = <3>; 56 snps,burst-map = <0x7>; 57 snps,txpbl = <16>; 58 snps,rxpbl = <8>; 59 }; 60 61 uarta: serial@3100000 { 62 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 63 reg = <0x03100000 0x40>; 64 reg-shift = <2>; 65 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&bpmp TEGRA194_CLK_UARTA>; 67 clock-names = "serial"; 68 resets = <&bpmp TEGRA194_RESET_UARTA>; 69 reset-names = "serial"; 70 status = "disabled"; 71 }; 72 73 uartb: serial@3110000 { 74 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 75 reg = <0x03110000 0x40>; 76 reg-shift = <2>; 77 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&bpmp TEGRA194_CLK_UARTB>; 79 clock-names = "serial"; 80 resets = <&bpmp TEGRA194_RESET_UARTB>; 81 reset-names = "serial"; 82 status = "disabled"; 83 }; 84 85 uartd: serial@3130000 { 86 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 87 reg = <0x03130000 0x40>; 88 reg-shift = <2>; 89 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&bpmp TEGRA194_CLK_UARTD>; 91 clock-names = "serial"; 92 resets = <&bpmp TEGRA194_RESET_UARTD>; 93 reset-names = "serial"; 94 status = "disabled"; 95 }; 96 97 uarte: serial@3140000 { 98 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 99 reg = <0x03140000 0x40>; 100 reg-shift = <2>; 101 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&bpmp TEGRA194_CLK_UARTE>; 103 clock-names = "serial"; 104 resets = <&bpmp TEGRA194_RESET_UARTE>; 105 reset-names = "serial"; 106 status = "disabled"; 107 }; 108 109 uartf: serial@3150000 { 110 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 111 reg = <0x03150000 0x40>; 112 reg-shift = <2>; 113 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&bpmp TEGRA194_CLK_UARTF>; 115 clock-names = "serial"; 116 resets = <&bpmp TEGRA194_RESET_UARTF>; 117 reset-names = "serial"; 118 status = "disabled"; 119 }; 120 121 gen1_i2c: i2c@3160000 { 122 compatible = "nvidia,tegra194-i2c"; 123 reg = <0x03160000 0x10000>; 124 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 clocks = <&bpmp TEGRA194_CLK_I2C1>; 128 clock-names = "div-clk"; 129 resets = <&bpmp TEGRA194_RESET_I2C1>; 130 reset-names = "i2c"; 131 status = "disabled"; 132 }; 133 134 uarth: serial@3170000 { 135 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 136 reg = <0x03170000 0x40>; 137 reg-shift = <2>; 138 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&bpmp TEGRA194_CLK_UARTH>; 140 clock-names = "serial"; 141 resets = <&bpmp TEGRA194_RESET_UARTH>; 142 reset-names = "serial"; 143 status = "disabled"; 144 }; 145 146 cam_i2c: i2c@3180000 { 147 compatible = "nvidia,tegra194-i2c"; 148 reg = <0x03180000 0x10000>; 149 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 clocks = <&bpmp TEGRA194_CLK_I2C3>; 153 clock-names = "div-clk"; 154 resets = <&bpmp TEGRA194_RESET_I2C3>; 155 reset-names = "i2c"; 156 status = "disabled"; 157 }; 158 159 /* shares pads with dpaux1 */ 160 dp_aux_ch1_i2c: i2c@3190000 { 161 compatible = "nvidia,tegra194-i2c"; 162 reg = <0x03190000 0x10000>; 163 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clocks = <&bpmp TEGRA194_CLK_I2C4>; 167 clock-names = "div-clk"; 168 resets = <&bpmp TEGRA194_RESET_I2C4>; 169 reset-names = "i2c"; 170 status = "disabled"; 171 }; 172 173 /* shares pads with dpaux0 */ 174 dp_aux_ch0_i2c: i2c@31b0000 { 175 compatible = "nvidia,tegra194-i2c"; 176 reg = <0x031b0000 0x10000>; 177 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clocks = <&bpmp TEGRA194_CLK_I2C6>; 181 clock-names = "div-clk"; 182 resets = <&bpmp TEGRA194_RESET_I2C6>; 183 reset-names = "i2c"; 184 status = "disabled"; 185 }; 186 187 gen7_i2c: i2c@31c0000 { 188 compatible = "nvidia,tegra194-i2c"; 189 reg = <0x031c0000 0x10000>; 190 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 clocks = <&bpmp TEGRA194_CLK_I2C7>; 194 clock-names = "div-clk"; 195 resets = <&bpmp TEGRA194_RESET_I2C7>; 196 reset-names = "i2c"; 197 status = "disabled"; 198 }; 199 200 gen9_i2c: i2c@31e0000 { 201 compatible = "nvidia,tegra194-i2c"; 202 reg = <0x031e0000 0x10000>; 203 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 clocks = <&bpmp TEGRA194_CLK_I2C9>; 207 clock-names = "div-clk"; 208 resets = <&bpmp TEGRA194_RESET_I2C9>; 209 reset-names = "i2c"; 210 status = "disabled"; 211 }; 212 213 pwm1: pwm@3280000 { 214 compatible = "nvidia,tegra194-pwm", 215 "nvidia,tegra186-pwm"; 216 reg = <0x3280000 0x10000>; 217 clocks = <&bpmp TEGRA194_CLK_PWM1>; 218 clock-names = "pwm"; 219 resets = <&bpmp TEGRA194_RESET_PWM1>; 220 reset-names = "pwm"; 221 status = "disabled"; 222 #pwm-cells = <2>; 223 }; 224 225 pwm2: pwm@3290000 { 226 compatible = "nvidia,tegra194-pwm", 227 "nvidia,tegra186-pwm"; 228 reg = <0x3290000 0x10000>; 229 clocks = <&bpmp TEGRA194_CLK_PWM2>; 230 clock-names = "pwm"; 231 resets = <&bpmp TEGRA194_RESET_PWM2>; 232 reset-names = "pwm"; 233 status = "disabled"; 234 #pwm-cells = <2>; 235 }; 236 237 pwm3: pwm@32a0000 { 238 compatible = "nvidia,tegra194-pwm", 239 "nvidia,tegra186-pwm"; 240 reg = <0x32a0000 0x10000>; 241 clocks = <&bpmp TEGRA194_CLK_PWM3>; 242 clock-names = "pwm"; 243 resets = <&bpmp TEGRA194_RESET_PWM3>; 244 reset-names = "pwm"; 245 status = "disabled"; 246 #pwm-cells = <2>; 247 }; 248 249 pwm5: pwm@32c0000 { 250 compatible = "nvidia,tegra194-pwm", 251 "nvidia,tegra186-pwm"; 252 reg = <0x32c0000 0x10000>; 253 clocks = <&bpmp TEGRA194_CLK_PWM5>; 254 clock-names = "pwm"; 255 resets = <&bpmp TEGRA194_RESET_PWM5>; 256 reset-names = "pwm"; 257 status = "disabled"; 258 #pwm-cells = <2>; 259 }; 260 261 pwm6: pwm@32d0000 { 262 compatible = "nvidia,tegra194-pwm", 263 "nvidia,tegra186-pwm"; 264 reg = <0x32d0000 0x10000>; 265 clocks = <&bpmp TEGRA194_CLK_PWM6>; 266 clock-names = "pwm"; 267 resets = <&bpmp TEGRA194_RESET_PWM6>; 268 reset-names = "pwm"; 269 status = "disabled"; 270 #pwm-cells = <2>; 271 }; 272 273 pwm7: pwm@32e0000 { 274 compatible = "nvidia,tegra194-pwm", 275 "nvidia,tegra186-pwm"; 276 reg = <0x32e0000 0x10000>; 277 clocks = <&bpmp TEGRA194_CLK_PWM7>; 278 clock-names = "pwm"; 279 resets = <&bpmp TEGRA194_RESET_PWM7>; 280 reset-names = "pwm"; 281 status = "disabled"; 282 #pwm-cells = <2>; 283 }; 284 285 pwm8: pwm@32f0000 { 286 compatible = "nvidia,tegra194-pwm", 287 "nvidia,tegra186-pwm"; 288 reg = <0x32f0000 0x10000>; 289 clocks = <&bpmp TEGRA194_CLK_PWM8>; 290 clock-names = "pwm"; 291 resets = <&bpmp TEGRA194_RESET_PWM8>; 292 reset-names = "pwm"; 293 status = "disabled"; 294 #pwm-cells = <2>; 295 }; 296 297 sdmmc1: sdhci@3400000 { 298 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 299 reg = <0x03400000 0x10000>; 300 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 302 clock-names = "sdhci"; 303 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 304 reset-names = "sdhci"; 305 status = "disabled"; 306 }; 307 308 sdmmc3: sdhci@3440000 { 309 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 310 reg = <0x03440000 0x10000>; 311 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 313 clock-names = "sdhci"; 314 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 315 reset-names = "sdhci"; 316 status = "disabled"; 317 }; 318 319 sdmmc4: sdhci@3460000 { 320 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 321 reg = <0x03460000 0x10000>; 322 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 324 clock-names = "sdhci"; 325 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 326 reset-names = "sdhci"; 327 status = "disabled"; 328 }; 329 330 gic: interrupt-controller@3881000 { 331 compatible = "arm,gic-400"; 332 #interrupt-cells = <3>; 333 interrupt-controller; 334 reg = <0x03881000 0x1000>, 335 <0x03882000 0x2000>, 336 <0x03884000 0x2000>, 337 <0x03886000 0x2000>; 338 interrupts = <GIC_PPI 9 339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 340 interrupt-parent = <&gic>; 341 }; 342 343 hsp_top0: hsp@3c00000 { 344 compatible = "nvidia,tegra186-hsp"; 345 reg = <0x03c00000 0xa0000>; 346 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 347 interrupt-names = "doorbell"; 348 #mbox-cells = <2>; 349 }; 350 351 gen2_i2c: i2c@c240000 { 352 compatible = "nvidia,tegra194-i2c"; 353 reg = <0x0c240000 0x10000>; 354 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 clocks = <&bpmp TEGRA194_CLK_I2C2>; 358 clock-names = "div-clk"; 359 resets = <&bpmp TEGRA194_RESET_I2C2>; 360 reset-names = "i2c"; 361 status = "disabled"; 362 }; 363 364 gen8_i2c: i2c@c250000 { 365 compatible = "nvidia,tegra194-i2c"; 366 reg = <0x0c250000 0x10000>; 367 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 clocks = <&bpmp TEGRA194_CLK_I2C8>; 371 clock-names = "div-clk"; 372 resets = <&bpmp TEGRA194_RESET_I2C8>; 373 reset-names = "i2c"; 374 status = "disabled"; 375 }; 376 377 uartc: serial@c280000 { 378 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 379 reg = <0x0c280000 0x40>; 380 reg-shift = <2>; 381 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&bpmp TEGRA194_CLK_UARTC>; 383 clock-names = "serial"; 384 resets = <&bpmp TEGRA194_RESET_UARTC>; 385 reset-names = "serial"; 386 status = "disabled"; 387 }; 388 389 uartg: serial@c290000 { 390 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 391 reg = <0x0c290000 0x40>; 392 reg-shift = <2>; 393 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&bpmp TEGRA194_CLK_UARTG>; 395 clock-names = "serial"; 396 resets = <&bpmp TEGRA194_RESET_UARTG>; 397 reset-names = "serial"; 398 status = "disabled"; 399 }; 400 401 pwm4: pwm@c340000 { 402 compatible = "nvidia,tegra194-pwm", 403 "nvidia,tegra186-pwm"; 404 reg = <0xc340000 0x10000>; 405 clocks = <&bpmp TEGRA194_CLK_PWM4>; 406 clock-names = "pwm"; 407 resets = <&bpmp TEGRA194_RESET_PWM4>; 408 reset-names = "pwm"; 409 status = "disabled"; 410 #pwm-cells = <2>; 411 }; 412 413 pmc@c360000 { 414 compatible = "nvidia,tegra194-pmc"; 415 reg = <0x0c360000 0x10000>, 416 <0x0c370000 0x10000>, 417 <0x0c380000 0x10000>, 418 <0x0c390000 0x10000>, 419 <0x0c3a0000 0x10000>; 420 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 421 }; 422 423 host1x@13e00000 { 424 compatible = "nvidia,tegra194-host1x", "simple-bus"; 425 reg = <0x13e00000 0x10000>, 426 <0x13e10000 0x10000>; 427 reg-names = "hypervisor", "vm"; 428 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 431 clock-names = "host1x"; 432 resets = <&bpmp TEGRA194_RESET_HOST1X>; 433 reset-names = "host1x"; 434 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 ranges = <0x15000000 0x15000000 0x01000000>; 439 440 display-hub@15200000 { 441 compatible = "nvidia,tegra194-display", "simple-bus"; 442 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 443 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 444 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 445 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 446 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 447 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 448 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 449 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 450 "wgrp3", "wgrp4", "wgrp5"; 451 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 452 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 453 clock-names = "disp", "hub"; 454 status = "disabled"; 455 456 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 457 458 #address-cells = <1>; 459 #size-cells = <1>; 460 461 ranges = <0x15200000 0x15200000 0x40000>; 462 463 display@15200000 { 464 compatible = "nvidia,tegra194-dc"; 465 reg = <0x15200000 0x10000>; 466 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 468 clock-names = "dc"; 469 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 470 reset-names = "dc"; 471 472 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 473 474 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 475 nvidia,head = <0>; 476 }; 477 478 display@15210000 { 479 compatible = "nvidia,tegra194-dc"; 480 reg = <0x15210000 0x10000>; 481 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 483 clock-names = "dc"; 484 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 485 reset-names = "dc"; 486 487 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 488 489 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 490 nvidia,head = <1>; 491 }; 492 493 display@15220000 { 494 compatible = "nvidia,tegra194-dc"; 495 reg = <0x15220000 0x10000>; 496 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 498 clock-names = "dc"; 499 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 500 reset-names = "dc"; 501 502 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 503 504 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 505 nvidia,head = <2>; 506 }; 507 508 display@15230000 { 509 compatible = "nvidia,tegra194-dc"; 510 reg = <0x15230000 0x10000>; 511 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 513 clock-names = "dc"; 514 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 515 reset-names = "dc"; 516 517 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 518 519 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 520 nvidia,head = <3>; 521 }; 522 }; 523 524 vic@15340000 { 525 compatible = "nvidia,tegra194-vic"; 526 reg = <0x15340000 0x00040000>; 527 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&bpmp TEGRA194_CLK_VIC>; 529 clock-names = "vic"; 530 resets = <&bpmp TEGRA194_RESET_VIC>; 531 reset-names = "vic"; 532 533 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 534 }; 535 536 dpaux0: dpaux@155c0000 { 537 compatible = "nvidia,tegra194-dpaux"; 538 reg = <0x155c0000 0x10000>; 539 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 541 <&bpmp TEGRA194_CLK_PLLDP>; 542 clock-names = "dpaux", "parent"; 543 resets = <&bpmp TEGRA194_RESET_DPAUX>; 544 reset-names = "dpaux"; 545 status = "disabled"; 546 547 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 548 549 state_dpaux0_aux: pinmux-aux { 550 groups = "dpaux-io"; 551 function = "aux"; 552 }; 553 554 state_dpaux0_i2c: pinmux-i2c { 555 groups = "dpaux-io"; 556 function = "i2c"; 557 }; 558 559 state_dpaux0_off: pinmux-off { 560 groups = "dpaux-io"; 561 function = "off"; 562 }; 563 564 i2c-bus { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 }; 568 }; 569 570 dpaux1: dpaux@155d0000 { 571 compatible = "nvidia,tegra194-dpaux"; 572 reg = <0x155d0000 0x10000>; 573 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 575 <&bpmp TEGRA194_CLK_PLLDP>; 576 clock-names = "dpaux", "parent"; 577 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 578 reset-names = "dpaux"; 579 status = "disabled"; 580 581 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 582 583 state_dpaux1_aux: pinmux-aux { 584 groups = "dpaux-io"; 585 function = "aux"; 586 }; 587 588 state_dpaux1_i2c: pinmux-i2c { 589 groups = "dpaux-io"; 590 function = "i2c"; 591 }; 592 593 state_dpaux1_off: pinmux-off { 594 groups = "dpaux-io"; 595 function = "off"; 596 }; 597 598 i2c-bus { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 }; 602 }; 603 604 dpaux2: dpaux@155e0000 { 605 compatible = "nvidia,tegra194-dpaux"; 606 reg = <0x155e0000 0x10000>; 607 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 609 <&bpmp TEGRA194_CLK_PLLDP>; 610 clock-names = "dpaux", "parent"; 611 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 612 reset-names = "dpaux"; 613 status = "disabled"; 614 615 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 616 617 state_dpaux2_aux: pinmux-aux { 618 groups = "dpaux-io"; 619 function = "aux"; 620 }; 621 622 state_dpaux2_i2c: pinmux-i2c { 623 groups = "dpaux-io"; 624 function = "i2c"; 625 }; 626 627 state_dpaux2_off: pinmux-off { 628 groups = "dpaux-io"; 629 function = "off"; 630 }; 631 632 i2c-bus { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 }; 636 }; 637 638 dpaux3: dpaux@155f0000 { 639 compatible = "nvidia,tegra194-dpaux"; 640 reg = <0x155f0000 0x10000>; 641 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 643 <&bpmp TEGRA194_CLK_PLLDP>; 644 clock-names = "dpaux", "parent"; 645 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 646 reset-names = "dpaux"; 647 status = "disabled"; 648 649 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 650 651 state_dpaux3_aux: pinmux-aux { 652 groups = "dpaux-io"; 653 function = "aux"; 654 }; 655 656 state_dpaux3_i2c: pinmux-i2c { 657 groups = "dpaux-io"; 658 function = "i2c"; 659 }; 660 661 state_dpaux3_off: pinmux-off { 662 groups = "dpaux-io"; 663 function = "off"; 664 }; 665 666 i2c-bus { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 }; 670 }; 671 672 sor0: sor@15b00000 { 673 compatible = "nvidia,tegra194-sor"; 674 reg = <0x15b00000 0x40000>; 675 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 677 <&bpmp TEGRA194_CLK_SOR0_OUT>, 678 <&bpmp TEGRA194_CLK_PLLD>, 679 <&bpmp TEGRA194_CLK_PLLDP>, 680 <&bpmp TEGRA194_CLK_SOR_SAFE>, 681 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 682 clock-names = "sor", "out", "parent", "dp", "safe", 683 "pad"; 684 resets = <&bpmp TEGRA194_RESET_SOR0>; 685 reset-names = "sor"; 686 pinctrl-0 = <&state_dpaux0_aux>; 687 pinctrl-1 = <&state_dpaux0_i2c>; 688 pinctrl-2 = <&state_dpaux0_off>; 689 pinctrl-names = "aux", "i2c", "off"; 690 status = "disabled"; 691 692 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 693 nvidia,interface = <0>; 694 }; 695 696 sor1: sor@15b40000 { 697 compatible = "nvidia,tegra194-sor"; 698 reg = <0x155c0000 0x40000>; 699 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 701 <&bpmp TEGRA194_CLK_SOR1_OUT>, 702 <&bpmp TEGRA194_CLK_PLLD2>, 703 <&bpmp TEGRA194_CLK_PLLDP>, 704 <&bpmp TEGRA194_CLK_SOR_SAFE>, 705 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 706 clock-names = "sor", "out", "parent", "dp", "safe", 707 "pad"; 708 resets = <&bpmp TEGRA194_RESET_SOR1>; 709 reset-names = "sor"; 710 pinctrl-0 = <&state_dpaux1_aux>; 711 pinctrl-1 = <&state_dpaux1_i2c>; 712 pinctrl-2 = <&state_dpaux1_off>; 713 pinctrl-names = "aux", "i2c", "off"; 714 status = "disabled"; 715 716 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 717 nvidia,interface = <1>; 718 }; 719 720 sor2: sor@15b80000 { 721 compatible = "nvidia,tegra194-sor"; 722 reg = <0x15b80000 0x40000>; 723 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 725 <&bpmp TEGRA194_CLK_SOR2_OUT>, 726 <&bpmp TEGRA194_CLK_PLLD3>, 727 <&bpmp TEGRA194_CLK_PLLDP>, 728 <&bpmp TEGRA194_CLK_SOR_SAFE>, 729 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 730 clock-names = "sor", "out", "parent", "dp", "safe", 731 "pad"; 732 resets = <&bpmp TEGRA194_RESET_SOR2>; 733 reset-names = "sor"; 734 pinctrl-0 = <&state_dpaux2_aux>; 735 pinctrl-1 = <&state_dpaux2_i2c>; 736 pinctrl-2 = <&state_dpaux2_off>; 737 pinctrl-names = "aux", "i2c", "off"; 738 status = "disabled"; 739 740 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 741 nvidia,interface = <2>; 742 }; 743 744 sor3: sor@15bc0000 { 745 compatible = "nvidia,tegra194-sor"; 746 reg = <0x15bc0000 0x40000>; 747 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 749 <&bpmp TEGRA194_CLK_SOR3_OUT>, 750 <&bpmp TEGRA194_CLK_PLLD4>, 751 <&bpmp TEGRA194_CLK_PLLDP>, 752 <&bpmp TEGRA194_CLK_SOR_SAFE>, 753 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 754 clock-names = "sor", "out", "parent", "dp", "safe", 755 "pad"; 756 resets = <&bpmp TEGRA194_RESET_SOR3>; 757 reset-names = "sor"; 758 pinctrl-0 = <&state_dpaux3_aux>; 759 pinctrl-1 = <&state_dpaux3_i2c>; 760 pinctrl-2 = <&state_dpaux3_off>; 761 pinctrl-names = "aux", "i2c", "off"; 762 status = "disabled"; 763 764 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 765 nvidia,interface = <3>; 766 }; 767 }; 768 }; 769 770 sysram@40000000 { 771 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 772 reg = <0x0 0x40000000 0x0 0x50000>; 773 #address-cells = <1>; 774 #size-cells = <1>; 775 ranges = <0x0 0x0 0x40000000 0x50000>; 776 777 cpu_bpmp_tx: shmem@4e000 { 778 compatible = "nvidia,tegra194-bpmp-shmem"; 779 reg = <0x4e000 0x1000>; 780 label = "cpu-bpmp-tx"; 781 pool; 782 }; 783 784 cpu_bpmp_rx: shmem@4f000 { 785 compatible = "nvidia,tegra194-bpmp-shmem"; 786 reg = <0x4f000 0x1000>; 787 label = "cpu-bpmp-rx"; 788 pool; 789 }; 790 }; 791 792 bpmp: bpmp { 793 compatible = "nvidia,tegra186-bpmp"; 794 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 795 TEGRA_HSP_DB_MASTER_BPMP>; 796 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 797 #clock-cells = <1>; 798 #reset-cells = <1>; 799 #power-domain-cells = <1>; 800 801 bpmp_i2c: i2c { 802 compatible = "nvidia,tegra186-bpmp-i2c"; 803 nvidia,bpmp-bus-id = <5>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 }; 807 808 bpmp_thermal: thermal { 809 compatible = "nvidia,tegra186-bpmp-thermal"; 810 #thermal-sensor-cells = <1>; 811 }; 812 }; 813 814 cpus { 815 #address-cells = <1>; 816 #size-cells = <0>; 817 818 cpu@0 { 819 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 820 device_type = "cpu"; 821 reg = <0x10000>; 822 enable-method = "psci"; 823 }; 824 825 cpu@1 { 826 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 827 device_type = "cpu"; 828 reg = <0x10001>; 829 enable-method = "psci"; 830 }; 831 832 cpu@2 { 833 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 834 device_type = "cpu"; 835 reg = <0x100>; 836 enable-method = "psci"; 837 }; 838 839 cpu@3 { 840 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 841 device_type = "cpu"; 842 reg = <0x101>; 843 enable-method = "psci"; 844 }; 845 846 cpu@4 { 847 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 848 device_type = "cpu"; 849 reg = <0x200>; 850 enable-method = "psci"; 851 }; 852 853 cpu@5 { 854 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 855 device_type = "cpu"; 856 reg = <0x201>; 857 enable-method = "psci"; 858 }; 859 860 cpu@6 { 861 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 862 device_type = "cpu"; 863 reg = <0x10300>; 864 enable-method = "psci"; 865 }; 866 867 cpu@7 { 868 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 869 device_type = "cpu"; 870 reg = <0x10301>; 871 enable-method = "psci"; 872 }; 873 }; 874 875 psci { 876 compatible = "arm,psci-1.0"; 877 status = "okay"; 878 method = "smc"; 879 }; 880 881 timer { 882 compatible = "arm,armv8-timer"; 883 interrupts = <GIC_PPI 13 884 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 885 <GIC_PPI 14 886 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 887 <GIC_PPI 11 888 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 889 <GIC_PPI 10 890 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 891 interrupt-parent = <&gic>; 892 }; 893}; 894