Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37 |
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#
dc6d5d85 |
| 29-Jun-2023 |
Sameer Pujar <spujar@nvidia.com> |
arm64: tegra: Update AHUB clock parent and rate
I2S data sanity test failures are seen at lower AHUB clock rates on Tegra234. The Tegra194 uses the same clock relationship for AHUB and it is likely
arm64: tegra: Update AHUB clock parent and rate
I2S data sanity test failures are seen at lower AHUB clock rates on Tegra234. The Tegra194 uses the same clock relationship for AHUB and it is likely that similar issues would be seen. Thus update the AHUB clock parent and rates here as well for Tegra194, Tegra186 and Tegra210.
Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components") Cc: stable@vger.kernel.org Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8 |
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#
71de0a05 |
| 23-Jan-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: tegra: Drop serial clock-names and reset-names
The serial node does not use clock-names and reset-names:
tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('cloc
arm64: tegra: Drop serial clock-names and reset-names
The serial node does not use clock-names and reset-names:
tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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4bb54c2c |
| 14-Feb-2023 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234
Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map, so bump the CBB ranges property to cover all of the 1 TiB add
arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234
Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map, so bump the CBB ranges property to cover all of the 1 TiB address space. This fixes an issue where some of the PCIe regions could not be remapped because of they were outside the memory specified by the CBB's ranges property.
Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3 |
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#
682e1c49 |
| 17-Oct-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Drop I2C iommus and dma-coherent properties
Drop the iommus and dma-coherent properties for the I2C controller device tree nodes. These are only needed for the device tree nodes that r
arm64: tegra: Drop I2C iommus and dma-coherent properties
Drop the iommus and dma-coherent properties for the I2C controller device tree nodes. These are only needed for the device tree nodes that represent the GPC DMA controller, since that is the device performing the direct memory accesses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
361238cd |
| 19-Jan-2023 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Mark host1x as dma-coherent on Tegra194/234
Ensure appropriate configuration is done to make the host1x device and context devices DMA coherent by adding the dma-coherent flag.
Fixes:
arm64: tegra: Mark host1x as dma-coherent on Tegra194/234
Ensure appropriate configuration is done to make the host1x device and context devices DMA coherent by adding the dma-coherent flag.
Fixes: b35f5b53a87b ("arm64: tegra: Add context isolation domains on Tegra234") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
f19bb95d |
| 19-Jan-2023 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Add dma-coherent property for Tegra194 XUDC
DMA operations for XUSB device controller (XUDC) are coherent for Tegra194 and so add the 'dma-coherent' property for this device.
Signed-o
arm64: tegra: Add dma-coherent property for Tegra194 XUDC
DMA operations for XUSB device controller (XUDC) are coherent for Tegra194 and so add the 'dma-coherent' property for this device.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
79ed18d9 |
| 22-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance").
While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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2838cfdd |
| 17-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all th
arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space.
Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children.
While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35 |
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#
979ac5ef |
| 14-Apr-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fix typo in gpio-ranges property
The gpio-ranges property name was missing a terminating "s", causing it to not be parsed and fail DT validation as well.
Signed-off-by: Thierry Reding
arm64: tegra: Fix typo in gpio-ranges property
The gpio-ranges property name was missing a terminating "s", causing it to not be parsed and fail DT validation as well.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
efe499d8 |
| 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fixup pinmux node names
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules.
Signed-off-by: Thierry Reding <tredin
arm64: tegra: Fixup pinmux node names
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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e9ddebc3 |
| 05-Sep-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove reset-names for QSPI
The Tegra QSPI controllers use a single reset control, so reset-names is not necessary and therefore not specified in the DT bindings. Drop the property fro
arm64: tegra: Remove reset-names for QSPI
The Tegra QSPI controllers use a single reset control, so reset-names is not necessary and therefore not specified in the DT bindings. Drop the property from device tree files to avoid validation warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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7f0ea5ac |
| 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Use correct compatible string for Tegra194 HDA
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list.
Signed-
arm64: tegra: Use correct compatible string for Tegra194 HDA
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
27f1568b |
| 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
dd0be827 |
| 10-Nov-2022 |
Akhil R <akhilrajeev@nvidia.com> |
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in kernel and reserve fe
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
6f380a4e |
| 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as on
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as one and the same device, split them up so that they are each their own devices. Also add gpio-ranges properties to the corresponding GPIO controllers such that the pinmux and GPIO controllers can be paired up properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
b6e097df |
| 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove clock-names from PWM nodes
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+
arm64: tegra: Remove clock-names from PWM nodes
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
8fbd2d11 |
| 03-Nov-2022 |
Dipen Patel <dipenp@nvidia.com> |
arm64: tegra: Enable GTE nodes
Add and enable AON and LIC GTE nodes by default.
Signed-off-by: Dipen Patel <dipenp@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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e25770fe |
| 06-Sep-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Fix ranges for host1x nodes
The currently specified 'ranges' properties don't actually include all devices under the host1x bus on Tegra194 and Tegra234. Expand them appropriately.
Si
arm64: tegra: Fix ranges for host1x nodes
The currently specified 'ranges' properties don't actually include all devices under the host1x bus on Tegra194 and Tegra234. Expand them appropriately.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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8e442805 |
| 06-Sep-2022 |
Akhil R <akhilrajeev@nvidia.com> |
arm64: tegra: Add GPCDMA support for Tegra I2C
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Redin
arm64: tegra: Add GPCDMA support for Tegra I2C
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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b0c1a994 |
| 02-Sep-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fixup iommu-map property formatting
Make sure that each phandle-array is enclosed in a set of angular brackets and properly indent each entry.
Signed-off-by: Thierry Reding <treding@n
arm64: tegra: Fixup iommu-map property formatting
Make sure that each phandle-array is enclosed in a set of angular brackets and properly indent each entry.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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e30cf101 |
| 27-Jun-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add Host1x context stream IDs on Tegra186+
Add Host1x context stream IDs on systems that support Host1x context isolation. Host1x and attached engines can use these stream IDs to allow
arm64: tegra: Add Host1x context stream IDs on Tegra186+
Add Host1x context stream IDs on systems that support Host1x context isolation. Host1x and attached engines can use these stream IDs to allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor, if one is present.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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5aa9083e |
| 04-Jul-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Enable native timers on Tegra194
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the dev
arm64: tegra: Enable native timers on Tegra194
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra194.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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a47e173e |
| 11-May-2022 |
Sumit Gupta <sumitg@nvidia.com> |
arm64: tegra: Add node for CBB 1.0 on Tegra194
Add device tree nodes to enable error handling on the Control Backbone (CBB). Tegra194 uses CBB version 1.0.
Signed-off-by: Sumit Gupta <sumitg@nvidia
arm64: tegra: Add node for CBB 1.0 on Tegra194
Add device tree nodes to enable error handling on the Control Backbone (CBB). Tegra194 uses CBB version 1.0.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
61192a9d |
| 22-Jun-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Mark BPMP channels as no-memory-wc
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will caus
arm64: tegra: Mark BPMP channels as no-memory-wc
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues.
Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map.
Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed.
As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory.
Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
4b6a1b7c |
| 06-Jun-2022 |
Sameer Pujar <spujar@nvidia.com> |
arm64: tegra: Add OPE device on Tegra210 and later
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant S
arm64: tegra: Add OPE device on Tegra210 and later
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files.
Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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