1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 aconnect { 63 compatible = "nvidia,tegra194-aconnect", 64 "nvidia,tegra210-aconnect"; 65 clocks = <&bpmp TEGRA194_CLK_APE>, 66 <&bpmp TEGRA194_CLK_APB2APE>; 67 clock-names = "ape", "apb2ape"; 68 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0x02900000 0x02900000 0x200000>; 72 status = "disabled"; 73 74 dma-controller@2930000 { 75 compatible = "nvidia,tegra194-adma", 76 "nvidia,tegra186-adma"; 77 reg = <0x02930000 0x20000>; 78 interrupt-parent = <&agic>; 79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 111 #dma-cells = <1>; 112 clocks = <&bpmp TEGRA194_CLK_AHUB>; 113 clock-names = "d_audio"; 114 status = "disabled"; 115 }; 116 117 agic: interrupt-controller@2a40000 { 118 compatible = "nvidia,tegra194-agic", 119 "nvidia,tegra210-agic"; 120 #interrupt-cells = <3>; 121 interrupt-controller; 122 reg = <0x02a41000 0x1000>, 123 <0x02a42000 0x2000>; 124 interrupts = <GIC_SPI 145 125 (GIC_CPU_MASK_SIMPLE(4) | 126 IRQ_TYPE_LEVEL_HIGH)>; 127 clocks = <&bpmp TEGRA194_CLK_APE>; 128 clock-names = "clk"; 129 status = "disabled"; 130 }; 131 }; 132 133 uarta: serial@3100000 { 134 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 135 reg = <0x03100000 0x40>; 136 reg-shift = <2>; 137 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&bpmp TEGRA194_CLK_UARTA>; 139 clock-names = "serial"; 140 resets = <&bpmp TEGRA194_RESET_UARTA>; 141 reset-names = "serial"; 142 status = "disabled"; 143 }; 144 145 uartb: serial@3110000 { 146 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 147 reg = <0x03110000 0x40>; 148 reg-shift = <2>; 149 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&bpmp TEGRA194_CLK_UARTB>; 151 clock-names = "serial"; 152 resets = <&bpmp TEGRA194_RESET_UARTB>; 153 reset-names = "serial"; 154 status = "disabled"; 155 }; 156 157 uartd: serial@3130000 { 158 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 159 reg = <0x03130000 0x40>; 160 reg-shift = <2>; 161 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&bpmp TEGRA194_CLK_UARTD>; 163 clock-names = "serial"; 164 resets = <&bpmp TEGRA194_RESET_UARTD>; 165 reset-names = "serial"; 166 status = "disabled"; 167 }; 168 169 uarte: serial@3140000 { 170 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 171 reg = <0x03140000 0x40>; 172 reg-shift = <2>; 173 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&bpmp TEGRA194_CLK_UARTE>; 175 clock-names = "serial"; 176 resets = <&bpmp TEGRA194_RESET_UARTE>; 177 reset-names = "serial"; 178 status = "disabled"; 179 }; 180 181 uartf: serial@3150000 { 182 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 183 reg = <0x03150000 0x40>; 184 reg-shift = <2>; 185 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&bpmp TEGRA194_CLK_UARTF>; 187 clock-names = "serial"; 188 resets = <&bpmp TEGRA194_RESET_UARTF>; 189 reset-names = "serial"; 190 status = "disabled"; 191 }; 192 193 gen1_i2c: i2c@3160000 { 194 compatible = "nvidia,tegra194-i2c"; 195 reg = <0x03160000 0x10000>; 196 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA194_CLK_I2C1>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA194_RESET_I2C1>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 uarth: serial@3170000 { 207 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 208 reg = <0x03170000 0x40>; 209 reg-shift = <2>; 210 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&bpmp TEGRA194_CLK_UARTH>; 212 clock-names = "serial"; 213 resets = <&bpmp TEGRA194_RESET_UARTH>; 214 reset-names = "serial"; 215 status = "disabled"; 216 }; 217 218 cam_i2c: i2c@3180000 { 219 compatible = "nvidia,tegra194-i2c"; 220 reg = <0x03180000 0x10000>; 221 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 clocks = <&bpmp TEGRA194_CLK_I2C3>; 225 clock-names = "div-clk"; 226 resets = <&bpmp TEGRA194_RESET_I2C3>; 227 reset-names = "i2c"; 228 status = "disabled"; 229 }; 230 231 /* shares pads with dpaux1 */ 232 dp_aux_ch1_i2c: i2c@3190000 { 233 compatible = "nvidia,tegra194-i2c"; 234 reg = <0x03190000 0x10000>; 235 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 clocks = <&bpmp TEGRA194_CLK_I2C4>; 239 clock-names = "div-clk"; 240 resets = <&bpmp TEGRA194_RESET_I2C4>; 241 reset-names = "i2c"; 242 status = "disabled"; 243 }; 244 245 /* shares pads with dpaux0 */ 246 dp_aux_ch0_i2c: i2c@31b0000 { 247 compatible = "nvidia,tegra194-i2c"; 248 reg = <0x031b0000 0x10000>; 249 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 clocks = <&bpmp TEGRA194_CLK_I2C6>; 253 clock-names = "div-clk"; 254 resets = <&bpmp TEGRA194_RESET_I2C6>; 255 reset-names = "i2c"; 256 status = "disabled"; 257 }; 258 259 gen7_i2c: i2c@31c0000 { 260 compatible = "nvidia,tegra194-i2c"; 261 reg = <0x031c0000 0x10000>; 262 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 clocks = <&bpmp TEGRA194_CLK_I2C7>; 266 clock-names = "div-clk"; 267 resets = <&bpmp TEGRA194_RESET_I2C7>; 268 reset-names = "i2c"; 269 status = "disabled"; 270 }; 271 272 gen9_i2c: i2c@31e0000 { 273 compatible = "nvidia,tegra194-i2c"; 274 reg = <0x031e0000 0x10000>; 275 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clocks = <&bpmp TEGRA194_CLK_I2C9>; 279 clock-names = "div-clk"; 280 resets = <&bpmp TEGRA194_RESET_I2C9>; 281 reset-names = "i2c"; 282 status = "disabled"; 283 }; 284 285 pwm1: pwm@3280000 { 286 compatible = "nvidia,tegra194-pwm", 287 "nvidia,tegra186-pwm"; 288 reg = <0x3280000 0x10000>; 289 clocks = <&bpmp TEGRA194_CLK_PWM1>; 290 clock-names = "pwm"; 291 resets = <&bpmp TEGRA194_RESET_PWM1>; 292 reset-names = "pwm"; 293 status = "disabled"; 294 #pwm-cells = <2>; 295 }; 296 297 pwm2: pwm@3290000 { 298 compatible = "nvidia,tegra194-pwm", 299 "nvidia,tegra186-pwm"; 300 reg = <0x3290000 0x10000>; 301 clocks = <&bpmp TEGRA194_CLK_PWM2>; 302 clock-names = "pwm"; 303 resets = <&bpmp TEGRA194_RESET_PWM2>; 304 reset-names = "pwm"; 305 status = "disabled"; 306 #pwm-cells = <2>; 307 }; 308 309 pwm3: pwm@32a0000 { 310 compatible = "nvidia,tegra194-pwm", 311 "nvidia,tegra186-pwm"; 312 reg = <0x32a0000 0x10000>; 313 clocks = <&bpmp TEGRA194_CLK_PWM3>; 314 clock-names = "pwm"; 315 resets = <&bpmp TEGRA194_RESET_PWM3>; 316 reset-names = "pwm"; 317 status = "disabled"; 318 #pwm-cells = <2>; 319 }; 320 321 pwm5: pwm@32c0000 { 322 compatible = "nvidia,tegra194-pwm", 323 "nvidia,tegra186-pwm"; 324 reg = <0x32c0000 0x10000>; 325 clocks = <&bpmp TEGRA194_CLK_PWM5>; 326 clock-names = "pwm"; 327 resets = <&bpmp TEGRA194_RESET_PWM5>; 328 reset-names = "pwm"; 329 status = "disabled"; 330 #pwm-cells = <2>; 331 }; 332 333 pwm6: pwm@32d0000 { 334 compatible = "nvidia,tegra194-pwm", 335 "nvidia,tegra186-pwm"; 336 reg = <0x32d0000 0x10000>; 337 clocks = <&bpmp TEGRA194_CLK_PWM6>; 338 clock-names = "pwm"; 339 resets = <&bpmp TEGRA194_RESET_PWM6>; 340 reset-names = "pwm"; 341 status = "disabled"; 342 #pwm-cells = <2>; 343 }; 344 345 pwm7: pwm@32e0000 { 346 compatible = "nvidia,tegra194-pwm", 347 "nvidia,tegra186-pwm"; 348 reg = <0x32e0000 0x10000>; 349 clocks = <&bpmp TEGRA194_CLK_PWM7>; 350 clock-names = "pwm"; 351 resets = <&bpmp TEGRA194_RESET_PWM7>; 352 reset-names = "pwm"; 353 status = "disabled"; 354 #pwm-cells = <2>; 355 }; 356 357 pwm8: pwm@32f0000 { 358 compatible = "nvidia,tegra194-pwm", 359 "nvidia,tegra186-pwm"; 360 reg = <0x32f0000 0x10000>; 361 clocks = <&bpmp TEGRA194_CLK_PWM8>; 362 clock-names = "pwm"; 363 resets = <&bpmp TEGRA194_RESET_PWM8>; 364 reset-names = "pwm"; 365 status = "disabled"; 366 #pwm-cells = <2>; 367 }; 368 369 sdmmc1: sdhci@3400000 { 370 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 371 reg = <0x03400000 0x10000>; 372 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 374 clock-names = "sdhci"; 375 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 376 reset-names = "sdhci"; 377 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 378 <0x07>; 379 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 380 <0x07>; 381 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 382 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 383 <0x07>; 384 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 385 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 386 nvidia,default-tap = <0x9>; 387 nvidia,default-trim = <0x5>; 388 status = "disabled"; 389 }; 390 391 sdmmc3: sdhci@3440000 { 392 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 393 reg = <0x03440000 0x10000>; 394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 396 clock-names = "sdhci"; 397 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 398 reset-names = "sdhci"; 399 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 400 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 401 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 402 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 403 <0x07>; 404 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 405 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 406 <0x07>; 407 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 408 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 409 nvidia,default-tap = <0x9>; 410 nvidia,default-trim = <0x5>; 411 status = "disabled"; 412 }; 413 414 sdmmc4: sdhci@3460000 { 415 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 416 reg = <0x03460000 0x10000>; 417 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 419 clock-names = "sdhci"; 420 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 421 <&bpmp TEGRA194_CLK_PLLC4>; 422 assigned-clock-parents = 423 <&bpmp TEGRA194_CLK_PLLC4>; 424 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 425 reset-names = "sdhci"; 426 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 427 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 428 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 429 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 430 <0x0a>; 431 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 432 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 433 <0x0a>; 434 nvidia,default-tap = <0x8>; 435 nvidia,default-trim = <0x14>; 436 nvidia,dqs-trim = <40>; 437 supports-cqe; 438 status = "disabled"; 439 }; 440 441 hda@3510000 { 442 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 443 reg = <0x3510000 0x10000>; 444 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&bpmp TEGRA194_CLK_HDA>, 446 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 447 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 448 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 449 resets = <&bpmp TEGRA194_RESET_HDA>, 450 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 451 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 452 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 453 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 454 status = "disabled"; 455 }; 456 457 gic: interrupt-controller@3881000 { 458 compatible = "arm,gic-400"; 459 #interrupt-cells = <3>; 460 interrupt-controller; 461 reg = <0x03881000 0x1000>, 462 <0x03882000 0x2000>, 463 <0x03884000 0x2000>, 464 <0x03886000 0x2000>; 465 interrupts = <GIC_PPI 9 466 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 467 interrupt-parent = <&gic>; 468 }; 469 470 cec@3960000 { 471 compatible = "nvidia,tegra194-cec"; 472 reg = <0x03960000 0x10000>; 473 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&bpmp TEGRA194_CLK_CEC>; 475 clock-names = "cec"; 476 status = "disabled"; 477 }; 478 479 hsp_top0: hsp@3c00000 { 480 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 481 reg = <0x03c00000 0xa0000>; 482 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 492 "shared3", "shared4", "shared5", "shared6", 493 "shared7"; 494 #mbox-cells = <2>; 495 }; 496 497 hsp_aon: hsp@c150000 { 498 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 499 reg = <0x0c150000 0xa0000>; 500 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 504 /* 505 * Shared interrupt 0 is routed only to AON/SPE, so 506 * we only have 4 shared interrupts for the CCPLEX. 507 */ 508 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 509 #mbox-cells = <2>; 510 }; 511 512 gen2_i2c: i2c@c240000 { 513 compatible = "nvidia,tegra194-i2c"; 514 reg = <0x0c240000 0x10000>; 515 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 clocks = <&bpmp TEGRA194_CLK_I2C2>; 519 clock-names = "div-clk"; 520 resets = <&bpmp TEGRA194_RESET_I2C2>; 521 reset-names = "i2c"; 522 status = "disabled"; 523 }; 524 525 gen8_i2c: i2c@c250000 { 526 compatible = "nvidia,tegra194-i2c"; 527 reg = <0x0c250000 0x10000>; 528 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&bpmp TEGRA194_CLK_I2C8>; 532 clock-names = "div-clk"; 533 resets = <&bpmp TEGRA194_RESET_I2C8>; 534 reset-names = "i2c"; 535 status = "disabled"; 536 }; 537 538 uartc: serial@c280000 { 539 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 540 reg = <0x0c280000 0x40>; 541 reg-shift = <2>; 542 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&bpmp TEGRA194_CLK_UARTC>; 544 clock-names = "serial"; 545 resets = <&bpmp TEGRA194_RESET_UARTC>; 546 reset-names = "serial"; 547 status = "disabled"; 548 }; 549 550 uartg: serial@c290000 { 551 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 552 reg = <0x0c290000 0x40>; 553 reg-shift = <2>; 554 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&bpmp TEGRA194_CLK_UARTG>; 556 clock-names = "serial"; 557 resets = <&bpmp TEGRA194_RESET_UARTG>; 558 reset-names = "serial"; 559 status = "disabled"; 560 }; 561 562 rtc: rtc@c2a0000 { 563 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 564 reg = <0x0c2a0000 0x10000>; 565 interrupt-parent = <&pmc>; 566 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 568 clock-names = "rtc"; 569 status = "disabled"; 570 }; 571 572 gpio_aon: gpio@c2f0000 { 573 compatible = "nvidia,tegra194-gpio-aon"; 574 reg-names = "security", "gpio"; 575 reg = <0xc2f0000 0x1000>, 576 <0xc2f1000 0x1000>; 577 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 587 pwm4: pwm@c340000 { 588 compatible = "nvidia,tegra194-pwm", 589 "nvidia,tegra186-pwm"; 590 reg = <0xc340000 0x10000>; 591 clocks = <&bpmp TEGRA194_CLK_PWM4>; 592 clock-names = "pwm"; 593 resets = <&bpmp TEGRA194_RESET_PWM4>; 594 reset-names = "pwm"; 595 status = "disabled"; 596 #pwm-cells = <2>; 597 }; 598 599 pmc: pmc@c360000 { 600 compatible = "nvidia,tegra194-pmc"; 601 reg = <0x0c360000 0x10000>, 602 <0x0c370000 0x10000>, 603 <0x0c380000 0x10000>, 604 <0x0c390000 0x10000>, 605 <0x0c3a0000 0x10000>; 606 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 607 608 #interrupt-cells = <2>; 609 interrupt-controller; 610 }; 611 612 host1x@13e00000 { 613 compatible = "nvidia,tegra194-host1x", "simple-bus"; 614 reg = <0x13e00000 0x10000>, 615 <0x13e10000 0x10000>; 616 reg-names = "hypervisor", "vm"; 617 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 620 clock-names = "host1x"; 621 resets = <&bpmp TEGRA194_RESET_HOST1X>; 622 reset-names = "host1x"; 623 624 #address-cells = <1>; 625 #size-cells = <1>; 626 627 ranges = <0x15000000 0x15000000 0x01000000>; 628 629 display-hub@15200000 { 630 compatible = "nvidia,tegra194-display", "simple-bus"; 631 reg = <0x15200000 0x00040000>; 632 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 633 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 634 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 635 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 636 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 637 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 638 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 639 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 640 "wgrp3", "wgrp4", "wgrp5"; 641 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 642 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 643 clock-names = "disp", "hub"; 644 status = "disabled"; 645 646 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 647 648 #address-cells = <1>; 649 #size-cells = <1>; 650 651 ranges = <0x15200000 0x15200000 0x40000>; 652 653 display@15200000 { 654 compatible = "nvidia,tegra194-dc"; 655 reg = <0x15200000 0x10000>; 656 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 658 clock-names = "dc"; 659 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 660 reset-names = "dc"; 661 662 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 663 664 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 665 nvidia,head = <0>; 666 }; 667 668 display@15210000 { 669 compatible = "nvidia,tegra194-dc"; 670 reg = <0x15210000 0x10000>; 671 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 673 clock-names = "dc"; 674 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 675 reset-names = "dc"; 676 677 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 678 679 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 680 nvidia,head = <1>; 681 }; 682 683 display@15220000 { 684 compatible = "nvidia,tegra194-dc"; 685 reg = <0x15220000 0x10000>; 686 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 688 clock-names = "dc"; 689 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 690 reset-names = "dc"; 691 692 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 693 694 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 695 nvidia,head = <2>; 696 }; 697 698 display@15230000 { 699 compatible = "nvidia,tegra194-dc"; 700 reg = <0x15230000 0x10000>; 701 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 703 clock-names = "dc"; 704 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 705 reset-names = "dc"; 706 707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 708 709 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 710 nvidia,head = <3>; 711 }; 712 }; 713 714 vic@15340000 { 715 compatible = "nvidia,tegra194-vic"; 716 reg = <0x15340000 0x00040000>; 717 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&bpmp TEGRA194_CLK_VIC>; 719 clock-names = "vic"; 720 resets = <&bpmp TEGRA194_RESET_VIC>; 721 reset-names = "vic"; 722 723 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 724 }; 725 726 dpaux0: dpaux@155c0000 { 727 compatible = "nvidia,tegra194-dpaux"; 728 reg = <0x155c0000 0x10000>; 729 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 731 <&bpmp TEGRA194_CLK_PLLDP>; 732 clock-names = "dpaux", "parent"; 733 resets = <&bpmp TEGRA194_RESET_DPAUX>; 734 reset-names = "dpaux"; 735 status = "disabled"; 736 737 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 738 739 state_dpaux0_aux: pinmux-aux { 740 groups = "dpaux-io"; 741 function = "aux"; 742 }; 743 744 state_dpaux0_i2c: pinmux-i2c { 745 groups = "dpaux-io"; 746 function = "i2c"; 747 }; 748 749 state_dpaux0_off: pinmux-off { 750 groups = "dpaux-io"; 751 function = "off"; 752 }; 753 754 i2c-bus { 755 #address-cells = <1>; 756 #size-cells = <0>; 757 }; 758 }; 759 760 dpaux1: dpaux@155d0000 { 761 compatible = "nvidia,tegra194-dpaux"; 762 reg = <0x155d0000 0x10000>; 763 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 765 <&bpmp TEGRA194_CLK_PLLDP>; 766 clock-names = "dpaux", "parent"; 767 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 768 reset-names = "dpaux"; 769 status = "disabled"; 770 771 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 772 773 state_dpaux1_aux: pinmux-aux { 774 groups = "dpaux-io"; 775 function = "aux"; 776 }; 777 778 state_dpaux1_i2c: pinmux-i2c { 779 groups = "dpaux-io"; 780 function = "i2c"; 781 }; 782 783 state_dpaux1_off: pinmux-off { 784 groups = "dpaux-io"; 785 function = "off"; 786 }; 787 788 i2c-bus { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 }; 792 }; 793 794 dpaux2: dpaux@155e0000 { 795 compatible = "nvidia,tegra194-dpaux"; 796 reg = <0x155e0000 0x10000>; 797 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 799 <&bpmp TEGRA194_CLK_PLLDP>; 800 clock-names = "dpaux", "parent"; 801 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 802 reset-names = "dpaux"; 803 status = "disabled"; 804 805 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 806 807 state_dpaux2_aux: pinmux-aux { 808 groups = "dpaux-io"; 809 function = "aux"; 810 }; 811 812 state_dpaux2_i2c: pinmux-i2c { 813 groups = "dpaux-io"; 814 function = "i2c"; 815 }; 816 817 state_dpaux2_off: pinmux-off { 818 groups = "dpaux-io"; 819 function = "off"; 820 }; 821 822 i2c-bus { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 }; 826 }; 827 828 dpaux3: dpaux@155f0000 { 829 compatible = "nvidia,tegra194-dpaux"; 830 reg = <0x155f0000 0x10000>; 831 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 833 <&bpmp TEGRA194_CLK_PLLDP>; 834 clock-names = "dpaux", "parent"; 835 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 836 reset-names = "dpaux"; 837 status = "disabled"; 838 839 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 840 841 state_dpaux3_aux: pinmux-aux { 842 groups = "dpaux-io"; 843 function = "aux"; 844 }; 845 846 state_dpaux3_i2c: pinmux-i2c { 847 groups = "dpaux-io"; 848 function = "i2c"; 849 }; 850 851 state_dpaux3_off: pinmux-off { 852 groups = "dpaux-io"; 853 function = "off"; 854 }; 855 856 i2c-bus { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 }; 860 }; 861 862 sor0: sor@15b00000 { 863 compatible = "nvidia,tegra194-sor"; 864 reg = <0x15b00000 0x40000>; 865 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 867 <&bpmp TEGRA194_CLK_SOR0_OUT>, 868 <&bpmp TEGRA194_CLK_PLLD>, 869 <&bpmp TEGRA194_CLK_PLLDP>, 870 <&bpmp TEGRA194_CLK_SOR_SAFE>, 871 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 872 clock-names = "sor", "out", "parent", "dp", "safe", 873 "pad"; 874 resets = <&bpmp TEGRA194_RESET_SOR0>; 875 reset-names = "sor"; 876 pinctrl-0 = <&state_dpaux0_aux>; 877 pinctrl-1 = <&state_dpaux0_i2c>; 878 pinctrl-2 = <&state_dpaux0_off>; 879 pinctrl-names = "aux", "i2c", "off"; 880 status = "disabled"; 881 882 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 883 nvidia,interface = <0>; 884 }; 885 886 sor1: sor@15b40000 { 887 compatible = "nvidia,tegra194-sor"; 888 reg = <0x155c0000 0x40000>; 889 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 891 <&bpmp TEGRA194_CLK_SOR1_OUT>, 892 <&bpmp TEGRA194_CLK_PLLD2>, 893 <&bpmp TEGRA194_CLK_PLLDP>, 894 <&bpmp TEGRA194_CLK_SOR_SAFE>, 895 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 896 clock-names = "sor", "out", "parent", "dp", "safe", 897 "pad"; 898 resets = <&bpmp TEGRA194_RESET_SOR1>; 899 reset-names = "sor"; 900 pinctrl-0 = <&state_dpaux1_aux>; 901 pinctrl-1 = <&state_dpaux1_i2c>; 902 pinctrl-2 = <&state_dpaux1_off>; 903 pinctrl-names = "aux", "i2c", "off"; 904 status = "disabled"; 905 906 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 907 nvidia,interface = <1>; 908 }; 909 910 sor2: sor@15b80000 { 911 compatible = "nvidia,tegra194-sor"; 912 reg = <0x15b80000 0x40000>; 913 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 915 <&bpmp TEGRA194_CLK_SOR2_OUT>, 916 <&bpmp TEGRA194_CLK_PLLD3>, 917 <&bpmp TEGRA194_CLK_PLLDP>, 918 <&bpmp TEGRA194_CLK_SOR_SAFE>, 919 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 920 clock-names = "sor", "out", "parent", "dp", "safe", 921 "pad"; 922 resets = <&bpmp TEGRA194_RESET_SOR2>; 923 reset-names = "sor"; 924 pinctrl-0 = <&state_dpaux2_aux>; 925 pinctrl-1 = <&state_dpaux2_i2c>; 926 pinctrl-2 = <&state_dpaux2_off>; 927 pinctrl-names = "aux", "i2c", "off"; 928 status = "disabled"; 929 930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 931 nvidia,interface = <2>; 932 }; 933 934 sor3: sor@15bc0000 { 935 compatible = "nvidia,tegra194-sor"; 936 reg = <0x15bc0000 0x40000>; 937 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 939 <&bpmp TEGRA194_CLK_SOR3_OUT>, 940 <&bpmp TEGRA194_CLK_PLLD4>, 941 <&bpmp TEGRA194_CLK_PLLDP>, 942 <&bpmp TEGRA194_CLK_SOR_SAFE>, 943 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 944 clock-names = "sor", "out", "parent", "dp", "safe", 945 "pad"; 946 resets = <&bpmp TEGRA194_RESET_SOR3>; 947 reset-names = "sor"; 948 pinctrl-0 = <&state_dpaux3_aux>; 949 pinctrl-1 = <&state_dpaux3_i2c>; 950 pinctrl-2 = <&state_dpaux3_off>; 951 pinctrl-names = "aux", "i2c", "off"; 952 status = "disabled"; 953 954 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 955 nvidia,interface = <3>; 956 }; 957 }; 958 }; 959 960 sysram@40000000 { 961 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 962 reg = <0x0 0x40000000 0x0 0x50000>; 963 #address-cells = <1>; 964 #size-cells = <1>; 965 ranges = <0x0 0x0 0x40000000 0x50000>; 966 967 cpu_bpmp_tx: shmem@4e000 { 968 compatible = "nvidia,tegra194-bpmp-shmem"; 969 reg = <0x4e000 0x1000>; 970 label = "cpu-bpmp-tx"; 971 pool; 972 }; 973 974 cpu_bpmp_rx: shmem@4f000 { 975 compatible = "nvidia,tegra194-bpmp-shmem"; 976 reg = <0x4f000 0x1000>; 977 label = "cpu-bpmp-rx"; 978 pool; 979 }; 980 }; 981 982 bpmp: bpmp { 983 compatible = "nvidia,tegra186-bpmp"; 984 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 985 TEGRA_HSP_DB_MASTER_BPMP>; 986 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 987 #clock-cells = <1>; 988 #reset-cells = <1>; 989 #power-domain-cells = <1>; 990 991 bpmp_i2c: i2c { 992 compatible = "nvidia,tegra186-bpmp-i2c"; 993 nvidia,bpmp-bus-id = <5>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 }; 997 998 bpmp_thermal: thermal { 999 compatible = "nvidia,tegra186-bpmp-thermal"; 1000 #thermal-sensor-cells = <1>; 1001 }; 1002 }; 1003 1004 cpus { 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 1008 cpu@0 { 1009 compatible = "nvidia,tegra194-carmel"; 1010 device_type = "cpu"; 1011 reg = <0x10000>; 1012 enable-method = "psci"; 1013 }; 1014 1015 cpu@1 { 1016 compatible = "nvidia,tegra194-carmel"; 1017 device_type = "cpu"; 1018 reg = <0x10001>; 1019 enable-method = "psci"; 1020 }; 1021 1022 cpu@2 { 1023 compatible = "nvidia,tegra194-carmel"; 1024 device_type = "cpu"; 1025 reg = <0x100>; 1026 enable-method = "psci"; 1027 }; 1028 1029 cpu@3 { 1030 compatible = "nvidia,tegra194-carmel"; 1031 device_type = "cpu"; 1032 reg = <0x101>; 1033 enable-method = "psci"; 1034 }; 1035 1036 cpu@4 { 1037 compatible = "nvidia,tegra194-carmel"; 1038 device_type = "cpu"; 1039 reg = <0x200>; 1040 enable-method = "psci"; 1041 }; 1042 1043 cpu@5 { 1044 compatible = "nvidia,tegra194-carmel"; 1045 device_type = "cpu"; 1046 reg = <0x201>; 1047 enable-method = "psci"; 1048 }; 1049 1050 cpu@6 { 1051 compatible = "nvidia,tegra194-carmel"; 1052 device_type = "cpu"; 1053 reg = <0x10300>; 1054 enable-method = "psci"; 1055 }; 1056 1057 cpu@7 { 1058 compatible = "nvidia,tegra194-carmel"; 1059 device_type = "cpu"; 1060 reg = <0x10301>; 1061 enable-method = "psci"; 1062 }; 1063 }; 1064 1065 psci { 1066 compatible = "arm,psci-1.0"; 1067 status = "okay"; 1068 method = "smc"; 1069 }; 1070 1071 tcu: tcu { 1072 compatible = "nvidia,tegra194-tcu"; 1073 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1074 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1075 mbox-names = "rx", "tx"; 1076 }; 1077 1078 thermal-zones { 1079 cpu { 1080 thermal-sensors = <&{/bpmp/thermal} 1081 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1082 status = "disabled"; 1083 }; 1084 1085 gpu { 1086 thermal-sensors = <&{/bpmp/thermal} 1087 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1088 status = "disabled"; 1089 }; 1090 1091 aux { 1092 thermal-sensors = <&{/bpmp/thermal} 1093 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1094 status = "disabled"; 1095 }; 1096 1097 pllx { 1098 thermal-sensors = <&{/bpmp/thermal} 1099 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1100 status = "disabled"; 1101 }; 1102 1103 ao { 1104 thermal-sensors = <&{/bpmp/thermal} 1105 TEGRA194_BPMP_THERMAL_ZONE_AO>; 1106 status = "disabled"; 1107 }; 1108 1109 tj { 1110 thermal-sensors = <&{/bpmp/thermal} 1111 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1112 status = "disabled"; 1113 }; 1114 }; 1115 1116 timer { 1117 compatible = "arm,armv8-timer"; 1118 interrupts = <GIC_PPI 13 1119 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1120 <GIC_PPI 14 1121 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1122 <GIC_PPI 11 1123 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1124 <GIC_PPI 10 1125 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1126 interrupt-parent = <&gic>; 1127 always-on; 1128 }; 1129}; 1130