1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@3881000 { 332 compatible = "arm,gic-400"; 333 #interrupt-cells = <3>; 334 interrupt-controller; 335 reg = <0x03881000 0x1000>, 336 <0x03882000 0x2000>, 337 <0x03884000 0x2000>, 338 <0x03886000 0x2000>; 339 interrupts = <GIC_PPI 9 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 341 interrupt-parent = <&gic>; 342 }; 343 344 hsp_top0: hsp@3c00000 { 345 compatible = "nvidia,tegra186-hsp"; 346 reg = <0x03c00000 0xa0000>; 347 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "doorbell"; 349 #mbox-cells = <2>; 350 }; 351 352 gen2_i2c: i2c@c240000 { 353 compatible = "nvidia,tegra194-i2c"; 354 reg = <0x0c240000 0x10000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&bpmp TEGRA194_CLK_I2C2>; 359 clock-names = "div-clk"; 360 resets = <&bpmp TEGRA194_RESET_I2C2>; 361 reset-names = "i2c"; 362 status = "disabled"; 363 }; 364 365 gen8_i2c: i2c@c250000 { 366 compatible = "nvidia,tegra194-i2c"; 367 reg = <0x0c250000 0x10000>; 368 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&bpmp TEGRA194_CLK_I2C8>; 372 clock-names = "div-clk"; 373 resets = <&bpmp TEGRA194_RESET_I2C8>; 374 reset-names = "i2c"; 375 status = "disabled"; 376 }; 377 378 uartc: serial@c280000 { 379 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 380 reg = <0x0c280000 0x40>; 381 reg-shift = <2>; 382 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&bpmp TEGRA194_CLK_UARTC>; 384 clock-names = "serial"; 385 resets = <&bpmp TEGRA194_RESET_UARTC>; 386 reset-names = "serial"; 387 status = "disabled"; 388 }; 389 390 uartg: serial@c290000 { 391 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 392 reg = <0x0c290000 0x40>; 393 reg-shift = <2>; 394 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA194_CLK_UARTG>; 396 clock-names = "serial"; 397 resets = <&bpmp TEGRA194_RESET_UARTG>; 398 reset-names = "serial"; 399 status = "disabled"; 400 }; 401 402 pwm4: pwm@c340000 { 403 compatible = "nvidia,tegra194-pwm", 404 "nvidia,tegra186-pwm"; 405 reg = <0xc340000 0x10000>; 406 clocks = <&bpmp TEGRA194_CLK_PWM4>; 407 clock-names = "pwm"; 408 resets = <&bpmp TEGRA194_RESET_PWM4>; 409 reset-names = "pwm"; 410 status = "disabled"; 411 #pwm-cells = <2>; 412 }; 413 414 pmc: pmc@c360000 { 415 compatible = "nvidia,tegra194-pmc"; 416 reg = <0x0c360000 0x10000>, 417 <0x0c370000 0x10000>, 418 <0x0c380000 0x10000>, 419 <0x0c390000 0x10000>, 420 <0x0c3a0000 0x10000>; 421 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 422 423 #interrupt-cells = <2>; 424 interrupt-controller; 425 }; 426 427 host1x@13e00000 { 428 compatible = "nvidia,tegra194-host1x", "simple-bus"; 429 reg = <0x13e00000 0x10000>, 430 <0x13e10000 0x10000>; 431 reg-names = "hypervisor", "vm"; 432 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 435 clock-names = "host1x"; 436 resets = <&bpmp TEGRA194_RESET_HOST1X>; 437 reset-names = "host1x"; 438 439 #address-cells = <1>; 440 #size-cells = <1>; 441 442 ranges = <0x15000000 0x15000000 0x01000000>; 443 444 display-hub@15200000 { 445 compatible = "nvidia,tegra194-display", "simple-bus"; 446 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 447 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 448 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 449 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 450 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 451 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 452 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 453 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 454 "wgrp3", "wgrp4", "wgrp5"; 455 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 456 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 457 clock-names = "disp", "hub"; 458 status = "disabled"; 459 460 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 461 462 #address-cells = <1>; 463 #size-cells = <1>; 464 465 ranges = <0x15200000 0x15200000 0x40000>; 466 467 display@15200000 { 468 compatible = "nvidia,tegra194-dc"; 469 reg = <0x15200000 0x10000>; 470 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 472 clock-names = "dc"; 473 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 474 reset-names = "dc"; 475 476 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 477 478 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 479 nvidia,head = <0>; 480 }; 481 482 display@15210000 { 483 compatible = "nvidia,tegra194-dc"; 484 reg = <0x15210000 0x10000>; 485 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 487 clock-names = "dc"; 488 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 489 reset-names = "dc"; 490 491 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 492 493 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 494 nvidia,head = <1>; 495 }; 496 497 display@15220000 { 498 compatible = "nvidia,tegra194-dc"; 499 reg = <0x15220000 0x10000>; 500 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 502 clock-names = "dc"; 503 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 504 reset-names = "dc"; 505 506 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 507 508 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 509 nvidia,head = <2>; 510 }; 511 512 display@15230000 { 513 compatible = "nvidia,tegra194-dc"; 514 reg = <0x15230000 0x10000>; 515 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 517 clock-names = "dc"; 518 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 519 reset-names = "dc"; 520 521 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 522 523 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 524 nvidia,head = <3>; 525 }; 526 }; 527 528 vic@15340000 { 529 compatible = "nvidia,tegra194-vic"; 530 reg = <0x15340000 0x00040000>; 531 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&bpmp TEGRA194_CLK_VIC>; 533 clock-names = "vic"; 534 resets = <&bpmp TEGRA194_RESET_VIC>; 535 reset-names = "vic"; 536 537 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 538 }; 539 540 dpaux0: dpaux@155c0000 { 541 compatible = "nvidia,tegra194-dpaux"; 542 reg = <0x155c0000 0x10000>; 543 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 545 <&bpmp TEGRA194_CLK_PLLDP>; 546 clock-names = "dpaux", "parent"; 547 resets = <&bpmp TEGRA194_RESET_DPAUX>; 548 reset-names = "dpaux"; 549 status = "disabled"; 550 551 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 552 553 state_dpaux0_aux: pinmux-aux { 554 groups = "dpaux-io"; 555 function = "aux"; 556 }; 557 558 state_dpaux0_i2c: pinmux-i2c { 559 groups = "dpaux-io"; 560 function = "i2c"; 561 }; 562 563 state_dpaux0_off: pinmux-off { 564 groups = "dpaux-io"; 565 function = "off"; 566 }; 567 568 i2c-bus { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 }; 572 }; 573 574 dpaux1: dpaux@155d0000 { 575 compatible = "nvidia,tegra194-dpaux"; 576 reg = <0x155d0000 0x10000>; 577 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 579 <&bpmp TEGRA194_CLK_PLLDP>; 580 clock-names = "dpaux", "parent"; 581 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 582 reset-names = "dpaux"; 583 status = "disabled"; 584 585 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 586 587 state_dpaux1_aux: pinmux-aux { 588 groups = "dpaux-io"; 589 function = "aux"; 590 }; 591 592 state_dpaux1_i2c: pinmux-i2c { 593 groups = "dpaux-io"; 594 function = "i2c"; 595 }; 596 597 state_dpaux1_off: pinmux-off { 598 groups = "dpaux-io"; 599 function = "off"; 600 }; 601 602 i2c-bus { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 }; 606 }; 607 608 dpaux2: dpaux@155e0000 { 609 compatible = "nvidia,tegra194-dpaux"; 610 reg = <0x155e0000 0x10000>; 611 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 613 <&bpmp TEGRA194_CLK_PLLDP>; 614 clock-names = "dpaux", "parent"; 615 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 616 reset-names = "dpaux"; 617 status = "disabled"; 618 619 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 620 621 state_dpaux2_aux: pinmux-aux { 622 groups = "dpaux-io"; 623 function = "aux"; 624 }; 625 626 state_dpaux2_i2c: pinmux-i2c { 627 groups = "dpaux-io"; 628 function = "i2c"; 629 }; 630 631 state_dpaux2_off: pinmux-off { 632 groups = "dpaux-io"; 633 function = "off"; 634 }; 635 636 i2c-bus { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 }; 640 }; 641 642 dpaux3: dpaux@155f0000 { 643 compatible = "nvidia,tegra194-dpaux"; 644 reg = <0x155f0000 0x10000>; 645 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 647 <&bpmp TEGRA194_CLK_PLLDP>; 648 clock-names = "dpaux", "parent"; 649 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 650 reset-names = "dpaux"; 651 status = "disabled"; 652 653 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 654 655 state_dpaux3_aux: pinmux-aux { 656 groups = "dpaux-io"; 657 function = "aux"; 658 }; 659 660 state_dpaux3_i2c: pinmux-i2c { 661 groups = "dpaux-io"; 662 function = "i2c"; 663 }; 664 665 state_dpaux3_off: pinmux-off { 666 groups = "dpaux-io"; 667 function = "off"; 668 }; 669 670 i2c-bus { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 }; 674 }; 675 676 sor0: sor@15b00000 { 677 compatible = "nvidia,tegra194-sor"; 678 reg = <0x15b00000 0x40000>; 679 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 681 <&bpmp TEGRA194_CLK_SOR0_OUT>, 682 <&bpmp TEGRA194_CLK_PLLD>, 683 <&bpmp TEGRA194_CLK_PLLDP>, 684 <&bpmp TEGRA194_CLK_SOR_SAFE>, 685 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 686 clock-names = "sor", "out", "parent", "dp", "safe", 687 "pad"; 688 resets = <&bpmp TEGRA194_RESET_SOR0>; 689 reset-names = "sor"; 690 pinctrl-0 = <&state_dpaux0_aux>; 691 pinctrl-1 = <&state_dpaux0_i2c>; 692 pinctrl-2 = <&state_dpaux0_off>; 693 pinctrl-names = "aux", "i2c", "off"; 694 status = "disabled"; 695 696 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 697 nvidia,interface = <0>; 698 }; 699 700 sor1: sor@15b40000 { 701 compatible = "nvidia,tegra194-sor"; 702 reg = <0x155c0000 0x40000>; 703 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 705 <&bpmp TEGRA194_CLK_SOR1_OUT>, 706 <&bpmp TEGRA194_CLK_PLLD2>, 707 <&bpmp TEGRA194_CLK_PLLDP>, 708 <&bpmp TEGRA194_CLK_SOR_SAFE>, 709 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 710 clock-names = "sor", "out", "parent", "dp", "safe", 711 "pad"; 712 resets = <&bpmp TEGRA194_RESET_SOR1>; 713 reset-names = "sor"; 714 pinctrl-0 = <&state_dpaux1_aux>; 715 pinctrl-1 = <&state_dpaux1_i2c>; 716 pinctrl-2 = <&state_dpaux1_off>; 717 pinctrl-names = "aux", "i2c", "off"; 718 status = "disabled"; 719 720 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 721 nvidia,interface = <1>; 722 }; 723 724 sor2: sor@15b80000 { 725 compatible = "nvidia,tegra194-sor"; 726 reg = <0x15b80000 0x40000>; 727 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 729 <&bpmp TEGRA194_CLK_SOR2_OUT>, 730 <&bpmp TEGRA194_CLK_PLLD3>, 731 <&bpmp TEGRA194_CLK_PLLDP>, 732 <&bpmp TEGRA194_CLK_SOR_SAFE>, 733 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 734 clock-names = "sor", "out", "parent", "dp", "safe", 735 "pad"; 736 resets = <&bpmp TEGRA194_RESET_SOR2>; 737 reset-names = "sor"; 738 pinctrl-0 = <&state_dpaux2_aux>; 739 pinctrl-1 = <&state_dpaux2_i2c>; 740 pinctrl-2 = <&state_dpaux2_off>; 741 pinctrl-names = "aux", "i2c", "off"; 742 status = "disabled"; 743 744 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 745 nvidia,interface = <2>; 746 }; 747 748 sor3: sor@15bc0000 { 749 compatible = "nvidia,tegra194-sor"; 750 reg = <0x15bc0000 0x40000>; 751 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 753 <&bpmp TEGRA194_CLK_SOR3_OUT>, 754 <&bpmp TEGRA194_CLK_PLLD4>, 755 <&bpmp TEGRA194_CLK_PLLDP>, 756 <&bpmp TEGRA194_CLK_SOR_SAFE>, 757 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 758 clock-names = "sor", "out", "parent", "dp", "safe", 759 "pad"; 760 resets = <&bpmp TEGRA194_RESET_SOR3>; 761 reset-names = "sor"; 762 pinctrl-0 = <&state_dpaux3_aux>; 763 pinctrl-1 = <&state_dpaux3_i2c>; 764 pinctrl-2 = <&state_dpaux3_off>; 765 pinctrl-names = "aux", "i2c", "off"; 766 status = "disabled"; 767 768 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 769 nvidia,interface = <3>; 770 }; 771 }; 772 }; 773 774 sysram@40000000 { 775 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 776 reg = <0x0 0x40000000 0x0 0x50000>; 777 #address-cells = <1>; 778 #size-cells = <1>; 779 ranges = <0x0 0x0 0x40000000 0x50000>; 780 781 cpu_bpmp_tx: shmem@4e000 { 782 compatible = "nvidia,tegra194-bpmp-shmem"; 783 reg = <0x4e000 0x1000>; 784 label = "cpu-bpmp-tx"; 785 pool; 786 }; 787 788 cpu_bpmp_rx: shmem@4f000 { 789 compatible = "nvidia,tegra194-bpmp-shmem"; 790 reg = <0x4f000 0x1000>; 791 label = "cpu-bpmp-rx"; 792 pool; 793 }; 794 }; 795 796 bpmp: bpmp { 797 compatible = "nvidia,tegra186-bpmp"; 798 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 799 TEGRA_HSP_DB_MASTER_BPMP>; 800 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 801 #clock-cells = <1>; 802 #reset-cells = <1>; 803 #power-domain-cells = <1>; 804 805 bpmp_i2c: i2c { 806 compatible = "nvidia,tegra186-bpmp-i2c"; 807 nvidia,bpmp-bus-id = <5>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 }; 811 812 bpmp_thermal: thermal { 813 compatible = "nvidia,tegra186-bpmp-thermal"; 814 #thermal-sensor-cells = <1>; 815 }; 816 }; 817 818 cpus { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 822 cpu@0 { 823 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 824 device_type = "cpu"; 825 reg = <0x10000>; 826 enable-method = "psci"; 827 }; 828 829 cpu@1 { 830 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 831 device_type = "cpu"; 832 reg = <0x10001>; 833 enable-method = "psci"; 834 }; 835 836 cpu@2 { 837 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 838 device_type = "cpu"; 839 reg = <0x100>; 840 enable-method = "psci"; 841 }; 842 843 cpu@3 { 844 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 845 device_type = "cpu"; 846 reg = <0x101>; 847 enable-method = "psci"; 848 }; 849 850 cpu@4 { 851 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 852 device_type = "cpu"; 853 reg = <0x200>; 854 enable-method = "psci"; 855 }; 856 857 cpu@5 { 858 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 859 device_type = "cpu"; 860 reg = <0x201>; 861 enable-method = "psci"; 862 }; 863 864 cpu@6 { 865 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 866 device_type = "cpu"; 867 reg = <0x10300>; 868 enable-method = "psci"; 869 }; 870 871 cpu@7 { 872 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 873 device_type = "cpu"; 874 reg = <0x10301>; 875 enable-method = "psci"; 876 }; 877 }; 878 879 psci { 880 compatible = "arm,psci-1.0"; 881 status = "okay"; 882 method = "smc"; 883 }; 884 885 thermal-zones { 886 cpu { 887 thermal-sensors = <&{/bpmp/thermal} 888 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 889 status = "disabled"; 890 }; 891 892 gpu { 893 thermal-sensors = <&{/bpmp/thermal} 894 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 895 status = "disabled"; 896 }; 897 898 aux { 899 thermal-sensors = <&{/bpmp/thermal} 900 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 901 status = "disabled"; 902 }; 903 904 pllx { 905 thermal-sensors = <&{/bpmp/thermal} 906 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 907 status = "disabled"; 908 }; 909 910 ao { 911 thermal-sensors = <&{/bpmp/thermal} 912 TEGRA194_BPMP_THERMAL_ZONE_AO>; 913 status = "disabled"; 914 }; 915 916 tj { 917 thermal-sensors = <&{/bpmp/thermal} 918 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 919 status = "disabled"; 920 }; 921 }; 922 923 timer { 924 compatible = "arm,armv8-timer"; 925 interrupts = <GIC_PPI 13 926 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 927 <GIC_PPI 14 928 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 929 <GIC_PPI 11 930 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 931 <GIC_PPI 10 932 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 933 interrupt-parent = <&gic>; 934 }; 935}; 936