1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@3881000 { 332 compatible = "arm,gic-400"; 333 #interrupt-cells = <3>; 334 interrupt-controller; 335 reg = <0x03881000 0x1000>, 336 <0x03882000 0x2000>, 337 <0x03884000 0x2000>, 338 <0x03886000 0x2000>; 339 interrupts = <GIC_PPI 9 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 341 interrupt-parent = <&gic>; 342 }; 343 344 hsp_top0: hsp@3c00000 { 345 compatible = "nvidia,tegra186-hsp"; 346 reg = <0x03c00000 0xa0000>; 347 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "doorbell"; 349 #mbox-cells = <2>; 350 }; 351 352 gen2_i2c: i2c@c240000 { 353 compatible = "nvidia,tegra194-i2c"; 354 reg = <0x0c240000 0x10000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&bpmp TEGRA194_CLK_I2C2>; 359 clock-names = "div-clk"; 360 resets = <&bpmp TEGRA194_RESET_I2C2>; 361 reset-names = "i2c"; 362 status = "disabled"; 363 }; 364 365 gen8_i2c: i2c@c250000 { 366 compatible = "nvidia,tegra194-i2c"; 367 reg = <0x0c250000 0x10000>; 368 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&bpmp TEGRA194_CLK_I2C8>; 372 clock-names = "div-clk"; 373 resets = <&bpmp TEGRA194_RESET_I2C8>; 374 reset-names = "i2c"; 375 status = "disabled"; 376 }; 377 378 uartc: serial@c280000 { 379 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 380 reg = <0x0c280000 0x40>; 381 reg-shift = <2>; 382 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&bpmp TEGRA194_CLK_UARTC>; 384 clock-names = "serial"; 385 resets = <&bpmp TEGRA194_RESET_UARTC>; 386 reset-names = "serial"; 387 status = "disabled"; 388 }; 389 390 uartg: serial@c290000 { 391 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 392 reg = <0x0c290000 0x40>; 393 reg-shift = <2>; 394 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA194_CLK_UARTG>; 396 clock-names = "serial"; 397 resets = <&bpmp TEGRA194_RESET_UARTG>; 398 reset-names = "serial"; 399 status = "disabled"; 400 }; 401 402 rtc: rtc@c2a0000 { 403 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 404 reg = <0x0c2a0000 0x10000>; 405 interrupt-parent = <&pmc>; 406 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 408 clock-names = "rtc"; 409 status = "disabled"; 410 }; 411 412 gpio_aon: gpio@c2f0000 { 413 compatible = "nvidia,tegra194-gpio-aon"; 414 reg-names = "security", "gpio"; 415 reg = <0xc2f0000 0x1000>, 416 <0xc2f1000 0x1000>; 417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 }; 426 427 pwm4: pwm@c340000 { 428 compatible = "nvidia,tegra194-pwm", 429 "nvidia,tegra186-pwm"; 430 reg = <0xc340000 0x10000>; 431 clocks = <&bpmp TEGRA194_CLK_PWM4>; 432 clock-names = "pwm"; 433 resets = <&bpmp TEGRA194_RESET_PWM4>; 434 reset-names = "pwm"; 435 status = "disabled"; 436 #pwm-cells = <2>; 437 }; 438 439 pmc: pmc@c360000 { 440 compatible = "nvidia,tegra194-pmc"; 441 reg = <0x0c360000 0x10000>, 442 <0x0c370000 0x10000>, 443 <0x0c380000 0x10000>, 444 <0x0c390000 0x10000>, 445 <0x0c3a0000 0x10000>; 446 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 447 448 #interrupt-cells = <2>; 449 interrupt-controller; 450 }; 451 452 host1x@13e00000 { 453 compatible = "nvidia,tegra194-host1x", "simple-bus"; 454 reg = <0x13e00000 0x10000>, 455 <0x13e10000 0x10000>; 456 reg-names = "hypervisor", "vm"; 457 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 460 clock-names = "host1x"; 461 resets = <&bpmp TEGRA194_RESET_HOST1X>; 462 reset-names = "host1x"; 463 464 #address-cells = <1>; 465 #size-cells = <1>; 466 467 ranges = <0x15000000 0x15000000 0x01000000>; 468 469 display-hub@15200000 { 470 compatible = "nvidia,tegra194-display", "simple-bus"; 471 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 472 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 473 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 474 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 475 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 476 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 477 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 478 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 479 "wgrp3", "wgrp4", "wgrp5"; 480 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 481 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 482 clock-names = "disp", "hub"; 483 status = "disabled"; 484 485 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 486 487 #address-cells = <1>; 488 #size-cells = <1>; 489 490 ranges = <0x15200000 0x15200000 0x40000>; 491 492 display@15200000 { 493 compatible = "nvidia,tegra194-dc"; 494 reg = <0x15200000 0x10000>; 495 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 497 clock-names = "dc"; 498 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 499 reset-names = "dc"; 500 501 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 502 503 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 504 nvidia,head = <0>; 505 }; 506 507 display@15210000 { 508 compatible = "nvidia,tegra194-dc"; 509 reg = <0x15210000 0x10000>; 510 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 512 clock-names = "dc"; 513 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 514 reset-names = "dc"; 515 516 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 517 518 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 519 nvidia,head = <1>; 520 }; 521 522 display@15220000 { 523 compatible = "nvidia,tegra194-dc"; 524 reg = <0x15220000 0x10000>; 525 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 527 clock-names = "dc"; 528 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 529 reset-names = "dc"; 530 531 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 532 533 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 534 nvidia,head = <2>; 535 }; 536 537 display@15230000 { 538 compatible = "nvidia,tegra194-dc"; 539 reg = <0x15230000 0x10000>; 540 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 542 clock-names = "dc"; 543 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 544 reset-names = "dc"; 545 546 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 547 548 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 549 nvidia,head = <3>; 550 }; 551 }; 552 553 vic@15340000 { 554 compatible = "nvidia,tegra194-vic"; 555 reg = <0x15340000 0x00040000>; 556 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&bpmp TEGRA194_CLK_VIC>; 558 clock-names = "vic"; 559 resets = <&bpmp TEGRA194_RESET_VIC>; 560 reset-names = "vic"; 561 562 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 563 }; 564 565 dpaux0: dpaux@155c0000 { 566 compatible = "nvidia,tegra194-dpaux"; 567 reg = <0x155c0000 0x10000>; 568 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 570 <&bpmp TEGRA194_CLK_PLLDP>; 571 clock-names = "dpaux", "parent"; 572 resets = <&bpmp TEGRA194_RESET_DPAUX>; 573 reset-names = "dpaux"; 574 status = "disabled"; 575 576 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 577 578 state_dpaux0_aux: pinmux-aux { 579 groups = "dpaux-io"; 580 function = "aux"; 581 }; 582 583 state_dpaux0_i2c: pinmux-i2c { 584 groups = "dpaux-io"; 585 function = "i2c"; 586 }; 587 588 state_dpaux0_off: pinmux-off { 589 groups = "dpaux-io"; 590 function = "off"; 591 }; 592 593 i2c-bus { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 }; 597 }; 598 599 dpaux1: dpaux@155d0000 { 600 compatible = "nvidia,tegra194-dpaux"; 601 reg = <0x155d0000 0x10000>; 602 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 604 <&bpmp TEGRA194_CLK_PLLDP>; 605 clock-names = "dpaux", "parent"; 606 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 607 reset-names = "dpaux"; 608 status = "disabled"; 609 610 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 611 612 state_dpaux1_aux: pinmux-aux { 613 groups = "dpaux-io"; 614 function = "aux"; 615 }; 616 617 state_dpaux1_i2c: pinmux-i2c { 618 groups = "dpaux-io"; 619 function = "i2c"; 620 }; 621 622 state_dpaux1_off: pinmux-off { 623 groups = "dpaux-io"; 624 function = "off"; 625 }; 626 627 i2c-bus { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 }; 631 }; 632 633 dpaux2: dpaux@155e0000 { 634 compatible = "nvidia,tegra194-dpaux"; 635 reg = <0x155e0000 0x10000>; 636 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 638 <&bpmp TEGRA194_CLK_PLLDP>; 639 clock-names = "dpaux", "parent"; 640 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 641 reset-names = "dpaux"; 642 status = "disabled"; 643 644 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 645 646 state_dpaux2_aux: pinmux-aux { 647 groups = "dpaux-io"; 648 function = "aux"; 649 }; 650 651 state_dpaux2_i2c: pinmux-i2c { 652 groups = "dpaux-io"; 653 function = "i2c"; 654 }; 655 656 state_dpaux2_off: pinmux-off { 657 groups = "dpaux-io"; 658 function = "off"; 659 }; 660 661 i2c-bus { 662 #address-cells = <1>; 663 #size-cells = <0>; 664 }; 665 }; 666 667 dpaux3: dpaux@155f0000 { 668 compatible = "nvidia,tegra194-dpaux"; 669 reg = <0x155f0000 0x10000>; 670 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 672 <&bpmp TEGRA194_CLK_PLLDP>; 673 clock-names = "dpaux", "parent"; 674 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 675 reset-names = "dpaux"; 676 status = "disabled"; 677 678 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 679 680 state_dpaux3_aux: pinmux-aux { 681 groups = "dpaux-io"; 682 function = "aux"; 683 }; 684 685 state_dpaux3_i2c: pinmux-i2c { 686 groups = "dpaux-io"; 687 function = "i2c"; 688 }; 689 690 state_dpaux3_off: pinmux-off { 691 groups = "dpaux-io"; 692 function = "off"; 693 }; 694 695 i2c-bus { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 }; 699 }; 700 701 sor0: sor@15b00000 { 702 compatible = "nvidia,tegra194-sor"; 703 reg = <0x15b00000 0x40000>; 704 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 706 <&bpmp TEGRA194_CLK_SOR0_OUT>, 707 <&bpmp TEGRA194_CLK_PLLD>, 708 <&bpmp TEGRA194_CLK_PLLDP>, 709 <&bpmp TEGRA194_CLK_SOR_SAFE>, 710 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 711 clock-names = "sor", "out", "parent", "dp", "safe", 712 "pad"; 713 resets = <&bpmp TEGRA194_RESET_SOR0>; 714 reset-names = "sor"; 715 pinctrl-0 = <&state_dpaux0_aux>; 716 pinctrl-1 = <&state_dpaux0_i2c>; 717 pinctrl-2 = <&state_dpaux0_off>; 718 pinctrl-names = "aux", "i2c", "off"; 719 status = "disabled"; 720 721 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 722 nvidia,interface = <0>; 723 }; 724 725 sor1: sor@15b40000 { 726 compatible = "nvidia,tegra194-sor"; 727 reg = <0x155c0000 0x40000>; 728 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 730 <&bpmp TEGRA194_CLK_SOR1_OUT>, 731 <&bpmp TEGRA194_CLK_PLLD2>, 732 <&bpmp TEGRA194_CLK_PLLDP>, 733 <&bpmp TEGRA194_CLK_SOR_SAFE>, 734 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 735 clock-names = "sor", "out", "parent", "dp", "safe", 736 "pad"; 737 resets = <&bpmp TEGRA194_RESET_SOR1>; 738 reset-names = "sor"; 739 pinctrl-0 = <&state_dpaux1_aux>; 740 pinctrl-1 = <&state_dpaux1_i2c>; 741 pinctrl-2 = <&state_dpaux1_off>; 742 pinctrl-names = "aux", "i2c", "off"; 743 status = "disabled"; 744 745 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 746 nvidia,interface = <1>; 747 }; 748 749 sor2: sor@15b80000 { 750 compatible = "nvidia,tegra194-sor"; 751 reg = <0x15b80000 0x40000>; 752 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 754 <&bpmp TEGRA194_CLK_SOR2_OUT>, 755 <&bpmp TEGRA194_CLK_PLLD3>, 756 <&bpmp TEGRA194_CLK_PLLDP>, 757 <&bpmp TEGRA194_CLK_SOR_SAFE>, 758 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 759 clock-names = "sor", "out", "parent", "dp", "safe", 760 "pad"; 761 resets = <&bpmp TEGRA194_RESET_SOR2>; 762 reset-names = "sor"; 763 pinctrl-0 = <&state_dpaux2_aux>; 764 pinctrl-1 = <&state_dpaux2_i2c>; 765 pinctrl-2 = <&state_dpaux2_off>; 766 pinctrl-names = "aux", "i2c", "off"; 767 status = "disabled"; 768 769 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 770 nvidia,interface = <2>; 771 }; 772 773 sor3: sor@15bc0000 { 774 compatible = "nvidia,tegra194-sor"; 775 reg = <0x15bc0000 0x40000>; 776 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 778 <&bpmp TEGRA194_CLK_SOR3_OUT>, 779 <&bpmp TEGRA194_CLK_PLLD4>, 780 <&bpmp TEGRA194_CLK_PLLDP>, 781 <&bpmp TEGRA194_CLK_SOR_SAFE>, 782 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 783 clock-names = "sor", "out", "parent", "dp", "safe", 784 "pad"; 785 resets = <&bpmp TEGRA194_RESET_SOR3>; 786 reset-names = "sor"; 787 pinctrl-0 = <&state_dpaux3_aux>; 788 pinctrl-1 = <&state_dpaux3_i2c>; 789 pinctrl-2 = <&state_dpaux3_off>; 790 pinctrl-names = "aux", "i2c", "off"; 791 status = "disabled"; 792 793 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 794 nvidia,interface = <3>; 795 }; 796 }; 797 }; 798 799 sysram@40000000 { 800 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 801 reg = <0x0 0x40000000 0x0 0x50000>; 802 #address-cells = <1>; 803 #size-cells = <1>; 804 ranges = <0x0 0x0 0x40000000 0x50000>; 805 806 cpu_bpmp_tx: shmem@4e000 { 807 compatible = "nvidia,tegra194-bpmp-shmem"; 808 reg = <0x4e000 0x1000>; 809 label = "cpu-bpmp-tx"; 810 pool; 811 }; 812 813 cpu_bpmp_rx: shmem@4f000 { 814 compatible = "nvidia,tegra194-bpmp-shmem"; 815 reg = <0x4f000 0x1000>; 816 label = "cpu-bpmp-rx"; 817 pool; 818 }; 819 }; 820 821 bpmp: bpmp { 822 compatible = "nvidia,tegra186-bpmp"; 823 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 824 TEGRA_HSP_DB_MASTER_BPMP>; 825 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 826 #clock-cells = <1>; 827 #reset-cells = <1>; 828 #power-domain-cells = <1>; 829 830 bpmp_i2c: i2c { 831 compatible = "nvidia,tegra186-bpmp-i2c"; 832 nvidia,bpmp-bus-id = <5>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 }; 836 837 bpmp_thermal: thermal { 838 compatible = "nvidia,tegra186-bpmp-thermal"; 839 #thermal-sensor-cells = <1>; 840 }; 841 }; 842 843 cpus { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 847 cpu@0 { 848 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 849 device_type = "cpu"; 850 reg = <0x10000>; 851 enable-method = "psci"; 852 }; 853 854 cpu@1 { 855 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 856 device_type = "cpu"; 857 reg = <0x10001>; 858 enable-method = "psci"; 859 }; 860 861 cpu@2 { 862 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 863 device_type = "cpu"; 864 reg = <0x100>; 865 enable-method = "psci"; 866 }; 867 868 cpu@3 { 869 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 870 device_type = "cpu"; 871 reg = <0x101>; 872 enable-method = "psci"; 873 }; 874 875 cpu@4 { 876 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 877 device_type = "cpu"; 878 reg = <0x200>; 879 enable-method = "psci"; 880 }; 881 882 cpu@5 { 883 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 884 device_type = "cpu"; 885 reg = <0x201>; 886 enable-method = "psci"; 887 }; 888 889 cpu@6 { 890 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 891 device_type = "cpu"; 892 reg = <0x10300>; 893 enable-method = "psci"; 894 }; 895 896 cpu@7 { 897 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 898 device_type = "cpu"; 899 reg = <0x10301>; 900 enable-method = "psci"; 901 }; 902 }; 903 904 psci { 905 compatible = "arm,psci-1.0"; 906 status = "okay"; 907 method = "smc"; 908 }; 909 910 thermal-zones { 911 cpu { 912 thermal-sensors = <&{/bpmp/thermal} 913 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 914 status = "disabled"; 915 }; 916 917 gpu { 918 thermal-sensors = <&{/bpmp/thermal} 919 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 920 status = "disabled"; 921 }; 922 923 aux { 924 thermal-sensors = <&{/bpmp/thermal} 925 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 926 status = "disabled"; 927 }; 928 929 pllx { 930 thermal-sensors = <&{/bpmp/thermal} 931 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 932 status = "disabled"; 933 }; 934 935 ao { 936 thermal-sensors = <&{/bpmp/thermal} 937 TEGRA194_BPMP_THERMAL_ZONE_AO>; 938 status = "disabled"; 939 }; 940 941 tj { 942 thermal-sensors = <&{/bpmp/thermal} 943 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 944 status = "disabled"; 945 }; 946 }; 947 948 timer { 949 compatible = "arm,armv8-timer"; 950 interrupts = <GIC_PPI 13 951 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 952 <GIC_PPI 14 953 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 954 <GIC_PPI 11 955 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 956 <GIC_PPI 10 957 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 958 interrupt-parent = <&gic>; 959 }; 960}; 961