1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 hda@3510000 { 332 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 333 reg = <0x3510000 0x10000>; 334 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&bpmp TEGRA194_CLK_HDA>, 336 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 337 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 338 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 339 resets = <&bpmp TEGRA194_RESET_HDA>, 340 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 341 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 342 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 343 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 344 status = "disabled"; 345 }; 346 347 gic: interrupt-controller@3881000 { 348 compatible = "arm,gic-400"; 349 #interrupt-cells = <3>; 350 interrupt-controller; 351 reg = <0x03881000 0x1000>, 352 <0x03882000 0x2000>, 353 <0x03884000 0x2000>, 354 <0x03886000 0x2000>; 355 interrupts = <GIC_PPI 9 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 357 interrupt-parent = <&gic>; 358 }; 359 360 cec@3960000 { 361 compatible = "nvidia,tegra194-cec"; 362 reg = <0x03960000 0x10000>; 363 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&bpmp TEGRA194_CLK_CEC>; 365 clock-names = "cec"; 366 status = "disabled"; 367 }; 368 369 hsp_top0: hsp@3c00000 { 370 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 371 reg = <0x03c00000 0xa0000>; 372 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 382 "shared3", "shared4", "shared5", "shared6", 383 "shared7"; 384 #mbox-cells = <2>; 385 }; 386 387 hsp_aon: hsp@c150000 { 388 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 389 reg = <0x0c150000 0xa0000>; 390 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 394 /* 395 * Shared interrupt 0 is routed only to AON/SPE, so 396 * we only have 4 shared interrupts for the CCPLEX. 397 */ 398 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 399 #mbox-cells = <2>; 400 }; 401 402 gen2_i2c: i2c@c240000 { 403 compatible = "nvidia,tegra194-i2c"; 404 reg = <0x0c240000 0x10000>; 405 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clocks = <&bpmp TEGRA194_CLK_I2C2>; 409 clock-names = "div-clk"; 410 resets = <&bpmp TEGRA194_RESET_I2C2>; 411 reset-names = "i2c"; 412 status = "disabled"; 413 }; 414 415 gen8_i2c: i2c@c250000 { 416 compatible = "nvidia,tegra194-i2c"; 417 reg = <0x0c250000 0x10000>; 418 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clocks = <&bpmp TEGRA194_CLK_I2C8>; 422 clock-names = "div-clk"; 423 resets = <&bpmp TEGRA194_RESET_I2C8>; 424 reset-names = "i2c"; 425 status = "disabled"; 426 }; 427 428 uartc: serial@c280000 { 429 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 430 reg = <0x0c280000 0x40>; 431 reg-shift = <2>; 432 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&bpmp TEGRA194_CLK_UARTC>; 434 clock-names = "serial"; 435 resets = <&bpmp TEGRA194_RESET_UARTC>; 436 reset-names = "serial"; 437 status = "disabled"; 438 }; 439 440 uartg: serial@c290000 { 441 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 442 reg = <0x0c290000 0x40>; 443 reg-shift = <2>; 444 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&bpmp TEGRA194_CLK_UARTG>; 446 clock-names = "serial"; 447 resets = <&bpmp TEGRA194_RESET_UARTG>; 448 reset-names = "serial"; 449 status = "disabled"; 450 }; 451 452 rtc: rtc@c2a0000 { 453 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 454 reg = <0x0c2a0000 0x10000>; 455 interrupt-parent = <&pmc>; 456 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 458 clock-names = "rtc"; 459 status = "disabled"; 460 }; 461 462 gpio_aon: gpio@c2f0000 { 463 compatible = "nvidia,tegra194-gpio-aon"; 464 reg-names = "security", "gpio"; 465 reg = <0xc2f0000 0x1000>, 466 <0xc2f1000 0x1000>; 467 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 }; 476 477 pwm4: pwm@c340000 { 478 compatible = "nvidia,tegra194-pwm", 479 "nvidia,tegra186-pwm"; 480 reg = <0xc340000 0x10000>; 481 clocks = <&bpmp TEGRA194_CLK_PWM4>; 482 clock-names = "pwm"; 483 resets = <&bpmp TEGRA194_RESET_PWM4>; 484 reset-names = "pwm"; 485 status = "disabled"; 486 #pwm-cells = <2>; 487 }; 488 489 pmc: pmc@c360000 { 490 compatible = "nvidia,tegra194-pmc"; 491 reg = <0x0c360000 0x10000>, 492 <0x0c370000 0x10000>, 493 <0x0c380000 0x10000>, 494 <0x0c390000 0x10000>, 495 <0x0c3a0000 0x10000>; 496 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 497 498 #interrupt-cells = <2>; 499 interrupt-controller; 500 }; 501 502 host1x@13e00000 { 503 compatible = "nvidia,tegra194-host1x", "simple-bus"; 504 reg = <0x13e00000 0x10000>, 505 <0x13e10000 0x10000>; 506 reg-names = "hypervisor", "vm"; 507 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 510 clock-names = "host1x"; 511 resets = <&bpmp TEGRA194_RESET_HOST1X>; 512 reset-names = "host1x"; 513 514 #address-cells = <1>; 515 #size-cells = <1>; 516 517 ranges = <0x15000000 0x15000000 0x01000000>; 518 519 display-hub@15200000 { 520 compatible = "nvidia,tegra194-display", "simple-bus"; 521 reg = <0x15200000 0x00040000>; 522 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 523 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 524 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 525 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 526 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 527 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 528 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 529 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 530 "wgrp3", "wgrp4", "wgrp5"; 531 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 532 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 533 clock-names = "disp", "hub"; 534 status = "disabled"; 535 536 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 537 538 #address-cells = <1>; 539 #size-cells = <1>; 540 541 ranges = <0x15200000 0x15200000 0x40000>; 542 543 display@15200000 { 544 compatible = "nvidia,tegra194-dc"; 545 reg = <0x15200000 0x10000>; 546 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 548 clock-names = "dc"; 549 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 550 reset-names = "dc"; 551 552 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 553 554 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 555 nvidia,head = <0>; 556 }; 557 558 display@15210000 { 559 compatible = "nvidia,tegra194-dc"; 560 reg = <0x15210000 0x10000>; 561 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 563 clock-names = "dc"; 564 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 565 reset-names = "dc"; 566 567 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 568 569 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 570 nvidia,head = <1>; 571 }; 572 573 display@15220000 { 574 compatible = "nvidia,tegra194-dc"; 575 reg = <0x15220000 0x10000>; 576 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 578 clock-names = "dc"; 579 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 580 reset-names = "dc"; 581 582 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 583 584 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 585 nvidia,head = <2>; 586 }; 587 588 display@15230000 { 589 compatible = "nvidia,tegra194-dc"; 590 reg = <0x15230000 0x10000>; 591 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 593 clock-names = "dc"; 594 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 595 reset-names = "dc"; 596 597 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 598 599 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 600 nvidia,head = <3>; 601 }; 602 }; 603 604 vic@15340000 { 605 compatible = "nvidia,tegra194-vic"; 606 reg = <0x15340000 0x00040000>; 607 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&bpmp TEGRA194_CLK_VIC>; 609 clock-names = "vic"; 610 resets = <&bpmp TEGRA194_RESET_VIC>; 611 reset-names = "vic"; 612 613 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 614 }; 615 616 dpaux0: dpaux@155c0000 { 617 compatible = "nvidia,tegra194-dpaux"; 618 reg = <0x155c0000 0x10000>; 619 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 621 <&bpmp TEGRA194_CLK_PLLDP>; 622 clock-names = "dpaux", "parent"; 623 resets = <&bpmp TEGRA194_RESET_DPAUX>; 624 reset-names = "dpaux"; 625 status = "disabled"; 626 627 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 628 629 state_dpaux0_aux: pinmux-aux { 630 groups = "dpaux-io"; 631 function = "aux"; 632 }; 633 634 state_dpaux0_i2c: pinmux-i2c { 635 groups = "dpaux-io"; 636 function = "i2c"; 637 }; 638 639 state_dpaux0_off: pinmux-off { 640 groups = "dpaux-io"; 641 function = "off"; 642 }; 643 644 i2c-bus { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 }; 648 }; 649 650 dpaux1: dpaux@155d0000 { 651 compatible = "nvidia,tegra194-dpaux"; 652 reg = <0x155d0000 0x10000>; 653 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 655 <&bpmp TEGRA194_CLK_PLLDP>; 656 clock-names = "dpaux", "parent"; 657 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 658 reset-names = "dpaux"; 659 status = "disabled"; 660 661 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 662 663 state_dpaux1_aux: pinmux-aux { 664 groups = "dpaux-io"; 665 function = "aux"; 666 }; 667 668 state_dpaux1_i2c: pinmux-i2c { 669 groups = "dpaux-io"; 670 function = "i2c"; 671 }; 672 673 state_dpaux1_off: pinmux-off { 674 groups = "dpaux-io"; 675 function = "off"; 676 }; 677 678 i2c-bus { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 }; 682 }; 683 684 dpaux2: dpaux@155e0000 { 685 compatible = "nvidia,tegra194-dpaux"; 686 reg = <0x155e0000 0x10000>; 687 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 689 <&bpmp TEGRA194_CLK_PLLDP>; 690 clock-names = "dpaux", "parent"; 691 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 692 reset-names = "dpaux"; 693 status = "disabled"; 694 695 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 696 697 state_dpaux2_aux: pinmux-aux { 698 groups = "dpaux-io"; 699 function = "aux"; 700 }; 701 702 state_dpaux2_i2c: pinmux-i2c { 703 groups = "dpaux-io"; 704 function = "i2c"; 705 }; 706 707 state_dpaux2_off: pinmux-off { 708 groups = "dpaux-io"; 709 function = "off"; 710 }; 711 712 i2c-bus { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 }; 716 }; 717 718 dpaux3: dpaux@155f0000 { 719 compatible = "nvidia,tegra194-dpaux"; 720 reg = <0x155f0000 0x10000>; 721 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 723 <&bpmp TEGRA194_CLK_PLLDP>; 724 clock-names = "dpaux", "parent"; 725 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 726 reset-names = "dpaux"; 727 status = "disabled"; 728 729 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 730 731 state_dpaux3_aux: pinmux-aux { 732 groups = "dpaux-io"; 733 function = "aux"; 734 }; 735 736 state_dpaux3_i2c: pinmux-i2c { 737 groups = "dpaux-io"; 738 function = "i2c"; 739 }; 740 741 state_dpaux3_off: pinmux-off { 742 groups = "dpaux-io"; 743 function = "off"; 744 }; 745 746 i2c-bus { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 }; 750 }; 751 752 sor0: sor@15b00000 { 753 compatible = "nvidia,tegra194-sor"; 754 reg = <0x15b00000 0x40000>; 755 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 757 <&bpmp TEGRA194_CLK_SOR0_OUT>, 758 <&bpmp TEGRA194_CLK_PLLD>, 759 <&bpmp TEGRA194_CLK_PLLDP>, 760 <&bpmp TEGRA194_CLK_SOR_SAFE>, 761 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 762 clock-names = "sor", "out", "parent", "dp", "safe", 763 "pad"; 764 resets = <&bpmp TEGRA194_RESET_SOR0>; 765 reset-names = "sor"; 766 pinctrl-0 = <&state_dpaux0_aux>; 767 pinctrl-1 = <&state_dpaux0_i2c>; 768 pinctrl-2 = <&state_dpaux0_off>; 769 pinctrl-names = "aux", "i2c", "off"; 770 status = "disabled"; 771 772 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 773 nvidia,interface = <0>; 774 }; 775 776 sor1: sor@15b40000 { 777 compatible = "nvidia,tegra194-sor"; 778 reg = <0x155c0000 0x40000>; 779 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 781 <&bpmp TEGRA194_CLK_SOR1_OUT>, 782 <&bpmp TEGRA194_CLK_PLLD2>, 783 <&bpmp TEGRA194_CLK_PLLDP>, 784 <&bpmp TEGRA194_CLK_SOR_SAFE>, 785 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 786 clock-names = "sor", "out", "parent", "dp", "safe", 787 "pad"; 788 resets = <&bpmp TEGRA194_RESET_SOR1>; 789 reset-names = "sor"; 790 pinctrl-0 = <&state_dpaux1_aux>; 791 pinctrl-1 = <&state_dpaux1_i2c>; 792 pinctrl-2 = <&state_dpaux1_off>; 793 pinctrl-names = "aux", "i2c", "off"; 794 status = "disabled"; 795 796 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 797 nvidia,interface = <1>; 798 }; 799 800 sor2: sor@15b80000 { 801 compatible = "nvidia,tegra194-sor"; 802 reg = <0x15b80000 0x40000>; 803 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 805 <&bpmp TEGRA194_CLK_SOR2_OUT>, 806 <&bpmp TEGRA194_CLK_PLLD3>, 807 <&bpmp TEGRA194_CLK_PLLDP>, 808 <&bpmp TEGRA194_CLK_SOR_SAFE>, 809 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 810 clock-names = "sor", "out", "parent", "dp", "safe", 811 "pad"; 812 resets = <&bpmp TEGRA194_RESET_SOR2>; 813 reset-names = "sor"; 814 pinctrl-0 = <&state_dpaux2_aux>; 815 pinctrl-1 = <&state_dpaux2_i2c>; 816 pinctrl-2 = <&state_dpaux2_off>; 817 pinctrl-names = "aux", "i2c", "off"; 818 status = "disabled"; 819 820 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 821 nvidia,interface = <2>; 822 }; 823 824 sor3: sor@15bc0000 { 825 compatible = "nvidia,tegra194-sor"; 826 reg = <0x15bc0000 0x40000>; 827 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 829 <&bpmp TEGRA194_CLK_SOR3_OUT>, 830 <&bpmp TEGRA194_CLK_PLLD4>, 831 <&bpmp TEGRA194_CLK_PLLDP>, 832 <&bpmp TEGRA194_CLK_SOR_SAFE>, 833 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 834 clock-names = "sor", "out", "parent", "dp", "safe", 835 "pad"; 836 resets = <&bpmp TEGRA194_RESET_SOR3>; 837 reset-names = "sor"; 838 pinctrl-0 = <&state_dpaux3_aux>; 839 pinctrl-1 = <&state_dpaux3_i2c>; 840 pinctrl-2 = <&state_dpaux3_off>; 841 pinctrl-names = "aux", "i2c", "off"; 842 status = "disabled"; 843 844 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 845 nvidia,interface = <3>; 846 }; 847 }; 848 }; 849 850 sysram@40000000 { 851 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 852 reg = <0x0 0x40000000 0x0 0x50000>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 ranges = <0x0 0x0 0x40000000 0x50000>; 856 857 cpu_bpmp_tx: shmem@4e000 { 858 compatible = "nvidia,tegra194-bpmp-shmem"; 859 reg = <0x4e000 0x1000>; 860 label = "cpu-bpmp-tx"; 861 pool; 862 }; 863 864 cpu_bpmp_rx: shmem@4f000 { 865 compatible = "nvidia,tegra194-bpmp-shmem"; 866 reg = <0x4f000 0x1000>; 867 label = "cpu-bpmp-rx"; 868 pool; 869 }; 870 }; 871 872 bpmp: bpmp { 873 compatible = "nvidia,tegra186-bpmp"; 874 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 875 TEGRA_HSP_DB_MASTER_BPMP>; 876 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 877 #clock-cells = <1>; 878 #reset-cells = <1>; 879 #power-domain-cells = <1>; 880 881 bpmp_i2c: i2c { 882 compatible = "nvidia,tegra186-bpmp-i2c"; 883 nvidia,bpmp-bus-id = <5>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 }; 887 888 bpmp_thermal: thermal { 889 compatible = "nvidia,tegra186-bpmp-thermal"; 890 #thermal-sensor-cells = <1>; 891 }; 892 }; 893 894 cpus { 895 #address-cells = <1>; 896 #size-cells = <0>; 897 898 cpu@0 { 899 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 900 device_type = "cpu"; 901 reg = <0x10000>; 902 enable-method = "psci"; 903 }; 904 905 cpu@1 { 906 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 907 device_type = "cpu"; 908 reg = <0x10001>; 909 enable-method = "psci"; 910 }; 911 912 cpu@2 { 913 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 914 device_type = "cpu"; 915 reg = <0x100>; 916 enable-method = "psci"; 917 }; 918 919 cpu@3 { 920 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 921 device_type = "cpu"; 922 reg = <0x101>; 923 enable-method = "psci"; 924 }; 925 926 cpu@4 { 927 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 928 device_type = "cpu"; 929 reg = <0x200>; 930 enable-method = "psci"; 931 }; 932 933 cpu@5 { 934 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 935 device_type = "cpu"; 936 reg = <0x201>; 937 enable-method = "psci"; 938 }; 939 940 cpu@6 { 941 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 942 device_type = "cpu"; 943 reg = <0x10300>; 944 enable-method = "psci"; 945 }; 946 947 cpu@7 { 948 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 949 device_type = "cpu"; 950 reg = <0x10301>; 951 enable-method = "psci"; 952 }; 953 }; 954 955 psci { 956 compatible = "arm,psci-1.0"; 957 status = "okay"; 958 method = "smc"; 959 }; 960 961 tcu: tcu { 962 compatible = "nvidia,tegra194-tcu"; 963 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 964 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 965 mbox-names = "rx", "tx"; 966 }; 967 968 thermal-zones { 969 cpu { 970 thermal-sensors = <&{/bpmp/thermal} 971 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 972 status = "disabled"; 973 }; 974 975 gpu { 976 thermal-sensors = <&{/bpmp/thermal} 977 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 978 status = "disabled"; 979 }; 980 981 aux { 982 thermal-sensors = <&{/bpmp/thermal} 983 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 984 status = "disabled"; 985 }; 986 987 pllx { 988 thermal-sensors = <&{/bpmp/thermal} 989 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 990 status = "disabled"; 991 }; 992 993 ao { 994 thermal-sensors = <&{/bpmp/thermal} 995 TEGRA194_BPMP_THERMAL_ZONE_AO>; 996 status = "disabled"; 997 }; 998 999 tj { 1000 thermal-sensors = <&{/bpmp/thermal} 1001 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1002 status = "disabled"; 1003 }; 1004 }; 1005 1006 timer { 1007 compatible = "arm,armv8-timer"; 1008 interrupts = <GIC_PPI 13 1009 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1010 <GIC_PPI 14 1011 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1012 <GIC_PPI 11 1013 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1014 <GIC_PPI 10 1015 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1016 interrupt-parent = <&gic>; 1017 }; 1018}; 1019