1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 307 <0x07>; 308 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 309 <0x07>; 310 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 311 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 312 <0x07>; 313 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 314 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 315 nvidia,default-tap = <0x9>; 316 nvidia,default-trim = <0x5>; 317 status = "disabled"; 318 }; 319 320 sdmmc3: sdhci@3440000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03440000 0x10000>; 323 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 327 reset-names = "sdhci"; 328 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 329 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 330 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 331 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 332 <0x07>; 333 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 334 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 335 <0x07>; 336 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 337 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 338 nvidia,default-tap = <0x9>; 339 nvidia,default-trim = <0x5>; 340 status = "disabled"; 341 }; 342 343 sdmmc4: sdhci@3460000 { 344 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 345 reg = <0x03460000 0x10000>; 346 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 348 clock-names = "sdhci"; 349 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 350 reset-names = "sdhci"; 351 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 352 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 353 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 354 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 355 <0x0a>; 356 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 357 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 358 <0x0a>; 359 nvidia,default-tap = <0x8>; 360 nvidia,default-trim = <0x14>; 361 nvidia,dqs-trim = <40>; 362 supports-cqe; 363 status = "disabled"; 364 }; 365 366 hda@3510000 { 367 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 368 reg = <0x3510000 0x10000>; 369 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&bpmp TEGRA194_CLK_HDA>, 371 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 372 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 373 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 374 resets = <&bpmp TEGRA194_RESET_HDA>, 375 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 376 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 377 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 378 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 379 status = "disabled"; 380 }; 381 382 gic: interrupt-controller@3881000 { 383 compatible = "arm,gic-400"; 384 #interrupt-cells = <3>; 385 interrupt-controller; 386 reg = <0x03881000 0x1000>, 387 <0x03882000 0x2000>, 388 <0x03884000 0x2000>, 389 <0x03886000 0x2000>; 390 interrupts = <GIC_PPI 9 391 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 392 interrupt-parent = <&gic>; 393 }; 394 395 cec@3960000 { 396 compatible = "nvidia,tegra194-cec"; 397 reg = <0x03960000 0x10000>; 398 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&bpmp TEGRA194_CLK_CEC>; 400 clock-names = "cec"; 401 status = "disabled"; 402 }; 403 404 hsp_top0: hsp@3c00000 { 405 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 406 reg = <0x03c00000 0xa0000>; 407 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 417 "shared3", "shared4", "shared5", "shared6", 418 "shared7"; 419 #mbox-cells = <2>; 420 }; 421 422 hsp_aon: hsp@c150000 { 423 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 424 reg = <0x0c150000 0xa0000>; 425 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 429 /* 430 * Shared interrupt 0 is routed only to AON/SPE, so 431 * we only have 4 shared interrupts for the CCPLEX. 432 */ 433 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 434 #mbox-cells = <2>; 435 }; 436 437 gen2_i2c: i2c@c240000 { 438 compatible = "nvidia,tegra194-i2c"; 439 reg = <0x0c240000 0x10000>; 440 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 clocks = <&bpmp TEGRA194_CLK_I2C2>; 444 clock-names = "div-clk"; 445 resets = <&bpmp TEGRA194_RESET_I2C2>; 446 reset-names = "i2c"; 447 status = "disabled"; 448 }; 449 450 gen8_i2c: i2c@c250000 { 451 compatible = "nvidia,tegra194-i2c"; 452 reg = <0x0c250000 0x10000>; 453 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 clocks = <&bpmp TEGRA194_CLK_I2C8>; 457 clock-names = "div-clk"; 458 resets = <&bpmp TEGRA194_RESET_I2C8>; 459 reset-names = "i2c"; 460 status = "disabled"; 461 }; 462 463 uartc: serial@c280000 { 464 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 465 reg = <0x0c280000 0x40>; 466 reg-shift = <2>; 467 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&bpmp TEGRA194_CLK_UARTC>; 469 clock-names = "serial"; 470 resets = <&bpmp TEGRA194_RESET_UARTC>; 471 reset-names = "serial"; 472 status = "disabled"; 473 }; 474 475 uartg: serial@c290000 { 476 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 477 reg = <0x0c290000 0x40>; 478 reg-shift = <2>; 479 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&bpmp TEGRA194_CLK_UARTG>; 481 clock-names = "serial"; 482 resets = <&bpmp TEGRA194_RESET_UARTG>; 483 reset-names = "serial"; 484 status = "disabled"; 485 }; 486 487 rtc: rtc@c2a0000 { 488 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 489 reg = <0x0c2a0000 0x10000>; 490 interrupt-parent = <&pmc>; 491 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 493 clock-names = "rtc"; 494 status = "disabled"; 495 }; 496 497 gpio_aon: gpio@c2f0000 { 498 compatible = "nvidia,tegra194-gpio-aon"; 499 reg-names = "security", "gpio"; 500 reg = <0xc2f0000 0x1000>, 501 <0xc2f1000 0x1000>; 502 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 }; 511 512 pwm4: pwm@c340000 { 513 compatible = "nvidia,tegra194-pwm", 514 "nvidia,tegra186-pwm"; 515 reg = <0xc340000 0x10000>; 516 clocks = <&bpmp TEGRA194_CLK_PWM4>; 517 clock-names = "pwm"; 518 resets = <&bpmp TEGRA194_RESET_PWM4>; 519 reset-names = "pwm"; 520 status = "disabled"; 521 #pwm-cells = <2>; 522 }; 523 524 pmc: pmc@c360000 { 525 compatible = "nvidia,tegra194-pmc"; 526 reg = <0x0c360000 0x10000>, 527 <0x0c370000 0x10000>, 528 <0x0c380000 0x10000>, 529 <0x0c390000 0x10000>, 530 <0x0c3a0000 0x10000>; 531 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 532 533 #interrupt-cells = <2>; 534 interrupt-controller; 535 }; 536 537 host1x@13e00000 { 538 compatible = "nvidia,tegra194-host1x", "simple-bus"; 539 reg = <0x13e00000 0x10000>, 540 <0x13e10000 0x10000>; 541 reg-names = "hypervisor", "vm"; 542 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 545 clock-names = "host1x"; 546 resets = <&bpmp TEGRA194_RESET_HOST1X>; 547 reset-names = "host1x"; 548 549 #address-cells = <1>; 550 #size-cells = <1>; 551 552 ranges = <0x15000000 0x15000000 0x01000000>; 553 554 display-hub@15200000 { 555 compatible = "nvidia,tegra194-display", "simple-bus"; 556 reg = <0x15200000 0x00040000>; 557 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 558 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 559 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 560 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 561 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 562 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 563 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 564 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 565 "wgrp3", "wgrp4", "wgrp5"; 566 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 567 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 568 clock-names = "disp", "hub"; 569 status = "disabled"; 570 571 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 572 573 #address-cells = <1>; 574 #size-cells = <1>; 575 576 ranges = <0x15200000 0x15200000 0x40000>; 577 578 display@15200000 { 579 compatible = "nvidia,tegra194-dc"; 580 reg = <0x15200000 0x10000>; 581 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 583 clock-names = "dc"; 584 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 585 reset-names = "dc"; 586 587 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 588 589 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 590 nvidia,head = <0>; 591 }; 592 593 display@15210000 { 594 compatible = "nvidia,tegra194-dc"; 595 reg = <0x15210000 0x10000>; 596 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 598 clock-names = "dc"; 599 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 600 reset-names = "dc"; 601 602 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 603 604 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 605 nvidia,head = <1>; 606 }; 607 608 display@15220000 { 609 compatible = "nvidia,tegra194-dc"; 610 reg = <0x15220000 0x10000>; 611 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 613 clock-names = "dc"; 614 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 615 reset-names = "dc"; 616 617 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 618 619 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 620 nvidia,head = <2>; 621 }; 622 623 display@15230000 { 624 compatible = "nvidia,tegra194-dc"; 625 reg = <0x15230000 0x10000>; 626 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 628 clock-names = "dc"; 629 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 630 reset-names = "dc"; 631 632 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 633 634 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 635 nvidia,head = <3>; 636 }; 637 }; 638 639 vic@15340000 { 640 compatible = "nvidia,tegra194-vic"; 641 reg = <0x15340000 0x00040000>; 642 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA194_CLK_VIC>; 644 clock-names = "vic"; 645 resets = <&bpmp TEGRA194_RESET_VIC>; 646 reset-names = "vic"; 647 648 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 649 }; 650 651 dpaux0: dpaux@155c0000 { 652 compatible = "nvidia,tegra194-dpaux"; 653 reg = <0x155c0000 0x10000>; 654 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 656 <&bpmp TEGRA194_CLK_PLLDP>; 657 clock-names = "dpaux", "parent"; 658 resets = <&bpmp TEGRA194_RESET_DPAUX>; 659 reset-names = "dpaux"; 660 status = "disabled"; 661 662 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 663 664 state_dpaux0_aux: pinmux-aux { 665 groups = "dpaux-io"; 666 function = "aux"; 667 }; 668 669 state_dpaux0_i2c: pinmux-i2c { 670 groups = "dpaux-io"; 671 function = "i2c"; 672 }; 673 674 state_dpaux0_off: pinmux-off { 675 groups = "dpaux-io"; 676 function = "off"; 677 }; 678 679 i2c-bus { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 }; 683 }; 684 685 dpaux1: dpaux@155d0000 { 686 compatible = "nvidia,tegra194-dpaux"; 687 reg = <0x155d0000 0x10000>; 688 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 690 <&bpmp TEGRA194_CLK_PLLDP>; 691 clock-names = "dpaux", "parent"; 692 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 693 reset-names = "dpaux"; 694 status = "disabled"; 695 696 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 697 698 state_dpaux1_aux: pinmux-aux { 699 groups = "dpaux-io"; 700 function = "aux"; 701 }; 702 703 state_dpaux1_i2c: pinmux-i2c { 704 groups = "dpaux-io"; 705 function = "i2c"; 706 }; 707 708 state_dpaux1_off: pinmux-off { 709 groups = "dpaux-io"; 710 function = "off"; 711 }; 712 713 i2c-bus { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 }; 717 }; 718 719 dpaux2: dpaux@155e0000 { 720 compatible = "nvidia,tegra194-dpaux"; 721 reg = <0x155e0000 0x10000>; 722 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 724 <&bpmp TEGRA194_CLK_PLLDP>; 725 clock-names = "dpaux", "parent"; 726 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 727 reset-names = "dpaux"; 728 status = "disabled"; 729 730 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 731 732 state_dpaux2_aux: pinmux-aux { 733 groups = "dpaux-io"; 734 function = "aux"; 735 }; 736 737 state_dpaux2_i2c: pinmux-i2c { 738 groups = "dpaux-io"; 739 function = "i2c"; 740 }; 741 742 state_dpaux2_off: pinmux-off { 743 groups = "dpaux-io"; 744 function = "off"; 745 }; 746 747 i2c-bus { 748 #address-cells = <1>; 749 #size-cells = <0>; 750 }; 751 }; 752 753 dpaux3: dpaux@155f0000 { 754 compatible = "nvidia,tegra194-dpaux"; 755 reg = <0x155f0000 0x10000>; 756 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 758 <&bpmp TEGRA194_CLK_PLLDP>; 759 clock-names = "dpaux", "parent"; 760 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 761 reset-names = "dpaux"; 762 status = "disabled"; 763 764 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 765 766 state_dpaux3_aux: pinmux-aux { 767 groups = "dpaux-io"; 768 function = "aux"; 769 }; 770 771 state_dpaux3_i2c: pinmux-i2c { 772 groups = "dpaux-io"; 773 function = "i2c"; 774 }; 775 776 state_dpaux3_off: pinmux-off { 777 groups = "dpaux-io"; 778 function = "off"; 779 }; 780 781 i2c-bus { 782 #address-cells = <1>; 783 #size-cells = <0>; 784 }; 785 }; 786 787 sor0: sor@15b00000 { 788 compatible = "nvidia,tegra194-sor"; 789 reg = <0x15b00000 0x40000>; 790 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 792 <&bpmp TEGRA194_CLK_SOR0_OUT>, 793 <&bpmp TEGRA194_CLK_PLLD>, 794 <&bpmp TEGRA194_CLK_PLLDP>, 795 <&bpmp TEGRA194_CLK_SOR_SAFE>, 796 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 797 clock-names = "sor", "out", "parent", "dp", "safe", 798 "pad"; 799 resets = <&bpmp TEGRA194_RESET_SOR0>; 800 reset-names = "sor"; 801 pinctrl-0 = <&state_dpaux0_aux>; 802 pinctrl-1 = <&state_dpaux0_i2c>; 803 pinctrl-2 = <&state_dpaux0_off>; 804 pinctrl-names = "aux", "i2c", "off"; 805 status = "disabled"; 806 807 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 808 nvidia,interface = <0>; 809 }; 810 811 sor1: sor@15b40000 { 812 compatible = "nvidia,tegra194-sor"; 813 reg = <0x155c0000 0x40000>; 814 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 816 <&bpmp TEGRA194_CLK_SOR1_OUT>, 817 <&bpmp TEGRA194_CLK_PLLD2>, 818 <&bpmp TEGRA194_CLK_PLLDP>, 819 <&bpmp TEGRA194_CLK_SOR_SAFE>, 820 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 821 clock-names = "sor", "out", "parent", "dp", "safe", 822 "pad"; 823 resets = <&bpmp TEGRA194_RESET_SOR1>; 824 reset-names = "sor"; 825 pinctrl-0 = <&state_dpaux1_aux>; 826 pinctrl-1 = <&state_dpaux1_i2c>; 827 pinctrl-2 = <&state_dpaux1_off>; 828 pinctrl-names = "aux", "i2c", "off"; 829 status = "disabled"; 830 831 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 832 nvidia,interface = <1>; 833 }; 834 835 sor2: sor@15b80000 { 836 compatible = "nvidia,tegra194-sor"; 837 reg = <0x15b80000 0x40000>; 838 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 840 <&bpmp TEGRA194_CLK_SOR2_OUT>, 841 <&bpmp TEGRA194_CLK_PLLD3>, 842 <&bpmp TEGRA194_CLK_PLLDP>, 843 <&bpmp TEGRA194_CLK_SOR_SAFE>, 844 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 845 clock-names = "sor", "out", "parent", "dp", "safe", 846 "pad"; 847 resets = <&bpmp TEGRA194_RESET_SOR2>; 848 reset-names = "sor"; 849 pinctrl-0 = <&state_dpaux2_aux>; 850 pinctrl-1 = <&state_dpaux2_i2c>; 851 pinctrl-2 = <&state_dpaux2_off>; 852 pinctrl-names = "aux", "i2c", "off"; 853 status = "disabled"; 854 855 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 856 nvidia,interface = <2>; 857 }; 858 859 sor3: sor@15bc0000 { 860 compatible = "nvidia,tegra194-sor"; 861 reg = <0x15bc0000 0x40000>; 862 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 864 <&bpmp TEGRA194_CLK_SOR3_OUT>, 865 <&bpmp TEGRA194_CLK_PLLD4>, 866 <&bpmp TEGRA194_CLK_PLLDP>, 867 <&bpmp TEGRA194_CLK_SOR_SAFE>, 868 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 869 clock-names = "sor", "out", "parent", "dp", "safe", 870 "pad"; 871 resets = <&bpmp TEGRA194_RESET_SOR3>; 872 reset-names = "sor"; 873 pinctrl-0 = <&state_dpaux3_aux>; 874 pinctrl-1 = <&state_dpaux3_i2c>; 875 pinctrl-2 = <&state_dpaux3_off>; 876 pinctrl-names = "aux", "i2c", "off"; 877 status = "disabled"; 878 879 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 880 nvidia,interface = <3>; 881 }; 882 }; 883 }; 884 885 sysram@40000000 { 886 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 887 reg = <0x0 0x40000000 0x0 0x50000>; 888 #address-cells = <1>; 889 #size-cells = <1>; 890 ranges = <0x0 0x0 0x40000000 0x50000>; 891 892 cpu_bpmp_tx: shmem@4e000 { 893 compatible = "nvidia,tegra194-bpmp-shmem"; 894 reg = <0x4e000 0x1000>; 895 label = "cpu-bpmp-tx"; 896 pool; 897 }; 898 899 cpu_bpmp_rx: shmem@4f000 { 900 compatible = "nvidia,tegra194-bpmp-shmem"; 901 reg = <0x4f000 0x1000>; 902 label = "cpu-bpmp-rx"; 903 pool; 904 }; 905 }; 906 907 bpmp: bpmp { 908 compatible = "nvidia,tegra186-bpmp"; 909 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 910 TEGRA_HSP_DB_MASTER_BPMP>; 911 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 912 #clock-cells = <1>; 913 #reset-cells = <1>; 914 #power-domain-cells = <1>; 915 916 bpmp_i2c: i2c { 917 compatible = "nvidia,tegra186-bpmp-i2c"; 918 nvidia,bpmp-bus-id = <5>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 }; 922 923 bpmp_thermal: thermal { 924 compatible = "nvidia,tegra186-bpmp-thermal"; 925 #thermal-sensor-cells = <1>; 926 }; 927 }; 928 929 cpus { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 933 cpu@0 { 934 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 935 device_type = "cpu"; 936 reg = <0x10000>; 937 enable-method = "psci"; 938 }; 939 940 cpu@1 { 941 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 942 device_type = "cpu"; 943 reg = <0x10001>; 944 enable-method = "psci"; 945 }; 946 947 cpu@2 { 948 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 949 device_type = "cpu"; 950 reg = <0x100>; 951 enable-method = "psci"; 952 }; 953 954 cpu@3 { 955 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 956 device_type = "cpu"; 957 reg = <0x101>; 958 enable-method = "psci"; 959 }; 960 961 cpu@4 { 962 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 963 device_type = "cpu"; 964 reg = <0x200>; 965 enable-method = "psci"; 966 }; 967 968 cpu@5 { 969 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 970 device_type = "cpu"; 971 reg = <0x201>; 972 enable-method = "psci"; 973 }; 974 975 cpu@6 { 976 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 977 device_type = "cpu"; 978 reg = <0x10300>; 979 enable-method = "psci"; 980 }; 981 982 cpu@7 { 983 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 984 device_type = "cpu"; 985 reg = <0x10301>; 986 enable-method = "psci"; 987 }; 988 }; 989 990 psci { 991 compatible = "arm,psci-1.0"; 992 status = "okay"; 993 method = "smc"; 994 }; 995 996 tcu: tcu { 997 compatible = "nvidia,tegra194-tcu"; 998 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 999 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1000 mbox-names = "rx", "tx"; 1001 }; 1002 1003 thermal-zones { 1004 cpu { 1005 thermal-sensors = <&{/bpmp/thermal} 1006 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1007 status = "disabled"; 1008 }; 1009 1010 gpu { 1011 thermal-sensors = <&{/bpmp/thermal} 1012 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1013 status = "disabled"; 1014 }; 1015 1016 aux { 1017 thermal-sensors = <&{/bpmp/thermal} 1018 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1019 status = "disabled"; 1020 }; 1021 1022 pllx { 1023 thermal-sensors = <&{/bpmp/thermal} 1024 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1025 status = "disabled"; 1026 }; 1027 1028 ao { 1029 thermal-sensors = <&{/bpmp/thermal} 1030 TEGRA194_BPMP_THERMAL_ZONE_AO>; 1031 status = "disabled"; 1032 }; 1033 1034 tj { 1035 thermal-sensors = <&{/bpmp/thermal} 1036 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1037 status = "disabled"; 1038 }; 1039 }; 1040 1041 timer { 1042 compatible = "arm,armv8-timer"; 1043 interrupts = <GIC_PPI 13 1044 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1045 <GIC_PPI 14 1046 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1047 <GIC_PPI 11 1048 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1049 <GIC_PPI 10 1050 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1051 interrupt-parent = <&gic>; 1052 }; 1053}; 1054