arm64: tegra: Update AHUB clock parent and rate

I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely

arm64: tegra: Update AHUB clock parent and rate

I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely that similar issues would be seen. Thus update the
AHUB clock parent and rates here as well for Tegra194, Tegra186
and Tegra210.

Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components")
Cc: stable@vger.kernel.org
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop serial clock-names and reset-names

The serial node does not use clock-names and reset-names:

tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('cloc

arm64: tegra: Drop serial clock-names and reset-names

The serial node does not use clock-names and reset-names:

tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234

Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map,
so bump the CBB ranges property to cover all of the 1 TiB add

arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234

Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map,
so bump the CBB ranges property to cover all of the 1 TiB address space.
This fixes an issue where some of the PCIe regions could not be remapped
because of they were outside the memory specified by the CBB's ranges
property.

Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop I2C iommus and dma-coherent properties

Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that r

arm64: tegra: Drop I2C iommus and dma-coherent properties

Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that represent the GPC DMA controller, since that is the device
performing the direct memory accesses.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Mark host1x as dma-coherent on Tegra194/234

Ensure appropriate configuration is done to make the host1x device
and context devices DMA coherent by adding the dma-coherent flag.

Fixes:

arm64: tegra: Mark host1x as dma-coherent on Tegra194/234

Ensure appropriate configuration is done to make the host1x device
and context devices DMA coherent by adding the dma-coherent flag.

Fixes: b35f5b53a87b ("arm64: tegra: Add context isolation domains on Tegra234")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add dma-coherent property for Tegra194 XUDC

DMA operations for XUSB device controller (XUDC) are coherent for
Tegra194 and so add the 'dma-coherent' property for this device.

Signed-o

arm64: tegra: Add dma-coherent property for Tegra194 XUDC

DMA operations for XUSB device controller (XUDC) are coherent for
Tegra194 and so add the 'dma-coherent' property for this device.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Sort nodes by unit-address, then alphabetically

Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions

arm64: tegra: Sort nodes by unit-address, then alphabetically

Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.

These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").

While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Bump #address-cells and #size-cells

The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
th

arm64: tegra: Bump #address-cells and #size-cells

The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
the IP blocks on that bus. However, most of these devices can do DMA to
a larger address space, so translation of DMA addresses needs to happen
in a 64-bit address space.

Partially this was already done by the memory controller increasing that
address space by setting #address-cells and #size-cells to 2, but a full
DMA address translation would still cause truncation when traversing to
the top-level bus.

Fix this by setting #address-cells = <2> and #size-cells = <2> on the
top-level bus and adjusting all "reg" and "ranges" properties of its
children.

While at it, also move the PCI and GPU nodes back under the top-level
bus where they belong. The were put outside of it to work around this
same problem.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix typo in gpio-ranges property

The gpio-ranges property name was missing a terminating "s", causing it
to not be parsed and fail DT validation as well.

Signed-off-by: Thierry Reding

arm64: tegra: Fix typo in gpio-ranges property

The gpio-ranges property name was missing a terminating "s", causing it
to not be parsed and fail DT validation as well.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fixup pinmux node names

Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.

Signed-off-by: Thierry Reding <tredin

arm64: tegra: Fixup pinmux node names

Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove reset-names for QSPI

The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property fro

arm64: tegra: Remove reset-names for QSPI

The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property from device tree files to avoid validation warnings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use correct compatible string for Tegra194 HDA

The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.

Signed-

arm64: tegra: Use correct compatible string for Tegra194 HDA

The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Update cache properties

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache

arm64: tegra: Update cache properties

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add dma-channel-mask in GPCDMA node

Add dma-channel-mask property in Tegra GPCDMA device tree node.

The property would help to specify the channels to be used in
kernel and reserve fe

arm64: tegra: Add dma-channel-mask in GPCDMA node

Add dma-channel-mask property in Tegra GPCDMA device tree node.

The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
This is wrong and does not align with the hardware. Correct this
and update the interrupts property to list all 32 interrupts.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Separate AON pinmux from main pinmux on Tegra194

The registers for the AON pinmux reside in a partition different from
the registers for the main pinmux. Instead of treating them as on

arm64: tegra: Separate AON pinmux from main pinmux on Tegra194

The registers for the AON pinmux reside in a partition different from
the registers for the main pinmux. Instead of treating them as one and
the same device, split them up so that they are each their own devices.
Also add gpio-ranges properties to the corresponding GPIO controllers
such that the pinmux and GPIO controllers can be paired up properly.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove clock-names from PWM nodes

The Tegra PWFM controllers use a single clock, so there's no need for a
clock-names property.

Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+

arm64: tegra: Remove clock-names from PWM nodes

The Tegra PWFM controllers use a single clock, so there's no need for a
clock-names property.

Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable GTE nodes

Add and enable AON and LIC GTE nodes by default.

Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Fix ranges for host1x nodes

The currently specified 'ranges' properties don't actually include
all devices under the host1x bus on Tegra194 and Tegra234. Expand
them appropriately.

Si

arm64: tegra: Fix ranges for host1x nodes

The currently specified 'ranges' properties don't actually include
all devices under the host1x bus on Tegra194 and Tegra234. Expand
them appropriately.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add GPCDMA support for Tegra I2C

Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Redin

arm64: tegra: Add GPCDMA support for Tegra I2C

Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fixup iommu-map property formatting

Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@n

arm64: tegra: Fixup iommu-map property formatting

Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add Host1x context stream IDs on Tegra186+

Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow

arm64: tegra: Add Host1x context stream IDs on Tegra186+

Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.

The specified stream IDs must match those configured by the hypervisor,
if one is present.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable native timers on Tegra194

The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add and
enable the dev

arm64: tegra: Enable native timers on Tegra194

The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add and
enable the device tree node on Tegra194.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add node for CBB 1.0 on Tegra194

Add device tree nodes to enable error handling on the Control Backbone
(CBB). Tegra194 uses CBB version 1.0.

Signed-off-by: Sumit Gupta <sumitg@nvidia

arm64: tegra: Add node for CBB 1.0 on Tegra194

Add device tree nodes to enable error handling on the Control Backbone
(CBB). Tegra194 uses CBB version 1.0.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Mark BPMP channels as no-memory-wc

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will caus

arm64: tegra: Mark BPMP channels as no-memory-wc

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will cause issues.

Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted
to resolve this by only mapping the regions specified in the device
tree on the assumption that there are no such restricted areas within
the 64K-aligned area of memory that contains the memory we wish to map.

Turns out this assumption is wrong, as there are such areas above the
4K pages described in the device trees. As such, we need to use the
bigger hammer that is no-memory-wc, which causes the memory to be
mapped as Device memory to which speculative accesses are disallowed.

As such, the previous patch in the series,
'firmware: tegra: bpmp: do only aligned access to IPC memory area',
is required with this patch to make the BPMP driver only issue aligned
memory accesses as those are also required with Device memory.

Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add OPE device on Tegra210 and later

Output Processing Engine (OPE) is a client of AHUB and is present on
Tegra210 and later generations of Tegra SoC. Add this device on the
relevant S

arm64: tegra: Add OPE device on Tegra210 and later

Output Processing Engine (OPE) is a client of AHUB and is present on
Tegra210 and later generations of Tegra SoC. Add this device on the
relevant SoC DTSI files.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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