1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 hda@3510000 { 332 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 333 reg = <0x3510000 0x10000>; 334 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&bpmp TEGRA194_CLK_HDA>, 336 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 337 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 338 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 339 resets = <&bpmp TEGRA194_RESET_HDA>, 340 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 341 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 342 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 343 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 344 status = "disabled"; 345 }; 346 347 gic: interrupt-controller@3881000 { 348 compatible = "arm,gic-400"; 349 #interrupt-cells = <3>; 350 interrupt-controller; 351 reg = <0x03881000 0x1000>, 352 <0x03882000 0x2000>, 353 <0x03884000 0x2000>, 354 <0x03886000 0x2000>; 355 interrupts = <GIC_PPI 9 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 357 interrupt-parent = <&gic>; 358 }; 359 360 cec@3960000 { 361 compatible = "nvidia,tegra194-cec"; 362 reg = <0x03960000 0x10000>; 363 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&bpmp TEGRA194_CLK_CEC>; 365 clock-names = "cec"; 366 status = "disabled"; 367 }; 368 369 hsp_top0: hsp@3c00000 { 370 compatible = "nvidia,tegra186-hsp"; 371 reg = <0x03c00000 0xa0000>; 372 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-names = "doorbell"; 374 #mbox-cells = <2>; 375 }; 376 377 gen2_i2c: i2c@c240000 { 378 compatible = "nvidia,tegra194-i2c"; 379 reg = <0x0c240000 0x10000>; 380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&bpmp TEGRA194_CLK_I2C2>; 384 clock-names = "div-clk"; 385 resets = <&bpmp TEGRA194_RESET_I2C2>; 386 reset-names = "i2c"; 387 status = "disabled"; 388 }; 389 390 gen8_i2c: i2c@c250000 { 391 compatible = "nvidia,tegra194-i2c"; 392 reg = <0x0c250000 0x10000>; 393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&bpmp TEGRA194_CLK_I2C8>; 397 clock-names = "div-clk"; 398 resets = <&bpmp TEGRA194_RESET_I2C8>; 399 reset-names = "i2c"; 400 status = "disabled"; 401 }; 402 403 uartc: serial@c280000 { 404 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 405 reg = <0x0c280000 0x40>; 406 reg-shift = <2>; 407 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&bpmp TEGRA194_CLK_UARTC>; 409 clock-names = "serial"; 410 resets = <&bpmp TEGRA194_RESET_UARTC>; 411 reset-names = "serial"; 412 status = "disabled"; 413 }; 414 415 uartg: serial@c290000 { 416 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 417 reg = <0x0c290000 0x40>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&bpmp TEGRA194_CLK_UARTG>; 421 clock-names = "serial"; 422 resets = <&bpmp TEGRA194_RESET_UARTG>; 423 reset-names = "serial"; 424 status = "disabled"; 425 }; 426 427 rtc: rtc@c2a0000 { 428 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 429 reg = <0x0c2a0000 0x10000>; 430 interrupt-parent = <&pmc>; 431 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 433 clock-names = "rtc"; 434 status = "disabled"; 435 }; 436 437 gpio_aon: gpio@c2f0000 { 438 compatible = "nvidia,tegra194-gpio-aon"; 439 reg-names = "security", "gpio"; 440 reg = <0xc2f0000 0x1000>, 441 <0xc2f1000 0x1000>; 442 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 452 pwm4: pwm@c340000 { 453 compatible = "nvidia,tegra194-pwm", 454 "nvidia,tegra186-pwm"; 455 reg = <0xc340000 0x10000>; 456 clocks = <&bpmp TEGRA194_CLK_PWM4>; 457 clock-names = "pwm"; 458 resets = <&bpmp TEGRA194_RESET_PWM4>; 459 reset-names = "pwm"; 460 status = "disabled"; 461 #pwm-cells = <2>; 462 }; 463 464 pmc: pmc@c360000 { 465 compatible = "nvidia,tegra194-pmc"; 466 reg = <0x0c360000 0x10000>, 467 <0x0c370000 0x10000>, 468 <0x0c380000 0x10000>, 469 <0x0c390000 0x10000>, 470 <0x0c3a0000 0x10000>; 471 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 472 473 #interrupt-cells = <2>; 474 interrupt-controller; 475 }; 476 477 host1x@13e00000 { 478 compatible = "nvidia,tegra194-host1x", "simple-bus"; 479 reg = <0x13e00000 0x10000>, 480 <0x13e10000 0x10000>; 481 reg-names = "hypervisor", "vm"; 482 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 485 clock-names = "host1x"; 486 resets = <&bpmp TEGRA194_RESET_HOST1X>; 487 reset-names = "host1x"; 488 489 #address-cells = <1>; 490 #size-cells = <1>; 491 492 ranges = <0x15000000 0x15000000 0x01000000>; 493 494 display-hub@15200000 { 495 compatible = "nvidia,tegra194-display", "simple-bus"; 496 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 497 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 498 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 499 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 500 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 501 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 502 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 503 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 504 "wgrp3", "wgrp4", "wgrp5"; 505 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 506 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 507 clock-names = "disp", "hub"; 508 status = "disabled"; 509 510 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 511 512 #address-cells = <1>; 513 #size-cells = <1>; 514 515 ranges = <0x15200000 0x15200000 0x40000>; 516 517 display@15200000 { 518 compatible = "nvidia,tegra194-dc"; 519 reg = <0x15200000 0x10000>; 520 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 522 clock-names = "dc"; 523 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 524 reset-names = "dc"; 525 526 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 527 528 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 529 nvidia,head = <0>; 530 }; 531 532 display@15210000 { 533 compatible = "nvidia,tegra194-dc"; 534 reg = <0x15210000 0x10000>; 535 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 537 clock-names = "dc"; 538 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 539 reset-names = "dc"; 540 541 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 542 543 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 544 nvidia,head = <1>; 545 }; 546 547 display@15220000 { 548 compatible = "nvidia,tegra194-dc"; 549 reg = <0x15220000 0x10000>; 550 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 552 clock-names = "dc"; 553 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 554 reset-names = "dc"; 555 556 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 557 558 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 559 nvidia,head = <2>; 560 }; 561 562 display@15230000 { 563 compatible = "nvidia,tegra194-dc"; 564 reg = <0x15230000 0x10000>; 565 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 567 clock-names = "dc"; 568 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 569 reset-names = "dc"; 570 571 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 572 573 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 574 nvidia,head = <3>; 575 }; 576 }; 577 578 vic@15340000 { 579 compatible = "nvidia,tegra194-vic"; 580 reg = <0x15340000 0x00040000>; 581 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA194_CLK_VIC>; 583 clock-names = "vic"; 584 resets = <&bpmp TEGRA194_RESET_VIC>; 585 reset-names = "vic"; 586 587 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 588 }; 589 590 dpaux0: dpaux@155c0000 { 591 compatible = "nvidia,tegra194-dpaux"; 592 reg = <0x155c0000 0x10000>; 593 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 595 <&bpmp TEGRA194_CLK_PLLDP>; 596 clock-names = "dpaux", "parent"; 597 resets = <&bpmp TEGRA194_RESET_DPAUX>; 598 reset-names = "dpaux"; 599 status = "disabled"; 600 601 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 602 603 state_dpaux0_aux: pinmux-aux { 604 groups = "dpaux-io"; 605 function = "aux"; 606 }; 607 608 state_dpaux0_i2c: pinmux-i2c { 609 groups = "dpaux-io"; 610 function = "i2c"; 611 }; 612 613 state_dpaux0_off: pinmux-off { 614 groups = "dpaux-io"; 615 function = "off"; 616 }; 617 618 i2c-bus { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 }; 622 }; 623 624 dpaux1: dpaux@155d0000 { 625 compatible = "nvidia,tegra194-dpaux"; 626 reg = <0x155d0000 0x10000>; 627 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 629 <&bpmp TEGRA194_CLK_PLLDP>; 630 clock-names = "dpaux", "parent"; 631 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 632 reset-names = "dpaux"; 633 status = "disabled"; 634 635 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 636 637 state_dpaux1_aux: pinmux-aux { 638 groups = "dpaux-io"; 639 function = "aux"; 640 }; 641 642 state_dpaux1_i2c: pinmux-i2c { 643 groups = "dpaux-io"; 644 function = "i2c"; 645 }; 646 647 state_dpaux1_off: pinmux-off { 648 groups = "dpaux-io"; 649 function = "off"; 650 }; 651 652 i2c-bus { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 }; 656 }; 657 658 dpaux2: dpaux@155e0000 { 659 compatible = "nvidia,tegra194-dpaux"; 660 reg = <0x155e0000 0x10000>; 661 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 663 <&bpmp TEGRA194_CLK_PLLDP>; 664 clock-names = "dpaux", "parent"; 665 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 666 reset-names = "dpaux"; 667 status = "disabled"; 668 669 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 670 671 state_dpaux2_aux: pinmux-aux { 672 groups = "dpaux-io"; 673 function = "aux"; 674 }; 675 676 state_dpaux2_i2c: pinmux-i2c { 677 groups = "dpaux-io"; 678 function = "i2c"; 679 }; 680 681 state_dpaux2_off: pinmux-off { 682 groups = "dpaux-io"; 683 function = "off"; 684 }; 685 686 i2c-bus { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 }; 690 }; 691 692 dpaux3: dpaux@155f0000 { 693 compatible = "nvidia,tegra194-dpaux"; 694 reg = <0x155f0000 0x10000>; 695 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 697 <&bpmp TEGRA194_CLK_PLLDP>; 698 clock-names = "dpaux", "parent"; 699 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 700 reset-names = "dpaux"; 701 status = "disabled"; 702 703 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 704 705 state_dpaux3_aux: pinmux-aux { 706 groups = "dpaux-io"; 707 function = "aux"; 708 }; 709 710 state_dpaux3_i2c: pinmux-i2c { 711 groups = "dpaux-io"; 712 function = "i2c"; 713 }; 714 715 state_dpaux3_off: pinmux-off { 716 groups = "dpaux-io"; 717 function = "off"; 718 }; 719 720 i2c-bus { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 }; 724 }; 725 726 sor0: sor@15b00000 { 727 compatible = "nvidia,tegra194-sor"; 728 reg = <0x15b00000 0x40000>; 729 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 731 <&bpmp TEGRA194_CLK_SOR0_OUT>, 732 <&bpmp TEGRA194_CLK_PLLD>, 733 <&bpmp TEGRA194_CLK_PLLDP>, 734 <&bpmp TEGRA194_CLK_SOR_SAFE>, 735 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 736 clock-names = "sor", "out", "parent", "dp", "safe", 737 "pad"; 738 resets = <&bpmp TEGRA194_RESET_SOR0>; 739 reset-names = "sor"; 740 pinctrl-0 = <&state_dpaux0_aux>; 741 pinctrl-1 = <&state_dpaux0_i2c>; 742 pinctrl-2 = <&state_dpaux0_off>; 743 pinctrl-names = "aux", "i2c", "off"; 744 status = "disabled"; 745 746 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 747 nvidia,interface = <0>; 748 }; 749 750 sor1: sor@15b40000 { 751 compatible = "nvidia,tegra194-sor"; 752 reg = <0x155c0000 0x40000>; 753 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 755 <&bpmp TEGRA194_CLK_SOR1_OUT>, 756 <&bpmp TEGRA194_CLK_PLLD2>, 757 <&bpmp TEGRA194_CLK_PLLDP>, 758 <&bpmp TEGRA194_CLK_SOR_SAFE>, 759 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 760 clock-names = "sor", "out", "parent", "dp", "safe", 761 "pad"; 762 resets = <&bpmp TEGRA194_RESET_SOR1>; 763 reset-names = "sor"; 764 pinctrl-0 = <&state_dpaux1_aux>; 765 pinctrl-1 = <&state_dpaux1_i2c>; 766 pinctrl-2 = <&state_dpaux1_off>; 767 pinctrl-names = "aux", "i2c", "off"; 768 status = "disabled"; 769 770 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 771 nvidia,interface = <1>; 772 }; 773 774 sor2: sor@15b80000 { 775 compatible = "nvidia,tegra194-sor"; 776 reg = <0x15b80000 0x40000>; 777 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 779 <&bpmp TEGRA194_CLK_SOR2_OUT>, 780 <&bpmp TEGRA194_CLK_PLLD3>, 781 <&bpmp TEGRA194_CLK_PLLDP>, 782 <&bpmp TEGRA194_CLK_SOR_SAFE>, 783 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 784 clock-names = "sor", "out", "parent", "dp", "safe", 785 "pad"; 786 resets = <&bpmp TEGRA194_RESET_SOR2>; 787 reset-names = "sor"; 788 pinctrl-0 = <&state_dpaux2_aux>; 789 pinctrl-1 = <&state_dpaux2_i2c>; 790 pinctrl-2 = <&state_dpaux2_off>; 791 pinctrl-names = "aux", "i2c", "off"; 792 status = "disabled"; 793 794 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 795 nvidia,interface = <2>; 796 }; 797 798 sor3: sor@15bc0000 { 799 compatible = "nvidia,tegra194-sor"; 800 reg = <0x15bc0000 0x40000>; 801 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 803 <&bpmp TEGRA194_CLK_SOR3_OUT>, 804 <&bpmp TEGRA194_CLK_PLLD4>, 805 <&bpmp TEGRA194_CLK_PLLDP>, 806 <&bpmp TEGRA194_CLK_SOR_SAFE>, 807 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 808 clock-names = "sor", "out", "parent", "dp", "safe", 809 "pad"; 810 resets = <&bpmp TEGRA194_RESET_SOR3>; 811 reset-names = "sor"; 812 pinctrl-0 = <&state_dpaux3_aux>; 813 pinctrl-1 = <&state_dpaux3_i2c>; 814 pinctrl-2 = <&state_dpaux3_off>; 815 pinctrl-names = "aux", "i2c", "off"; 816 status = "disabled"; 817 818 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 819 nvidia,interface = <3>; 820 }; 821 }; 822 }; 823 824 sysram@40000000 { 825 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 826 reg = <0x0 0x40000000 0x0 0x50000>; 827 #address-cells = <1>; 828 #size-cells = <1>; 829 ranges = <0x0 0x0 0x40000000 0x50000>; 830 831 cpu_bpmp_tx: shmem@4e000 { 832 compatible = "nvidia,tegra194-bpmp-shmem"; 833 reg = <0x4e000 0x1000>; 834 label = "cpu-bpmp-tx"; 835 pool; 836 }; 837 838 cpu_bpmp_rx: shmem@4f000 { 839 compatible = "nvidia,tegra194-bpmp-shmem"; 840 reg = <0x4f000 0x1000>; 841 label = "cpu-bpmp-rx"; 842 pool; 843 }; 844 }; 845 846 bpmp: bpmp { 847 compatible = "nvidia,tegra186-bpmp"; 848 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 849 TEGRA_HSP_DB_MASTER_BPMP>; 850 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 851 #clock-cells = <1>; 852 #reset-cells = <1>; 853 #power-domain-cells = <1>; 854 855 bpmp_i2c: i2c { 856 compatible = "nvidia,tegra186-bpmp-i2c"; 857 nvidia,bpmp-bus-id = <5>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 }; 861 862 bpmp_thermal: thermal { 863 compatible = "nvidia,tegra186-bpmp-thermal"; 864 #thermal-sensor-cells = <1>; 865 }; 866 }; 867 868 cpus { 869 #address-cells = <1>; 870 #size-cells = <0>; 871 872 cpu@0 { 873 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 874 device_type = "cpu"; 875 reg = <0x10000>; 876 enable-method = "psci"; 877 }; 878 879 cpu@1 { 880 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 881 device_type = "cpu"; 882 reg = <0x10001>; 883 enable-method = "psci"; 884 }; 885 886 cpu@2 { 887 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 888 device_type = "cpu"; 889 reg = <0x100>; 890 enable-method = "psci"; 891 }; 892 893 cpu@3 { 894 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 895 device_type = "cpu"; 896 reg = <0x101>; 897 enable-method = "psci"; 898 }; 899 900 cpu@4 { 901 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 902 device_type = "cpu"; 903 reg = <0x200>; 904 enable-method = "psci"; 905 }; 906 907 cpu@5 { 908 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 909 device_type = "cpu"; 910 reg = <0x201>; 911 enable-method = "psci"; 912 }; 913 914 cpu@6 { 915 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 916 device_type = "cpu"; 917 reg = <0x10300>; 918 enable-method = "psci"; 919 }; 920 921 cpu@7 { 922 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 923 device_type = "cpu"; 924 reg = <0x10301>; 925 enable-method = "psci"; 926 }; 927 }; 928 929 psci { 930 compatible = "arm,psci-1.0"; 931 status = "okay"; 932 method = "smc"; 933 }; 934 935 thermal-zones { 936 cpu { 937 thermal-sensors = <&{/bpmp/thermal} 938 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 939 status = "disabled"; 940 }; 941 942 gpu { 943 thermal-sensors = <&{/bpmp/thermal} 944 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 945 status = "disabled"; 946 }; 947 948 aux { 949 thermal-sensors = <&{/bpmp/thermal} 950 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 951 status = "disabled"; 952 }; 953 954 pllx { 955 thermal-sensors = <&{/bpmp/thermal} 956 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 957 status = "disabled"; 958 }; 959 960 ao { 961 thermal-sensors = <&{/bpmp/thermal} 962 TEGRA194_BPMP_THERMAL_ZONE_AO>; 963 status = "disabled"; 964 }; 965 966 tj { 967 thermal-sensors = <&{/bpmp/thermal} 968 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 969 status = "disabled"; 970 }; 971 }; 972 973 timer { 974 compatible = "arm,armv8-timer"; 975 interrupts = <GIC_PPI 13 976 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 977 <GIC_PPI 14 978 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 979 <GIC_PPI 11 980 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 981 <GIC_PPI 10 982 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 983 interrupt-parent = <&gic>; 984 }; 985}; 986