1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/reset/tegra194-reset.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 9 10/ { 11 compatible = "nvidia,tegra194"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* control backbone */ 17 cbb { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x0 0x40000000>; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra194-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x2200000 0x10000>, 27 <0x2210000 0x10000>; 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x02490000 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46 <&bpmp TEGRA194_CLK_EQOS_AXI>, 47 <&bpmp TEGRA194_CLK_EQOS_RX>, 48 <&bpmp TEGRA194_CLK_EQOS_TX>, 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA194_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <16>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 64 reg = <0x03100000 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA194_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA194_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 76 reg = <0x03110000 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA194_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA194_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 88 reg = <0x03130000 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA194_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA194_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 100 reg = <0x03140000 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA194_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA194_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 112 reg = <0x03150000 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA194_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA194_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra194-i2c"; 124 reg = <0x03160000 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA194_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA194_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 uarth: serial@3170000 { 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 137 reg = <0x03170000 0x40>; 138 reg-shift = <2>; 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA194_CLK_UARTH>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA194_RESET_UARTH>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 cam_i2c: i2c@3180000 { 148 compatible = "nvidia,tegra194-i2c"; 149 reg = <0x03180000 0x10000>; 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&bpmp TEGRA194_CLK_I2C3>; 154 clock-names = "div-clk"; 155 resets = <&bpmp TEGRA194_RESET_I2C3>; 156 reset-names = "i2c"; 157 status = "disabled"; 158 }; 159 160 /* shares pads with dpaux1 */ 161 dp_aux_ch1_i2c: i2c@3190000 { 162 compatible = "nvidia,tegra194-i2c"; 163 reg = <0x03190000 0x10000>; 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&bpmp TEGRA194_CLK_I2C4>; 168 clock-names = "div-clk"; 169 resets = <&bpmp TEGRA194_RESET_I2C4>; 170 reset-names = "i2c"; 171 status = "disabled"; 172 }; 173 174 /* shares pads with dpaux0 */ 175 dp_aux_ch0_i2c: i2c@31b0000 { 176 compatible = "nvidia,tegra194-i2c"; 177 reg = <0x031b0000 0x10000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA194_CLK_I2C6>; 182 clock-names = "div-clk"; 183 resets = <&bpmp TEGRA194_RESET_I2C6>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gen7_i2c: i2c@31c0000 { 189 compatible = "nvidia,tegra194-i2c"; 190 reg = <0x031c0000 0x10000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clocks = <&bpmp TEGRA194_CLK_I2C7>; 195 clock-names = "div-clk"; 196 resets = <&bpmp TEGRA194_RESET_I2C7>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 gen9_i2c: i2c@31e0000 { 202 compatible = "nvidia,tegra194-i2c"; 203 reg = <0x031e0000 0x10000>; 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&bpmp TEGRA194_CLK_I2C9>; 208 clock-names = "div-clk"; 209 resets = <&bpmp TEGRA194_RESET_I2C9>; 210 reset-names = "i2c"; 211 status = "disabled"; 212 }; 213 214 pwm1: pwm@3280000 { 215 compatible = "nvidia,tegra194-pwm", 216 "nvidia,tegra186-pwm"; 217 reg = <0x3280000 0x10000>; 218 clocks = <&bpmp TEGRA194_CLK_PWM1>; 219 clock-names = "pwm"; 220 resets = <&bpmp TEGRA194_RESET_PWM1>; 221 reset-names = "pwm"; 222 status = "disabled"; 223 #pwm-cells = <2>; 224 }; 225 226 pwm2: pwm@3290000 { 227 compatible = "nvidia,tegra194-pwm", 228 "nvidia,tegra186-pwm"; 229 reg = <0x3290000 0x10000>; 230 clocks = <&bpmp TEGRA194_CLK_PWM2>; 231 clock-names = "pwm"; 232 resets = <&bpmp TEGRA194_RESET_PWM2>; 233 reset-names = "pwm"; 234 status = "disabled"; 235 #pwm-cells = <2>; 236 }; 237 238 pwm3: pwm@32a0000 { 239 compatible = "nvidia,tegra194-pwm", 240 "nvidia,tegra186-pwm"; 241 reg = <0x32a0000 0x10000>; 242 clocks = <&bpmp TEGRA194_CLK_PWM3>; 243 clock-names = "pwm"; 244 resets = <&bpmp TEGRA194_RESET_PWM3>; 245 reset-names = "pwm"; 246 status = "disabled"; 247 #pwm-cells = <2>; 248 }; 249 250 pwm5: pwm@32c0000 { 251 compatible = "nvidia,tegra194-pwm", 252 "nvidia,tegra186-pwm"; 253 reg = <0x32c0000 0x10000>; 254 clocks = <&bpmp TEGRA194_CLK_PWM5>; 255 clock-names = "pwm"; 256 resets = <&bpmp TEGRA194_RESET_PWM5>; 257 reset-names = "pwm"; 258 status = "disabled"; 259 #pwm-cells = <2>; 260 }; 261 262 pwm6: pwm@32d0000 { 263 compatible = "nvidia,tegra194-pwm", 264 "nvidia,tegra186-pwm"; 265 reg = <0x32d0000 0x10000>; 266 clocks = <&bpmp TEGRA194_CLK_PWM6>; 267 clock-names = "pwm"; 268 resets = <&bpmp TEGRA194_RESET_PWM6>; 269 reset-names = "pwm"; 270 status = "disabled"; 271 #pwm-cells = <2>; 272 }; 273 274 pwm7: pwm@32e0000 { 275 compatible = "nvidia,tegra194-pwm", 276 "nvidia,tegra186-pwm"; 277 reg = <0x32e0000 0x10000>; 278 clocks = <&bpmp TEGRA194_CLK_PWM7>; 279 clock-names = "pwm"; 280 resets = <&bpmp TEGRA194_RESET_PWM7>; 281 reset-names = "pwm"; 282 status = "disabled"; 283 #pwm-cells = <2>; 284 }; 285 286 pwm8: pwm@32f0000 { 287 compatible = "nvidia,tegra194-pwm", 288 "nvidia,tegra186-pwm"; 289 reg = <0x32f0000 0x10000>; 290 clocks = <&bpmp TEGRA194_CLK_PWM8>; 291 clock-names = "pwm"; 292 resets = <&bpmp TEGRA194_RESET_PWM8>; 293 reset-names = "pwm"; 294 status = "disabled"; 295 #pwm-cells = <2>; 296 }; 297 298 sdmmc1: sdhci@3400000 { 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 300 reg = <0x03400000 0x10000>; 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 303 clock-names = "sdhci"; 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 305 reset-names = "sdhci"; 306 status = "disabled"; 307 }; 308 309 sdmmc3: sdhci@3440000 { 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 311 reg = <0x03440000 0x10000>; 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 316 reset-names = "sdhci"; 317 status = "disabled"; 318 }; 319 320 sdmmc4: sdhci@3460000 { 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 322 reg = <0x03460000 0x10000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 325 clock-names = "sdhci"; 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 327 reset-names = "sdhci"; 328 status = "disabled"; 329 }; 330 331 hda@3510000 { 332 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 333 reg = <0x3510000 0x10000>; 334 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&bpmp TEGRA194_CLK_HDA>, 336 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 337 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 338 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 339 resets = <&bpmp TEGRA194_RESET_HDA>, 340 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 341 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 342 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 343 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 344 status = "disabled"; 345 }; 346 347 gic: interrupt-controller@3881000 { 348 compatible = "arm,gic-400"; 349 #interrupt-cells = <3>; 350 interrupt-controller; 351 reg = <0x03881000 0x1000>, 352 <0x03882000 0x2000>, 353 <0x03884000 0x2000>, 354 <0x03886000 0x2000>; 355 interrupts = <GIC_PPI 9 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 357 interrupt-parent = <&gic>; 358 }; 359 360 hsp_top0: hsp@3c00000 { 361 compatible = "nvidia,tegra186-hsp"; 362 reg = <0x03c00000 0xa0000>; 363 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 364 interrupt-names = "doorbell"; 365 #mbox-cells = <2>; 366 }; 367 368 gen2_i2c: i2c@c240000 { 369 compatible = "nvidia,tegra194-i2c"; 370 reg = <0x0c240000 0x10000>; 371 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 clocks = <&bpmp TEGRA194_CLK_I2C2>; 375 clock-names = "div-clk"; 376 resets = <&bpmp TEGRA194_RESET_I2C2>; 377 reset-names = "i2c"; 378 status = "disabled"; 379 }; 380 381 gen8_i2c: i2c@c250000 { 382 compatible = "nvidia,tegra194-i2c"; 383 reg = <0x0c250000 0x10000>; 384 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&bpmp TEGRA194_CLK_I2C8>; 388 clock-names = "div-clk"; 389 resets = <&bpmp TEGRA194_RESET_I2C8>; 390 reset-names = "i2c"; 391 status = "disabled"; 392 }; 393 394 uartc: serial@c280000 { 395 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 396 reg = <0x0c280000 0x40>; 397 reg-shift = <2>; 398 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&bpmp TEGRA194_CLK_UARTC>; 400 clock-names = "serial"; 401 resets = <&bpmp TEGRA194_RESET_UARTC>; 402 reset-names = "serial"; 403 status = "disabled"; 404 }; 405 406 uartg: serial@c290000 { 407 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 408 reg = <0x0c290000 0x40>; 409 reg-shift = <2>; 410 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&bpmp TEGRA194_CLK_UARTG>; 412 clock-names = "serial"; 413 resets = <&bpmp TEGRA194_RESET_UARTG>; 414 reset-names = "serial"; 415 status = "disabled"; 416 }; 417 418 rtc: rtc@c2a0000 { 419 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 420 reg = <0x0c2a0000 0x10000>; 421 interrupt-parent = <&pmc>; 422 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 424 clock-names = "rtc"; 425 status = "disabled"; 426 }; 427 428 gpio_aon: gpio@c2f0000 { 429 compatible = "nvidia,tegra194-gpio-aon"; 430 reg-names = "security", "gpio"; 431 reg = <0xc2f0000 0x1000>, 432 <0xc2f1000 0x1000>; 433 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 443 pwm4: pwm@c340000 { 444 compatible = "nvidia,tegra194-pwm", 445 "nvidia,tegra186-pwm"; 446 reg = <0xc340000 0x10000>; 447 clocks = <&bpmp TEGRA194_CLK_PWM4>; 448 clock-names = "pwm"; 449 resets = <&bpmp TEGRA194_RESET_PWM4>; 450 reset-names = "pwm"; 451 status = "disabled"; 452 #pwm-cells = <2>; 453 }; 454 455 pmc: pmc@c360000 { 456 compatible = "nvidia,tegra194-pmc"; 457 reg = <0x0c360000 0x10000>, 458 <0x0c370000 0x10000>, 459 <0x0c380000 0x10000>, 460 <0x0c390000 0x10000>, 461 <0x0c3a0000 0x10000>; 462 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 463 464 #interrupt-cells = <2>; 465 interrupt-controller; 466 }; 467 468 host1x@13e00000 { 469 compatible = "nvidia,tegra194-host1x", "simple-bus"; 470 reg = <0x13e00000 0x10000>, 471 <0x13e10000 0x10000>; 472 reg-names = "hypervisor", "vm"; 473 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 476 clock-names = "host1x"; 477 resets = <&bpmp TEGRA194_RESET_HOST1X>; 478 reset-names = "host1x"; 479 480 #address-cells = <1>; 481 #size-cells = <1>; 482 483 ranges = <0x15000000 0x15000000 0x01000000>; 484 485 display-hub@15200000 { 486 compatible = "nvidia,tegra194-display", "simple-bus"; 487 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 488 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 489 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 490 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 491 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 492 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 493 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 494 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 495 "wgrp3", "wgrp4", "wgrp5"; 496 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 497 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 498 clock-names = "disp", "hub"; 499 status = "disabled"; 500 501 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 502 503 #address-cells = <1>; 504 #size-cells = <1>; 505 506 ranges = <0x15200000 0x15200000 0x40000>; 507 508 display@15200000 { 509 compatible = "nvidia,tegra194-dc"; 510 reg = <0x15200000 0x10000>; 511 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 513 clock-names = "dc"; 514 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 515 reset-names = "dc"; 516 517 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 518 519 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 520 nvidia,head = <0>; 521 }; 522 523 display@15210000 { 524 compatible = "nvidia,tegra194-dc"; 525 reg = <0x15210000 0x10000>; 526 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 528 clock-names = "dc"; 529 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 530 reset-names = "dc"; 531 532 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 533 534 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 535 nvidia,head = <1>; 536 }; 537 538 display@15220000 { 539 compatible = "nvidia,tegra194-dc"; 540 reg = <0x15220000 0x10000>; 541 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 543 clock-names = "dc"; 544 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 545 reset-names = "dc"; 546 547 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 548 549 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 550 nvidia,head = <2>; 551 }; 552 553 display@15230000 { 554 compatible = "nvidia,tegra194-dc"; 555 reg = <0x15230000 0x10000>; 556 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 558 clock-names = "dc"; 559 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 560 reset-names = "dc"; 561 562 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 563 564 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 565 nvidia,head = <3>; 566 }; 567 }; 568 569 vic@15340000 { 570 compatible = "nvidia,tegra194-vic"; 571 reg = <0x15340000 0x00040000>; 572 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&bpmp TEGRA194_CLK_VIC>; 574 clock-names = "vic"; 575 resets = <&bpmp TEGRA194_RESET_VIC>; 576 reset-names = "vic"; 577 578 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 579 }; 580 581 dpaux0: dpaux@155c0000 { 582 compatible = "nvidia,tegra194-dpaux"; 583 reg = <0x155c0000 0x10000>; 584 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 586 <&bpmp TEGRA194_CLK_PLLDP>; 587 clock-names = "dpaux", "parent"; 588 resets = <&bpmp TEGRA194_RESET_DPAUX>; 589 reset-names = "dpaux"; 590 status = "disabled"; 591 592 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 593 594 state_dpaux0_aux: pinmux-aux { 595 groups = "dpaux-io"; 596 function = "aux"; 597 }; 598 599 state_dpaux0_i2c: pinmux-i2c { 600 groups = "dpaux-io"; 601 function = "i2c"; 602 }; 603 604 state_dpaux0_off: pinmux-off { 605 groups = "dpaux-io"; 606 function = "off"; 607 }; 608 609 i2c-bus { 610 #address-cells = <1>; 611 #size-cells = <0>; 612 }; 613 }; 614 615 dpaux1: dpaux@155d0000 { 616 compatible = "nvidia,tegra194-dpaux"; 617 reg = <0x155d0000 0x10000>; 618 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 620 <&bpmp TEGRA194_CLK_PLLDP>; 621 clock-names = "dpaux", "parent"; 622 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 623 reset-names = "dpaux"; 624 status = "disabled"; 625 626 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 627 628 state_dpaux1_aux: pinmux-aux { 629 groups = "dpaux-io"; 630 function = "aux"; 631 }; 632 633 state_dpaux1_i2c: pinmux-i2c { 634 groups = "dpaux-io"; 635 function = "i2c"; 636 }; 637 638 state_dpaux1_off: pinmux-off { 639 groups = "dpaux-io"; 640 function = "off"; 641 }; 642 643 i2c-bus { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 }; 647 }; 648 649 dpaux2: dpaux@155e0000 { 650 compatible = "nvidia,tegra194-dpaux"; 651 reg = <0x155e0000 0x10000>; 652 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 654 <&bpmp TEGRA194_CLK_PLLDP>; 655 clock-names = "dpaux", "parent"; 656 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 657 reset-names = "dpaux"; 658 status = "disabled"; 659 660 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 661 662 state_dpaux2_aux: pinmux-aux { 663 groups = "dpaux-io"; 664 function = "aux"; 665 }; 666 667 state_dpaux2_i2c: pinmux-i2c { 668 groups = "dpaux-io"; 669 function = "i2c"; 670 }; 671 672 state_dpaux2_off: pinmux-off { 673 groups = "dpaux-io"; 674 function = "off"; 675 }; 676 677 i2c-bus { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 }; 681 }; 682 683 dpaux3: dpaux@155f0000 { 684 compatible = "nvidia,tegra194-dpaux"; 685 reg = <0x155f0000 0x10000>; 686 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 688 <&bpmp TEGRA194_CLK_PLLDP>; 689 clock-names = "dpaux", "parent"; 690 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 691 reset-names = "dpaux"; 692 status = "disabled"; 693 694 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 695 696 state_dpaux3_aux: pinmux-aux { 697 groups = "dpaux-io"; 698 function = "aux"; 699 }; 700 701 state_dpaux3_i2c: pinmux-i2c { 702 groups = "dpaux-io"; 703 function = "i2c"; 704 }; 705 706 state_dpaux3_off: pinmux-off { 707 groups = "dpaux-io"; 708 function = "off"; 709 }; 710 711 i2c-bus { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 }; 715 }; 716 717 sor0: sor@15b00000 { 718 compatible = "nvidia,tegra194-sor"; 719 reg = <0x15b00000 0x40000>; 720 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 722 <&bpmp TEGRA194_CLK_SOR0_OUT>, 723 <&bpmp TEGRA194_CLK_PLLD>, 724 <&bpmp TEGRA194_CLK_PLLDP>, 725 <&bpmp TEGRA194_CLK_SOR_SAFE>, 726 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 727 clock-names = "sor", "out", "parent", "dp", "safe", 728 "pad"; 729 resets = <&bpmp TEGRA194_RESET_SOR0>; 730 reset-names = "sor"; 731 pinctrl-0 = <&state_dpaux0_aux>; 732 pinctrl-1 = <&state_dpaux0_i2c>; 733 pinctrl-2 = <&state_dpaux0_off>; 734 pinctrl-names = "aux", "i2c", "off"; 735 status = "disabled"; 736 737 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 738 nvidia,interface = <0>; 739 }; 740 741 sor1: sor@15b40000 { 742 compatible = "nvidia,tegra194-sor"; 743 reg = <0x155c0000 0x40000>; 744 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 746 <&bpmp TEGRA194_CLK_SOR1_OUT>, 747 <&bpmp TEGRA194_CLK_PLLD2>, 748 <&bpmp TEGRA194_CLK_PLLDP>, 749 <&bpmp TEGRA194_CLK_SOR_SAFE>, 750 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 751 clock-names = "sor", "out", "parent", "dp", "safe", 752 "pad"; 753 resets = <&bpmp TEGRA194_RESET_SOR1>; 754 reset-names = "sor"; 755 pinctrl-0 = <&state_dpaux1_aux>; 756 pinctrl-1 = <&state_dpaux1_i2c>; 757 pinctrl-2 = <&state_dpaux1_off>; 758 pinctrl-names = "aux", "i2c", "off"; 759 status = "disabled"; 760 761 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 762 nvidia,interface = <1>; 763 }; 764 765 sor2: sor@15b80000 { 766 compatible = "nvidia,tegra194-sor"; 767 reg = <0x15b80000 0x40000>; 768 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 770 <&bpmp TEGRA194_CLK_SOR2_OUT>, 771 <&bpmp TEGRA194_CLK_PLLD3>, 772 <&bpmp TEGRA194_CLK_PLLDP>, 773 <&bpmp TEGRA194_CLK_SOR_SAFE>, 774 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 775 clock-names = "sor", "out", "parent", "dp", "safe", 776 "pad"; 777 resets = <&bpmp TEGRA194_RESET_SOR2>; 778 reset-names = "sor"; 779 pinctrl-0 = <&state_dpaux2_aux>; 780 pinctrl-1 = <&state_dpaux2_i2c>; 781 pinctrl-2 = <&state_dpaux2_off>; 782 pinctrl-names = "aux", "i2c", "off"; 783 status = "disabled"; 784 785 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 786 nvidia,interface = <2>; 787 }; 788 789 sor3: sor@15bc0000 { 790 compatible = "nvidia,tegra194-sor"; 791 reg = <0x15bc0000 0x40000>; 792 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 794 <&bpmp TEGRA194_CLK_SOR3_OUT>, 795 <&bpmp TEGRA194_CLK_PLLD4>, 796 <&bpmp TEGRA194_CLK_PLLDP>, 797 <&bpmp TEGRA194_CLK_SOR_SAFE>, 798 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 799 clock-names = "sor", "out", "parent", "dp", "safe", 800 "pad"; 801 resets = <&bpmp TEGRA194_RESET_SOR3>; 802 reset-names = "sor"; 803 pinctrl-0 = <&state_dpaux3_aux>; 804 pinctrl-1 = <&state_dpaux3_i2c>; 805 pinctrl-2 = <&state_dpaux3_off>; 806 pinctrl-names = "aux", "i2c", "off"; 807 status = "disabled"; 808 809 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 810 nvidia,interface = <3>; 811 }; 812 }; 813 }; 814 815 sysram@40000000 { 816 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 817 reg = <0x0 0x40000000 0x0 0x50000>; 818 #address-cells = <1>; 819 #size-cells = <1>; 820 ranges = <0x0 0x0 0x40000000 0x50000>; 821 822 cpu_bpmp_tx: shmem@4e000 { 823 compatible = "nvidia,tegra194-bpmp-shmem"; 824 reg = <0x4e000 0x1000>; 825 label = "cpu-bpmp-tx"; 826 pool; 827 }; 828 829 cpu_bpmp_rx: shmem@4f000 { 830 compatible = "nvidia,tegra194-bpmp-shmem"; 831 reg = <0x4f000 0x1000>; 832 label = "cpu-bpmp-rx"; 833 pool; 834 }; 835 }; 836 837 bpmp: bpmp { 838 compatible = "nvidia,tegra186-bpmp"; 839 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 840 TEGRA_HSP_DB_MASTER_BPMP>; 841 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 842 #clock-cells = <1>; 843 #reset-cells = <1>; 844 #power-domain-cells = <1>; 845 846 bpmp_i2c: i2c { 847 compatible = "nvidia,tegra186-bpmp-i2c"; 848 nvidia,bpmp-bus-id = <5>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 }; 852 853 bpmp_thermal: thermal { 854 compatible = "nvidia,tegra186-bpmp-thermal"; 855 #thermal-sensor-cells = <1>; 856 }; 857 }; 858 859 cpus { 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 cpu@0 { 864 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 865 device_type = "cpu"; 866 reg = <0x10000>; 867 enable-method = "psci"; 868 }; 869 870 cpu@1 { 871 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 872 device_type = "cpu"; 873 reg = <0x10001>; 874 enable-method = "psci"; 875 }; 876 877 cpu@2 { 878 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 879 device_type = "cpu"; 880 reg = <0x100>; 881 enable-method = "psci"; 882 }; 883 884 cpu@3 { 885 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 886 device_type = "cpu"; 887 reg = <0x101>; 888 enable-method = "psci"; 889 }; 890 891 cpu@4 { 892 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 893 device_type = "cpu"; 894 reg = <0x200>; 895 enable-method = "psci"; 896 }; 897 898 cpu@5 { 899 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 900 device_type = "cpu"; 901 reg = <0x201>; 902 enable-method = "psci"; 903 }; 904 905 cpu@6 { 906 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 907 device_type = "cpu"; 908 reg = <0x10300>; 909 enable-method = "psci"; 910 }; 911 912 cpu@7 { 913 compatible = "nvidia,tegra194-carmel", "arm,armv8"; 914 device_type = "cpu"; 915 reg = <0x10301>; 916 enable-method = "psci"; 917 }; 918 }; 919 920 psci { 921 compatible = "arm,psci-1.0"; 922 status = "okay"; 923 method = "smc"; 924 }; 925 926 thermal-zones { 927 cpu { 928 thermal-sensors = <&{/bpmp/thermal} 929 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 930 status = "disabled"; 931 }; 932 933 gpu { 934 thermal-sensors = <&{/bpmp/thermal} 935 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 936 status = "disabled"; 937 }; 938 939 aux { 940 thermal-sensors = <&{/bpmp/thermal} 941 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 942 status = "disabled"; 943 }; 944 945 pllx { 946 thermal-sensors = <&{/bpmp/thermal} 947 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 948 status = "disabled"; 949 }; 950 951 ao { 952 thermal-sensors = <&{/bpmp/thermal} 953 TEGRA194_BPMP_THERMAL_ZONE_AO>; 954 status = "disabled"; 955 }; 956 957 tj { 958 thermal-sensors = <&{/bpmp/thermal} 959 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 960 status = "disabled"; 961 }; 962 }; 963 964 timer { 965 compatible = "arm,armv8-timer"; 966 interrupts = <GIC_PPI 13 967 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 968 <GIC_PPI 14 969 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 970 <GIC_PPI 11 971 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 972 <GIC_PPI 10 973 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 974 interrupt-parent = <&gic>; 975 }; 976}; 977