eb5c8539 | 30-May-2018 |
Alexey Brodkin <abrodkin@synopsys.com> |
ARC: Reset: Implement weak reset_cpu()
This will allow for board-specific implementation of reset. Default version will just stop execution with help of BRK instruction.
Signed-off-by: Alexey Brodk
ARC: Reset: Implement weak reset_cpu()
This will allow for board-specific implementation of reset. Default version will just stop execution with help of BRK instruction.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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8f187142 | 30-May-2018 |
Alexey Brodkin <abrodkin@synopsys.com> |
ARC: Reset: Use __builtin_arc_brk() instead of open-coded ASM
For quite some time we have a GCC's built-in which inserts BRK instruction so let's use it instead of simple insertion of in-line assemb
ARC: Reset: Use __builtin_arc_brk() instead of open-coded ASM
For quite some time we have a GCC's built-in which inserts BRK instruction so let's use it instead of simple insertion of in-line assembly.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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ce307128 | 29-May-2018 |
Alexey Brodkin <abrodkin@synopsys.com> |
ARC: Improve relocation fix-ups
We used to have the one and only linker script for all ARC boards and so we relied on a particular order of symbols there.
Because of that we used __ivt_end as the m
ARC: Improve relocation fix-ups
We used to have the one and only linker script for all ARC boards and so we relied on a particular order of symbols there.
Because of that we used __ivt_end as the marker of the end of all the code which won't be true any longer if we move .ivt section to any other place. That said we'd better check for each section separately.
A couple of other improvements: 1. There's no point to include the marker of section end in interested range because its address is beyond the section, i.e. we should compare with "<" but not "<=".
2. .ivt section for ARCv2 cores is just an array of 32-bit ints and they are not swapped even on little-endia cores while in case of ARCompact cores .ivt contains valid code so swapping is required.
3. Just in case add check for ARC600 which is also ARCompact and its .ivt is normal code.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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6b85b26e | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Refactor arc_ioc_setup()
Move all checks before cache flush and IOC setup.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys
ARC: Cache: Refactor arc_ioc_setup()
Move all checks before cache flush and IOC setup.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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9f0253c6 | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Add missing cache cleanup before cache disable
Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Flush and invalidate SLC before L1 D$ di
ARC: Cache: Add missing cache cleanup before cache disable
Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Flush and invalidate SLC before L1 D$ disabling (as it will be bypassed for data) Otherwise we can lose some data when we disable L1 D$ if this data isn't flushed to next level cache. Or we can get wrong data if L1 D$ has some entries after enable which we modified when the L1 D$ was disabled. * Invalidate L1 I$ before disabling. Otherwise we can execute wrong instructions after L1 I$ enable if we modified any code when L1 I$ was disabled.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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7241944a | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Add more HW configuration checks
Add additional cache configuration checks and note about supported configurations.
It is unlikely to face some configuration in real life but it's bette
ARC: Cache: Add more HW configuration checks
Add additional cache configuration checks and note about supported configurations.
It is unlikely to face some configuration in real life but it's better to be prepared and refuse to work on those.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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375945ba | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Implement a function to sync and cleanup caches
Implement specialized function to clenup caches (and therefore sync instruction and data caches) which can be used for cleanup before linux launc
ARC: Implement a function to sync and cleanup caches
Implement specialized function to clenup caches (and therefore sync instruction and data caches) which can be used for cleanup before linux launch or to sync caches during U-Boot self-relocation.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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95336738 | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Fix SLC operations when SLC is bypassed for data
If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory.
If L1 I$ is disabled SLC is
ARC: Cache: Fix SLC operations when SLC is bypassed for data
If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory.
If L1 I$ is disabled SLC is NOT bypassed for instructions and all instruction requests are fetched through SLC.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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c75eeb0b | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Implement [i,d]cache_enabled() as separate functions
Implement icache_enabled() and dcache_enabled() as separate functions which can be used with "inline" attribute. This is a preparatio
ARC: Cache: Implement [i,d]cache_enabled() as separate functions
Implement icache_enabled() and dcache_enabled() as separate functions which can be used with "inline" attribute. This is a preparation to make them always_inline.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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246ba284 | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Move PAE exists check into slc_upper_region_init()
Move check for PAE existence into slc_upper_region_init() instead of its caller as more appropriate place.
Signed-off-by: Eugeniy Palt
ARC: Cache: Move PAE exists check into slc_upper_region_init()
Move check for PAE existence into slc_upper_region_init() instead of its caller as more appropriate place.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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bf8974ed | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Move cache global variables to arch_global_data
There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these varia
ARC: Move cache global variables to arch_global_data
There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these variables get overwritten when we copy .data section from ROM.
Instead we move these global variables into our "global data" structure so that we may really start from ROM.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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75790873 | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Get rid of [slc,pae,icache,dcache]_exists global variables
There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initializati
ARC: Cache: Get rid of [slc,pae,icache,dcache]_exists global variables
There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these variables get overwritten when we copy .data section from ROM.
Instead we'll use icache_exists(), dcache_exists(), slc_exists(), pae_exists() functions which directly check BCRs every time.
In U-Boot case ops are used only during self-relocation and DMA so we shouldn't be hit by noticeable performance degradation.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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ea9f6f1e | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Move SLC status check into slc_entire_op() and slc_rgn_op()
As of today we check SLC status before each call of __slc_rgn_op() or __slc_entire_op(). So move status check into __slc_rgn_o
ARC: Cache: Move SLC status check into slc_entire_op() and slc_rgn_op()
As of today we check SLC status before each call of __slc_rgn_op() or __slc_entire_op(). So move status check into __slc_rgn_op() and __slc_entire_op().
As we need to check status before *each* function execution and we call slc_entire_op() and slc_rgn_op() from different places we add this check directly into SLC entire/line functions instead of their callers to avoid code duplication.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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05c6a26a | 21-Mar-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: Cache: Use is_isa_arcv2() instead of CONFIG_ISA_ARCV2 ifdef
Use is_isa_arcv2() function where it is possible instead of CONFIG_ISA_ARCV2 define check to make code cleaner at the same time keepi
ARC: Cache: Use is_isa_arcv2() instead of CONFIG_ISA_ARCV2 ifdef
Use is_isa_arcv2() function where it is possible instead of CONFIG_ISA_ARCV2 define check to make code cleaner at the same time keeping pretty much the same functionality - code in branches under "if (is_isa_arcv2())" won't be compiled if CONFIG_ISA_ARCV2 is not defined, still we need a couple of CONFIG_ISA_ARCV2 ifdefs to make compiler happy. That's because code in !is_isa_x() branch gets compiled and only then gets optimized away.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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