xref: /openbmc/u-boot/drivers/ram/stm32mp1/stm32mp1_ram.c (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1 /*
2  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
5  */
6 
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <ram.h>
11 #include <regmap.h>
12 #include <syscon.h>
13 #include <asm/io.h>
14 #include "stm32mp1_ddr.h"
15 
16 static const char *const clkname[] = {
17 	"ddrc1",
18 	"ddrc2",
19 	"ddrcapb",
20 	"ddrphycapb",
21 	"ddrphyc" /* LAST clock => used for get_rate() */
22 };
23 
24 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
25 {
26 	unsigned long ddrphy_clk;
27 	unsigned long ddr_clk;
28 	struct clk clk;
29 	int ret;
30 	int idx;
31 
32 	for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
33 		ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
34 
35 		if (!ret)
36 			ret = clk_enable(&clk);
37 
38 		if (ret) {
39 			printf("error for %s : %d\n", clkname[idx], ret);
40 			return ret;
41 		}
42 	}
43 
44 	priv->clk = clk;
45 	ddrphy_clk = clk_get_rate(&priv->clk);
46 
47 	debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
48 	      mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
49 	/* max 10% frequency delta */
50 	ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000);
51 	if (ddr_clk > (mem_speed * 1000 * 100)) {
52 		pr_err("DDR expected freq %d MHz, current is %d MHz\n",
53 		       mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
54 		return -EINVAL;
55 	}
56 
57 	return 0;
58 }
59 
60 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
61 {
62 	struct ddr_info *priv = dev_get_priv(dev);
63 	int ret, idx;
64 	struct clk axidcg;
65 	struct stm32mp1_ddr_config config;
66 
67 #define PARAM(x, y) \
68 	{ x,\
69 	  offsetof(struct stm32mp1_ddr_config, y),\
70 	  sizeof(config.y) / sizeof(u32)}
71 
72 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
73 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
74 
75 	const struct {
76 		const char *name; /* name in DT */
77 		const u32 offset; /* offset in config struct */
78 		const u32 size;   /* size of parameters */
79 	} param[] = {
80 		CTL_PARAM(reg),
81 		CTL_PARAM(timing),
82 		CTL_PARAM(map),
83 		CTL_PARAM(perf),
84 		PHY_PARAM(reg),
85 		PHY_PARAM(timing),
86 		PHY_PARAM(cal)
87 	};
88 
89 	config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
90 	config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
91 	config.info.name = dev_read_string(dev, "st,mem-name");
92 	if (!config.info.name) {
93 		debug("%s: no st,mem-name\n", __func__);
94 		return -EINVAL;
95 	}
96 	printf("RAM: %s\n", config.info.name);
97 
98 	for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
99 		ret = dev_read_u32_array(dev, param[idx].name,
100 					 (void *)((u32)&config +
101 						  param[idx].offset),
102 					 param[idx].size);
103 		debug("%s: %s[0x%x] = %d\n", __func__,
104 		      param[idx].name, param[idx].size, ret);
105 		if (ret) {
106 			pr_err("%s: Cannot read %s\n",
107 			       __func__, param[idx].name);
108 			return -EINVAL;
109 		}
110 	}
111 
112 	ret = clk_get_by_name(dev, "axidcg", &axidcg);
113 	if (ret) {
114 		debug("%s: Cannot found axidcg\n", __func__);
115 		return -EINVAL;
116 	}
117 	clk_disable(&axidcg); /* disable clock gating during init */
118 
119 	stm32mp1_ddr_init(priv, &config);
120 
121 	clk_enable(&axidcg); /* enable clock gating */
122 
123 	/* check size */
124 	debug("%s : get_ram_size(%x, %x)\n", __func__,
125 	      (u32)priv->info.base, (u32)STM32_DDR_SIZE);
126 
127 	priv->info.size = get_ram_size((long *)priv->info.base,
128 				       STM32_DDR_SIZE);
129 
130 	debug("%s : %x\n", __func__, (u32)priv->info.size);
131 
132 	/* check memory access for all memory */
133 	if (config.info.size != priv->info.size) {
134 		printf("DDR invalid size : 0x%x, expected 0x%x\n",
135 		       priv->info.size, config.info.size);
136 		return -EINVAL;
137 	}
138 	return 0;
139 }
140 
141 static int stm32mp1_ddr_probe(struct udevice *dev)
142 {
143 	struct ddr_info *priv = dev_get_priv(dev);
144 	struct regmap *map;
145 	int ret;
146 
147 	debug("STM32MP1 DDR probe\n");
148 	priv->dev = dev;
149 
150 	ret = regmap_init_mem(dev, &map);
151 	if (ret)
152 		return ret;
153 
154 	priv->ctl = regmap_get_range(map, 0);
155 	priv->phy = regmap_get_range(map, 1);
156 
157 	priv->rcc = STM32_RCC_BASE;
158 
159 	priv->info.base = STM32_DDR_BASE;
160 
161 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
162 	priv->info.size = 0;
163 	return stm32mp1_ddr_setup(dev);
164 #else
165 	priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
166 	return 0;
167 #endif
168 }
169 
170 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
171 {
172 	struct ddr_info *priv = dev_get_priv(dev);
173 
174 	*info = priv->info;
175 
176 	return 0;
177 }
178 
179 static struct ram_ops stm32mp1_ddr_ops = {
180 	.get_info = stm32mp1_ddr_get_info,
181 };
182 
183 static const struct udevice_id stm32mp1_ddr_ids[] = {
184 	{ .compatible = "st,stm32mp1-ddr" },
185 	{ }
186 };
187 
188 U_BOOT_DRIVER(ddr_stm32mp1) = {
189 	.name = "stm32mp1_ddr",
190 	.id = UCLASS_RAM,
191 	.of_match = stm32mp1_ddr_ids,
192 	.ops = &stm32mp1_ddr_ops,
193 	.probe = stm32mp1_ddr_probe,
194 	.priv_auto_alloc_size = sizeof(struct ddr_info),
195 };
196