1 /* 2 * board/renesas/koelsch/koelsch.c 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 * 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <environment.h> 15 #include <asm/processor.h> 16 #include <asm/mach-types.h> 17 #include <asm/io.h> 18 #include <linux/errno.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/gpio.h> 21 #include <asm/arch/rmobile.h> 22 #include <asm/arch/rcar-mstp.h> 23 #include <asm/arch/sh_sdhi.h> 24 #include <netdev.h> 25 #include <miiphy.h> 26 #include <i2c.h> 27 #include <div64.h> 28 #include "qos.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define CLK2MHZ(clk) (clk / 1000 / 1000) 33 void s_init(void) 34 { 35 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 36 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 37 u32 stc; 38 39 /* Watchdog init */ 40 writel(0xA5A5A500, &rwdt->rwtcsra); 41 writel(0xA5A5A500, &swdt->swtcsra); 42 43 /* CPU frequency setting. Set to 1.5GHz */ 44 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 45 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 46 47 /* QoS */ 48 qos_init(); 49 } 50 51 #define TMU0_MSTP125 (1 << 25) 52 #define SCIF0_MSTP721 (1 << 21) 53 #define ETHER_MSTP813 (1 << 13) 54 55 #define SDHI0_MSTP314 (1 << 14) 56 #define SDHI1_MSTP312 (1 << 12) 57 #define SDHI2_MSTP311 (1 << 11) 58 59 #define SD1CKCR 0xE6150078 60 #define SD2CKCR 0xE615026C 61 #define SD_97500KHZ 0x7 62 63 int board_early_init_f(void) 64 { 65 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 66 67 /* SCIF0 */ 68 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 69 70 /* ETHER */ 71 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 72 73 /* SDHI */ 74 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, 75 SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); 76 77 /* 78 * SD0 clock is set to 97.5MHz by default. 79 * Set SD1 and SD2 to the 97.5MHz as well. 80 */ 81 writel(SD_97500KHZ, SD1CKCR); 82 writel(SD_97500KHZ, SD2CKCR); 83 84 return 0; 85 } 86 87 /* LSI pin pull-up control */ 88 #define PUPR5 0xe6060114 89 #define PUPR5_ETH 0x3FFC0000 90 #define PUPR5_ETH_MAGIC (1 << 27) 91 int board_init(void) 92 { 93 /* adress of boot parameters */ 94 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 95 96 /* Init PFC controller */ 97 r8a7791_pinmux_init(); 98 99 /* ETHER Enable */ 100 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 101 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 102 gpio_request(GPIO_FN_ETH_RXD0, NULL); 103 gpio_request(GPIO_FN_ETH_RXD1, NULL); 104 gpio_request(GPIO_FN_ETH_LINK, NULL); 105 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 106 gpio_request(GPIO_FN_ETH_MDIO, NULL); 107 gpio_request(GPIO_FN_ETH_TXD1, NULL); 108 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 109 gpio_request(GPIO_FN_ETH_TXD0, NULL); 110 gpio_request(GPIO_FN_ETH_MDC, NULL); 111 gpio_request(GPIO_FN_IRQ0, NULL); 112 113 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 114 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 115 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 116 117 gpio_direction_output(GPIO_GP_5_22, 0); 118 mdelay(20); 119 gpio_set_value(GPIO_GP_5_22, 1); 120 udelay(1); 121 122 return 0; 123 } 124 125 #define CXR24 0xEE7003C0 /* MAC address high register */ 126 #define CXR25 0xEE7003C8 /* MAC address low register */ 127 int board_eth_init(bd_t *bis) 128 { 129 #ifdef CONFIG_SH_ETHER 130 int ret = -ENODEV; 131 u32 val; 132 unsigned char enetaddr[6]; 133 134 ret = sh_eth_initialize(bis); 135 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 136 return ret; 137 138 /* Set Mac address */ 139 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 140 enetaddr[2] << 8 | enetaddr[3]; 141 writel(val, CXR24); 142 143 val = enetaddr[4] << 8 | enetaddr[5]; 144 writel(val, CXR25); 145 146 return ret; 147 #else 148 return 0; 149 #endif 150 } 151 152 int board_mmc_init(bd_t *bis) 153 { 154 int ret = -ENODEV; 155 156 #ifdef CONFIG_SH_SDHI 157 gpio_request(GPIO_FN_SD0_DATA0, NULL); 158 gpio_request(GPIO_FN_SD0_DATA1, NULL); 159 gpio_request(GPIO_FN_SD0_DATA2, NULL); 160 gpio_request(GPIO_FN_SD0_DATA3, NULL); 161 gpio_request(GPIO_FN_SD0_CLK, NULL); 162 gpio_request(GPIO_FN_SD0_CMD, NULL); 163 gpio_request(GPIO_FN_SD0_CD, NULL); 164 gpio_request(GPIO_FN_SD2_DATA0, NULL); 165 gpio_request(GPIO_FN_SD2_DATA1, NULL); 166 gpio_request(GPIO_FN_SD2_DATA2, NULL); 167 gpio_request(GPIO_FN_SD2_DATA3, NULL); 168 gpio_request(GPIO_FN_SD2_CLK, NULL); 169 gpio_request(GPIO_FN_SD2_CMD, NULL); 170 gpio_request(GPIO_FN_SD2_CD, NULL); 171 172 /* SDHI 0 */ 173 gpio_request(GPIO_GP_7_17, NULL); 174 gpio_request(GPIO_GP_2_12, NULL); 175 gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ 176 gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ 177 178 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 179 SH_SDHI_QUIRK_16BIT_BUF); 180 if (ret) 181 return ret; 182 183 /* SDHI 1 */ 184 gpio_request(GPIO_GP_7_18, NULL); 185 gpio_request(GPIO_GP_2_13, NULL); 186 gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ 187 gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ 188 189 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); 190 if (ret) 191 return ret; 192 193 /* SDHI 2 */ 194 gpio_request(GPIO_GP_7_19, NULL); 195 gpio_request(GPIO_GP_2_26, NULL); 196 gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ 197 gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ 198 199 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 200 #endif 201 return ret; 202 } 203 204 int dram_init(void) 205 { 206 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 207 208 return 0; 209 } 210 211 /* koelsch has KSZ8041NL/RNL */ 212 #define PHY_CONTROL1 0x1E 213 #define PHY_LED_MODE 0xC0000 214 #define PHY_LED_MODE_ACK 0x4000 215 int board_phy_config(struct phy_device *phydev) 216 { 217 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 218 ret &= ~PHY_LED_MODE; 219 ret |= PHY_LED_MODE_ACK; 220 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 221 222 return 0; 223 } 224 225 const struct rmobile_sysinfo sysinfo = { 226 CONFIG_ARCH_RMOBILE_BOARD_STRING 227 }; 228 229 void reset_cpu(ulong addr) 230 { 231 u8 val; 232 233 i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 234 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 235 val |= 0x02; 236 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 237 } 238 239 static const struct sh_serial_platdata serial_platdata = { 240 .base = SCIF0_BASE, 241 .type = PORT_SCIF, 242 .clk = 14745600, 243 .clk_mode = EXT_CLK, 244 }; 245 246 U_BOOT_DEVICE(koelsch_serials) = { 247 .name = "serial_sh", 248 .platdata = &serial_platdata, 249 }; 250