1 /* 2 * board/renesas/gose/gose.c 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm.h> 12 #include <dm/platform_data/serial_sh.h> 13 #include <environment.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/sh_sdhi.h> 23 #include <netdev.h> 24 #include <miiphy.h> 25 #include <i2c.h> 26 #include "qos.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define CLK2MHZ(clk) (clk / 1000 / 1000) 31 void s_init(void) 32 { 33 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 34 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 35 u32 stc; 36 37 /* Watchdog init */ 38 writel(0xA5A5A500, &rwdt->rwtcsra); 39 writel(0xA5A5A500, &swdt->swtcsra); 40 41 /* CPU frequency setting. Set to 1.5GHz */ 42 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 43 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 44 45 /* QoS */ 46 qos_init(); 47 } 48 49 #define TMU0_MSTP125 (1 << 25) 50 #define SCIF0_MSTP721 (1 << 21) 51 #define ETHER_MSTP813 (1 << 13) 52 53 #define SDHI0_MSTP314 (1 << 14) 54 #define SDHI1_MSTP312 (1 << 12) 55 #define SDHI2_MSTP311 (1 << 11) 56 57 #define SD1CKCR 0xE6150078 58 #define SD2CKCR 0xE615026C 59 #define SD_97500KHZ 0x7 60 61 int board_early_init_f(void) 62 { 63 /* TMU0 */ 64 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 65 66 /* SCIF0 */ 67 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 68 69 /* ETHER */ 70 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 71 72 /* SDHI */ 73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, 74 SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); 75 writel(SD_97500KHZ, SD1CKCR); 76 writel(SD_97500KHZ, SD2CKCR); 77 78 return 0; 79 } 80 81 #define PUPR5 0xE6060114 82 #define PUPR5_ETH 0x3FFC0000 83 #define PUPR5_ETH_MAGIC (1 << 27) 84 85 int board_init(void) 86 { 87 /* adress of boot parameters */ 88 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 89 90 /* Init PFC controller */ 91 r8a7793_pinmux_init(); 92 93 /* ETHER Enable */ 94 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 95 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 96 gpio_request(GPIO_FN_ETH_RXD0, NULL); 97 gpio_request(GPIO_FN_ETH_RXD1, NULL); 98 gpio_request(GPIO_FN_ETH_LINK, NULL); 99 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 100 gpio_request(GPIO_FN_ETH_MDIO, NULL); 101 gpio_request(GPIO_FN_ETH_TXD1, NULL); 102 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 103 gpio_request(GPIO_FN_ETH_TXD0, NULL); 104 gpio_request(GPIO_FN_ETH_MDC, NULL); 105 gpio_request(GPIO_FN_IRQ0, NULL); 106 107 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 108 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 109 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 110 111 gpio_direction_output(GPIO_GP_5_22, 0); 112 mdelay(20); 113 gpio_set_value(GPIO_GP_5_22, 1); 114 udelay(1); 115 116 return 0; 117 } 118 119 #define CXR24 0xEE7003C0 /* MAC address high register */ 120 #define CXR25 0xEE7003C8 /* MAC address low register */ 121 122 int board_eth_init(bd_t *bis) 123 { 124 int ret = -ENODEV; 125 u32 val; 126 unsigned char enetaddr[6]; 127 128 #ifdef CONFIG_SH_ETHER 129 ret = sh_eth_initialize(bis); 130 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 131 return ret; 132 133 /* Set Mac address */ 134 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 135 enetaddr[2] << 8 | enetaddr[3]; 136 writel(val, CXR24); 137 138 val = enetaddr[4] << 8 | enetaddr[5]; 139 writel(val, CXR25); 140 #endif 141 142 return ret; 143 } 144 145 int board_mmc_init(bd_t *bis) 146 { 147 int ret = -ENODEV; 148 149 #ifdef CONFIG_SH_SDHI 150 gpio_request(GPIO_FN_SD0_DATA0, NULL); 151 gpio_request(GPIO_FN_SD0_DATA1, NULL); 152 gpio_request(GPIO_FN_SD0_DATA2, NULL); 153 gpio_request(GPIO_FN_SD0_DATA3, NULL); 154 gpio_request(GPIO_FN_SD0_CLK, NULL); 155 gpio_request(GPIO_FN_SD0_CMD, NULL); 156 gpio_request(GPIO_FN_SD0_CD, NULL); 157 gpio_request(GPIO_FN_SD2_DATA0, NULL); 158 gpio_request(GPIO_FN_SD2_DATA1, NULL); 159 gpio_request(GPIO_FN_SD2_DATA2, NULL); 160 gpio_request(GPIO_FN_SD2_DATA3, NULL); 161 gpio_request(GPIO_FN_SD2_CLK, NULL); 162 gpio_request(GPIO_FN_SD2_CMD, NULL); 163 gpio_request(GPIO_FN_SD2_CD, NULL); 164 165 /* SDHI 0 */ 166 gpio_request(GPIO_GP_7_17, NULL); 167 gpio_request(GPIO_GP_2_12, NULL); 168 gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ 169 gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ 170 171 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 172 SH_SDHI_QUIRK_16BIT_BUF); 173 if (ret) 174 return ret; 175 176 /* SDHI 1 */ 177 gpio_request(GPIO_GP_7_18, NULL); 178 gpio_request(GPIO_GP_2_13, NULL); 179 gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ 180 gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ 181 182 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); 183 if (ret) 184 return ret; 185 186 /* SDHI 2 */ 187 gpio_request(GPIO_GP_7_19, NULL); 188 gpio_request(GPIO_GP_2_26, NULL); 189 gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ 190 gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ 191 192 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 193 #endif 194 return ret; 195 } 196 197 int dram_init(void) 198 { 199 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 200 201 return 0; 202 } 203 204 const struct rmobile_sysinfo sysinfo = { 205 CONFIG_ARCH_RMOBILE_BOARD_STRING 206 }; 207 208 void reset_cpu(ulong addr) 209 { 210 u8 val; 211 212 i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 213 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 214 val |= 0x02; 215 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 216 } 217 218 static const struct sh_serial_platdata serial_platdata = { 219 .base = SCIF0_BASE, 220 .type = PORT_SCIF, 221 .clk = 14745600, 222 .clk_mode = EXT_CLK, 223 }; 224 225 U_BOOT_DEVICE(gose_serials) = { 226 .name = "serial_sh", 227 .platdata = &serial_platdata, 228 }; 229