| 26bd3f31 | 14-Sep-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+-------------------------------
arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality.
Note:
* The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
* Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
* All daughter cards beyond the basic boards shall be maintained as
overlays.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com
show more ...
|
| d361ed88 | 14-Sep-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: Add support for J7200 SoC
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V
arm64: dts: ti: Add support for J7200 SoC
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
and I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-5-lokeshvutla@ti.com
show more ...
|
| 21bb8c83 | 14-Sep-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
To allow lesser dependency and better maintainability use CONFIG_ARCH_K3
for building dtbs for all K3 based devices. This is as per the
discus
arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
To allow lesser dependency and better maintainability use CONFIG_ARCH_K3
for building dtbs for all K3 based devices. This is as per the
discussion in [0].
[0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-2-lokeshvutla@ti.com
show more ...
|
| 66db854b | 14-Sep-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC m
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200914152115.1788-3-kishon@ti.com
show more ...
|
| 4e583388 | 14-Sep-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
Add PCIe device tree nodes (both RC and EP) for the four
PCIe instances here.
Also add the missing translations required in the "ranges"
DT
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
Add PCIe device tree nodes (both RC and EP) for the four
PCIe instances here.
Also add the missing translations required in the "ranges"
DT property of cbass_main to access all the four PCIe
instances.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200914152115.1788-2-kishon@ti.com
show more ...
|
| 9a8ecd41 | 03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-wakeup: Use generic temperature-sensor for node name
Use temperature-sensor@ naming for nodes following standard conventions of device
tree (section 2.2.2 Generic Names recom
arm64: dts: ti: k3-am65-wakeup: Use generic temperature-sensor for node name
Use temperature-sensor@ naming for nodes following standard conventions of device
tree (section 2.2.2 Generic Names recommendation in [1]).
[1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3
Suggested-by: Suman Anna <s-anna@ti.com>
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-8-nm@ti.com
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|
| 4c19fb9c | 03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-base-board Use generic camera for node name instead of ov5640
Use camera@ naming for nodes following standard conventions of device
tree (section 2.2.2 Generic Names recommen
arm64: dts: ti: k3-am65-base-board Use generic camera for node name instead of ov5640
Use camera@ naming for nodes following standard conventions of device
tree (section 2.2.2 Generic Names recommendation in [1]).
[1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3
Suggested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-7-nm@ti.com
show more ...
|
| 86e67b59 | 03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names
serdes and ehrpwm_tbclk nodes should be using clock@ naming for nodes
following standard conventions of device tree (section 2.2.2
arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names
serdes and ehrpwm_tbclk nodes should be using clock@ naming for nodes
following standard conventions of device tree (section 2.2.2 Generic
Names recommendation in [1]).
[1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3
Suggested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-5-nm@ti.com
show more ...
|
| 91e5f404 | 03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*: Use generic gpio for node names
Use gpio@ naming for nodes following standard conventions of device
tree (section 2.2.2 Generic Names recommendation in [1]).
[1] https://g
arm64: dts: ti: k3-am65*: Use generic gpio for node names
Use gpio@ naming for nodes following standard conventions of device
tree (section 2.2.2 Generic Names recommendation in [1]).
[1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3
Suggested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-4-nm@ti.com
show more ...
|
| 05e393c5 | 03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-main: Use lower case hexadecimal
Device tree convention uses lower case a-f for hexadecimals. Fix the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vut
arm64: dts: ti: k3-am65-main: Use lower case hexadecimal
Device tree convention uses lower case a-f for hexadecimals. Fix the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-3-nm@ti.com
show more ...
|
| 1aedefe1 | 03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j721e: Use lower case hexadecimal
Device tree convention uses lower case a-f for hexadecimals. Fix the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <
arm64: dts: ti: k3-j721e: Use lower case hexadecimal
Device tree convention uses lower case a-f for hexadecimals. Fix the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-2-nm@ti.com
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|
| 269a5641 | 02-Aug-2020 |
Sekhar Nori <nsekhar@ti.com> |
arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed
Per errata i2104 documented in AM65x device errata document (TI document
number SPRZ452E, revised June 2019), Gen3 operation is not supported for
arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed
Per errata i2104 documented in AM65x device errata document (TI document
number SPRZ452E, revised June 2019), Gen3 operation is not supported for
both PCIe Root Complex and Endpoint modes of operation.
See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf
Restrict speed to Gen2 to address the errata.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com
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|
| 67cfbb62 | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication b
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-9-s-anna@ti.com
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|
| 1939d37f | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN v
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.
The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-8-s-anna@ti.com
show more ...
|
| cf53928f | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
Add the required 'mboxes' property to the C71x DSP processor for the TI
J721E common processor board. The mailboxes and some shared memory
arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
Add the required 'mboxes' property to the C71x DSP processor for the TI
J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the DSPs. The nodes are therefore added
in the common k3-j721e-som-p0.dtsi file so that all of these can be
co-located.
The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-7-s-anna@ti.com
show more ...
|
| 804a4cc7 | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 K
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
C71x_0 DSP: j7-c71_0-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-6-s-anna@ti.com
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|
| e379ba84 | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within t
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.
The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.
The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.
The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-5-s-anna@ti.com
show more ...
|
| a55babbf | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
Add the required 'mboxes' property to both the C66x DSP processors for the
TI J721E common processor board. The mailboxes and some shared
arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
Add the required 'mboxes' property to both the C66x DSP processors for the
TI J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the DSPs. The nodes are therefore added
in the common k3-j721e-som-p0.dtsi file so that all of these can be
co-located.
The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-4-s-anna@ti.com
show more ...
|
| eb9a2a63 | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, a
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
C66x_0 DSP: j7-c66_0-fw
C66x_1 DSP: j7-c66_1-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-3-s-anna@ti.com
show more ...
|
| 74b5742b | 25-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file
The commit eb9f9173d01f ("arm64: dts: ti: k3-j721e-common-proc-board:
Add IPC sub-mailbox nodes") has added the sub-mailbox no
arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file
The commit eb9f9173d01f ("arm64: dts: ti: k3-j721e-common-proc-board:
Add IPC sub-mailbox nodes") has added the sub-mailbox nodes used by
various remote processors and disabled the unused mailbox clusters
directly in the k3-j721e-common-proc-board dts file. Move all of these
nodes into the k3-j721e-som-p0.dtsi file instead to co-locate all the
mailboxes and the soon to be added DDR reserved-memory carveout nodes
used by remoteprocs within the same dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-2-s-anna@ti.com
show more ...
|
| 8ebcaaae | 26-Aug-2020 |
Keerthy <j-keerthy@ti.com> |
arm64: dts: ti: k3-j721e-main: Add crypto accelerator node
Add crypto accelarator node for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites.
[t-kris
arm64: dts: ti: k3-j721e-main: Add crypto accelerator node
Add crypto accelarator node for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites.
[t-kristo@ti.com: Modifications based on introduction of yaml binding]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200826082921.19143-3-t-kristo@ti.com
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|