1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: dmsc@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clocks { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 chipid@43000014 { 38 compatible = "ti,am654-chipid"; 39 reg = <0x00 0x43000014 0x00 0x4>; 40 }; 41 42 wkup_pmx0: pinctrl@4301c000 { 43 compatible = "pinctrl-single"; 44 /* Proxy 0 addressing */ 45 reg = <0x00 0x4301c000 0x00 0x178>; 46 #pinctrl-cells = <1>; 47 pinctrl-single,register-width = <32>; 48 pinctrl-single,function-mask = <0xffffffff>; 49 }; 50 51 mcu_ram: sram@41c00000 { 52 compatible = "mmio-sram"; 53 reg = <0x00 0x41c00000 0x00 0x100000>; 54 ranges = <0x00 0x00 0x41c00000 0x100000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 }; 58 59 wkup_uart0: serial@42300000 { 60 compatible = "ti,j721e-uart", "ti,am654-uart"; 61 reg = <0x00 0x42300000 0x00 0x100>; 62 reg-shift = <2>; 63 reg-io-width = <4>; 64 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 65 clock-frequency = <48000000>; 66 current-speed = <115200>; 67 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 68 clocks = <&k3_clks 287 2>; 69 clock-names = "fclk"; 70 }; 71 72 mcu_uart0: serial@40a00000 { 73 compatible = "ti,j721e-uart", "ti,am654-uart"; 74 reg = <0x00 0x40a00000 0x00 0x100>; 75 reg-shift = <2>; 76 reg-io-width = <4>; 77 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 78 clock-frequency = <96000000>; 79 current-speed = <115200>; 80 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 81 clocks = <&k3_clks 149 2>; 82 clock-names = "fclk"; 83 }; 84 85 wkup_gpio_intr: interrupt-controller2 { 86 compatible = "ti,sci-intr"; 87 ti,intr-trigger-type = <1>; 88 interrupt-controller; 89 interrupt-parent = <&gic500>; 90 #interrupt-cells = <1>; 91 ti,sci = <&dmsc>; 92 ti,sci-dev-id = <137>; 93 ti,interrupt-ranges = <16 960 16>; 94 }; 95 96 mcu_navss: bus@28380000 { 97 compatible = "simple-mfd"; 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 101 dma-coherent; 102 dma-ranges; 103 ti,sci-dev-id = <232>; 104 105 mcu_ringacc: ringacc@2b800000 { 106 compatible = "ti,am654-navss-ringacc"; 107 reg = <0x00 0x2b800000 0x00 0x400000>, 108 <0x00 0x2b000000 0x00 0x400000>, 109 <0x00 0x28590000 0x00 0x100>, 110 <0x00 0x2a500000 0x00 0x40000>; 111 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 112 ti,num-rings = <286>; 113 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 114 ti,sci = <&dmsc>; 115 ti,sci-dev-id = <235>; 116 msi-parent = <&main_udmass_inta>; 117 }; 118 119 mcu_udmap: dma-controller@285c0000 { 120 compatible = "ti,j721e-navss-mcu-udmap"; 121 reg = <0x00 0x285c0000 0x00 0x100>, 122 <0x00 0x2a800000 0x00 0x40000>, 123 <0x00 0x2aa00000 0x00 0x40000>; 124 reg-names = "gcfg", "rchanrt", "tchanrt"; 125 msi-parent = <&main_udmass_inta>; 126 #dma-cells = <1>; 127 128 ti,sci = <&dmsc>; 129 ti,sci-dev-id = <236>; 130 ti,ringacc = <&mcu_ringacc>; 131 132 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 133 <0x0f>; /* TX_HCHAN */ 134 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 135 <0x0b>; /* RX_HCHAN */ 136 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 137 }; 138 }; 139}; 140