1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/mux-j721e-wiz.h> 10 11&cbass_main { 12 msmc_ram: sram@70000000 { 13 compatible = "mmio-sram"; 14 reg = <0x0 0x70000000 0x0 0x800000>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x0 0x0 0x70000000 0x800000>; 18 19 atf-sram@0 { 20 reg = <0x0 0x20000>; 21 }; 22 }; 23 24 scm_conf: scm-conf@100000 { 25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x0 0x0 0x00100000 0x1c000>; 30 31 pcie0_ctrl: syscon@4070 { 32 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 33 reg = <0x00004070 0x4>; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 ranges = <0x4070 0x4070 0x4>; 37 }; 38 39 pcie1_ctrl: syscon@4074 { 40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 41 reg = <0x00004074 0x4>; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x4074 0x4074 0x4>; 45 }; 46 47 pcie2_ctrl: syscon@4078 { 48 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 49 reg = <0x00004078 0x4>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 ranges = <0x4078 0x4078 0x4>; 53 }; 54 55 pcie3_ctrl: syscon@407c { 56 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 57 reg = <0x0000407c 0x4>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges = <0x407c 0x407c 0x4>; 61 }; 62 63 serdes_ln_ctrl: mux@4080 { 64 compatible = "mmio-mux"; 65 reg = <0x00004080 0x50>; 66 #mux-control-cells = <1>; 67 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 68 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 69 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 70 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 71 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 72 /* SERDES4 lane0/1/2/3 select */ 73 idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, 74 <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, 75 <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, 76 <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>, 77 <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; 78 }; 79 80 usb_serdes_mux: mux-controller@4000 { 81 compatible = "mmio-mux"; 82 #mux-control-cells = <1>; 83 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 84 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 85 }; 86 }; 87 88 gic500: interrupt-controller@1800000 { 89 compatible = "arm,gic-v3"; 90 #address-cells = <2>; 91 #size-cells = <2>; 92 ranges; 93 #interrupt-cells = <3>; 94 interrupt-controller; 95 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 96 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 97 98 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 99 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 100 101 gic_its: msi-controller@1820000 { 102 compatible = "arm,gic-v3-its"; 103 reg = <0x00 0x01820000 0x00 0x10000>; 104 socionext,synquacer-pre-its = <0x1000000 0x400000>; 105 msi-controller; 106 #msi-cells = <1>; 107 }; 108 }; 109 110 main_gpio_intr: interrupt-controller0 { 111 compatible = "ti,sci-intr"; 112 ti,intr-trigger-type = <1>; 113 interrupt-controller; 114 interrupt-parent = <&gic500>; 115 #interrupt-cells = <1>; 116 ti,sci = <&dmsc>; 117 ti,sci-dev-id = <131>; 118 ti,interrupt-ranges = <8 392 56>; 119 }; 120 121 main-navss { 122 compatible = "simple-mfd"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 dma-coherent; 127 dma-ranges; 128 129 ti,sci-dev-id = <199>; 130 131 main_navss_intr: interrupt-controller1 { 132 compatible = "ti,sci-intr"; 133 ti,intr-trigger-type = <4>; 134 interrupt-controller; 135 interrupt-parent = <&gic500>; 136 #interrupt-cells = <1>; 137 ti,sci = <&dmsc>; 138 ti,sci-dev-id = <213>; 139 ti,interrupt-ranges = <0 64 64>, 140 <64 448 64>, 141 <128 672 64>; 142 }; 143 144 main_udmass_inta: interrupt-controller@33d00000 { 145 compatible = "ti,sci-inta"; 146 reg = <0x0 0x33d00000 0x0 0x100000>; 147 interrupt-controller; 148 interrupt-parent = <&main_navss_intr>; 149 msi-controller; 150 ti,sci = <&dmsc>; 151 ti,sci-dev-id = <209>; 152 ti,interrupt-ranges = <0 0 256>; 153 }; 154 155 secure_proxy_main: mailbox@32c00000 { 156 compatible = "ti,am654-secure-proxy"; 157 #mbox-cells = <1>; 158 reg-names = "target_data", "rt", "scfg"; 159 reg = <0x00 0x32c00000 0x00 0x100000>, 160 <0x00 0x32400000 0x00 0x100000>, 161 <0x00 0x32800000 0x00 0x100000>; 162 interrupt-names = "rx_011"; 163 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 smmu0: iommu@36600000 { 167 compatible = "arm,smmu-v3"; 168 reg = <0x0 0x36600000 0x0 0x100000>; 169 interrupt-parent = <&gic500>; 170 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 171 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 172 interrupt-names = "eventq", "gerror"; 173 #iommu-cells = <1>; 174 }; 175 176 hwspinlock: spinlock@30e00000 { 177 compatible = "ti,am654-hwspinlock"; 178 reg = <0x00 0x30e00000 0x00 0x1000>; 179 #hwlock-cells = <1>; 180 }; 181 182 mailbox0_cluster0: mailbox@31f80000 { 183 compatible = "ti,am654-mailbox"; 184 reg = <0x00 0x31f80000 0x00 0x200>; 185 #mbox-cells = <1>; 186 ti,mbox-num-users = <4>; 187 ti,mbox-num-fifos = <16>; 188 interrupt-parent = <&main_navss_intr>; 189 }; 190 191 mailbox0_cluster1: mailbox@31f81000 { 192 compatible = "ti,am654-mailbox"; 193 reg = <0x00 0x31f81000 0x00 0x200>; 194 #mbox-cells = <1>; 195 ti,mbox-num-users = <4>; 196 ti,mbox-num-fifos = <16>; 197 interrupt-parent = <&main_navss_intr>; 198 }; 199 200 mailbox0_cluster2: mailbox@31f82000 { 201 compatible = "ti,am654-mailbox"; 202 reg = <0x00 0x31f82000 0x00 0x200>; 203 #mbox-cells = <1>; 204 ti,mbox-num-users = <4>; 205 ti,mbox-num-fifos = <16>; 206 interrupt-parent = <&main_navss_intr>; 207 }; 208 209 mailbox0_cluster3: mailbox@31f83000 { 210 compatible = "ti,am654-mailbox"; 211 reg = <0x00 0x31f83000 0x00 0x200>; 212 #mbox-cells = <1>; 213 ti,mbox-num-users = <4>; 214 ti,mbox-num-fifos = <16>; 215 interrupt-parent = <&main_navss_intr>; 216 }; 217 218 mailbox0_cluster4: mailbox@31f84000 { 219 compatible = "ti,am654-mailbox"; 220 reg = <0x00 0x31f84000 0x00 0x200>; 221 #mbox-cells = <1>; 222 ti,mbox-num-users = <4>; 223 ti,mbox-num-fifos = <16>; 224 interrupt-parent = <&main_navss_intr>; 225 }; 226 227 mailbox0_cluster5: mailbox@31f85000 { 228 compatible = "ti,am654-mailbox"; 229 reg = <0x00 0x31f85000 0x00 0x200>; 230 #mbox-cells = <1>; 231 ti,mbox-num-users = <4>; 232 ti,mbox-num-fifos = <16>; 233 interrupt-parent = <&main_navss_intr>; 234 }; 235 236 mailbox0_cluster6: mailbox@31f86000 { 237 compatible = "ti,am654-mailbox"; 238 reg = <0x00 0x31f86000 0x00 0x200>; 239 #mbox-cells = <1>; 240 ti,mbox-num-users = <4>; 241 ti,mbox-num-fifos = <16>; 242 interrupt-parent = <&main_navss_intr>; 243 }; 244 245 mailbox0_cluster7: mailbox@31f87000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f87000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 }; 253 254 mailbox0_cluster8: mailbox@31f88000 { 255 compatible = "ti,am654-mailbox"; 256 reg = <0x00 0x31f88000 0x00 0x200>; 257 #mbox-cells = <1>; 258 ti,mbox-num-users = <4>; 259 ti,mbox-num-fifos = <16>; 260 interrupt-parent = <&main_navss_intr>; 261 }; 262 263 mailbox0_cluster9: mailbox@31f89000 { 264 compatible = "ti,am654-mailbox"; 265 reg = <0x00 0x31f89000 0x00 0x200>; 266 #mbox-cells = <1>; 267 ti,mbox-num-users = <4>; 268 ti,mbox-num-fifos = <16>; 269 interrupt-parent = <&main_navss_intr>; 270 }; 271 272 mailbox0_cluster10: mailbox@31f8a000 { 273 compatible = "ti,am654-mailbox"; 274 reg = <0x00 0x31f8a000 0x00 0x200>; 275 #mbox-cells = <1>; 276 ti,mbox-num-users = <4>; 277 ti,mbox-num-fifos = <16>; 278 interrupt-parent = <&main_navss_intr>; 279 }; 280 281 mailbox0_cluster11: mailbox@31f8b000 { 282 compatible = "ti,am654-mailbox"; 283 reg = <0x00 0x31f8b000 0x00 0x200>; 284 #mbox-cells = <1>; 285 ti,mbox-num-users = <4>; 286 ti,mbox-num-fifos = <16>; 287 interrupt-parent = <&main_navss_intr>; 288 }; 289 290 main_ringacc: ringacc@3c000000 { 291 compatible = "ti,am654-navss-ringacc"; 292 reg = <0x0 0x3c000000 0x0 0x400000>, 293 <0x0 0x38000000 0x0 0x400000>, 294 <0x0 0x31120000 0x0 0x100>, 295 <0x0 0x33000000 0x0 0x40000>; 296 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 297 ti,num-rings = <1024>; 298 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 299 ti,sci = <&dmsc>; 300 ti,sci-dev-id = <211>; 301 msi-parent = <&main_udmass_inta>; 302 }; 303 304 main_udmap: dma-controller@31150000 { 305 compatible = "ti,j721e-navss-main-udmap"; 306 reg = <0x0 0x31150000 0x0 0x100>, 307 <0x0 0x34000000 0x0 0x100000>, 308 <0x0 0x35000000 0x0 0x100000>; 309 reg-names = "gcfg", "rchanrt", "tchanrt"; 310 msi-parent = <&main_udmass_inta>; 311 #dma-cells = <1>; 312 313 ti,sci = <&dmsc>; 314 ti,sci-dev-id = <212>; 315 ti,ringacc = <&main_ringacc>; 316 317 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 318 <0x0f>, /* TX_HCHAN */ 319 <0x10>; /* TX_UHCHAN */ 320 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 321 <0x0b>, /* RX_HCHAN */ 322 <0x0c>; /* RX_UHCHAN */ 323 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 324 }; 325 326 cpts@310d0000 { 327 compatible = "ti,j721e-cpts"; 328 reg = <0x0 0x310d0000 0x0 0x400>; 329 reg-names = "cpts"; 330 clocks = <&k3_clks 201 1>; 331 clock-names = "cpts"; 332 interrupts-extended = <&main_navss_intr 391>; 333 interrupt-names = "cpts"; 334 ti,cpts-periodic-outputs = <6>; 335 ti,cpts-ext-ts-inputs = <8>; 336 }; 337 }; 338 339 main_crypto: crypto@4e00000 { 340 compatible = "ti,j721e-sa2ul"; 341 reg = <0x0 0x4e00000 0x0 0x1200>; 342 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 343 #address-cells = <2>; 344 #size-cells = <2>; 345 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 346 347 status = "okay"; 348 349 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 350 <&main_udmap 0x4001>; 351 dma-names = "tx", "rx1", "rx2"; 352 dma-coherent; 353 354 rng: rng@4e10000 { 355 compatible = "inside-secure,safexcel-eip76"; 356 reg = <0x0 0x4e10000 0x0 0x7d>; 357 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&k3_clks 264 1>; 359 }; 360 }; 361 362 main_pmx0: pinctrl@11c000 { 363 compatible = "pinctrl-single"; 364 /* Proxy 0 addressing */ 365 reg = <0x0 0x11c000 0x0 0x2b4>; 366 #pinctrl-cells = <1>; 367 pinctrl-single,register-width = <32>; 368 pinctrl-single,function-mask = <0xffffffff>; 369 }; 370 371 dummy_cmn_refclk: dummy-cmn-refclk { 372 #clock-cells = <0>; 373 compatible = "fixed-clock"; 374 clock-frequency = <100000000>; 375 }; 376 377 dummy_cmn_refclk1: dummy-cmn-refclk1 { 378 #clock-cells = <0>; 379 compatible = "fixed-clock"; 380 clock-frequency = <100000000>; 381 }; 382 383 serdes_wiz0: wiz@5000000 { 384 compatible = "ti,j721e-wiz-16g"; 385 #address-cells = <1>; 386 #size-cells = <1>; 387 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 388 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 389 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 390 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 391 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 392 num-lanes = <2>; 393 #reset-cells = <1>; 394 ranges = <0x5000000 0x0 0x5000000 0x10000>; 395 396 wiz0_pll0_refclk: pll0-refclk { 397 clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; 398 #clock-cells = <0>; 399 assigned-clocks = <&wiz0_pll0_refclk>; 400 assigned-clock-parents = <&k3_clks 292 11>; 401 }; 402 403 wiz0_pll1_refclk: pll1-refclk { 404 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; 405 #clock-cells = <0>; 406 assigned-clocks = <&wiz0_pll1_refclk>; 407 assigned-clock-parents = <&k3_clks 292 0>; 408 }; 409 410 wiz0_refclk_dig: refclk-dig { 411 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 412 #clock-cells = <0>; 413 assigned-clocks = <&wiz0_refclk_dig>; 414 assigned-clock-parents = <&k3_clks 292 11>; 415 }; 416 417 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 418 clocks = <&wiz0_refclk_dig>; 419 #clock-cells = <0>; 420 }; 421 422 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 423 clocks = <&wiz0_pll1_refclk>; 424 #clock-cells = <0>; 425 }; 426 427 serdes0: serdes@5000000 { 428 compatible = "ti,sierra-phy-t0"; 429 reg-names = "serdes"; 430 reg = <0x5000000 0x10000>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 resets = <&serdes_wiz0 0>; 434 reset-names = "sierra_reset"; 435 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 436 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 437 }; 438 }; 439 440 serdes_wiz1: wiz@5010000 { 441 compatible = "ti,j721e-wiz-16g"; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; 446 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 447 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 448 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 449 num-lanes = <2>; 450 #reset-cells = <1>; 451 ranges = <0x5010000 0x0 0x5010000 0x10000>; 452 453 wiz1_pll0_refclk: pll0-refclk { 454 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 455 #clock-cells = <0>; 456 assigned-clocks = <&wiz1_pll0_refclk>; 457 assigned-clock-parents = <&k3_clks 293 13>; 458 }; 459 460 wiz1_pll1_refclk: pll1-refclk { 461 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 462 #clock-cells = <0>; 463 assigned-clocks = <&wiz1_pll1_refclk>; 464 assigned-clock-parents = <&k3_clks 293 0>; 465 }; 466 467 wiz1_refclk_dig: refclk-dig { 468 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 469 #clock-cells = <0>; 470 assigned-clocks = <&wiz1_refclk_dig>; 471 assigned-clock-parents = <&k3_clks 293 13>; 472 }; 473 474 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 475 clocks = <&wiz1_refclk_dig>; 476 #clock-cells = <0>; 477 }; 478 479 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 480 clocks = <&wiz1_pll1_refclk>; 481 #clock-cells = <0>; 482 }; 483 484 serdes1: serdes@5010000 { 485 compatible = "ti,sierra-phy-t0"; 486 reg-names = "serdes"; 487 reg = <0x5010000 0x10000>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 resets = <&serdes_wiz1 0>; 491 reset-names = "sierra_reset"; 492 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 493 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 494 }; 495 }; 496 497 serdes_wiz2: wiz@5020000 { 498 compatible = "ti,j721e-wiz-16g"; 499 #address-cells = <1>; 500 #size-cells = <1>; 501 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 502 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; 503 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 504 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 505 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 506 num-lanes = <2>; 507 #reset-cells = <1>; 508 ranges = <0x5020000 0x0 0x5020000 0x10000>; 509 510 wiz2_pll0_refclk: pll0-refclk { 511 clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; 512 #clock-cells = <0>; 513 assigned-clocks = <&wiz2_pll0_refclk>; 514 assigned-clock-parents = <&k3_clks 294 11>; 515 }; 516 517 wiz2_pll1_refclk: pll1-refclk { 518 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; 519 #clock-cells = <0>; 520 assigned-clocks = <&wiz2_pll1_refclk>; 521 assigned-clock-parents = <&k3_clks 294 0>; 522 }; 523 524 wiz2_refclk_dig: refclk-dig { 525 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 526 #clock-cells = <0>; 527 assigned-clocks = <&wiz2_refclk_dig>; 528 assigned-clock-parents = <&k3_clks 294 11>; 529 }; 530 531 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 532 clocks = <&wiz2_refclk_dig>; 533 #clock-cells = <0>; 534 }; 535 536 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 537 clocks = <&wiz2_pll1_refclk>; 538 #clock-cells = <0>; 539 }; 540 541 serdes2: serdes@5020000 { 542 compatible = "ti,sierra-phy-t0"; 543 reg-names = "serdes"; 544 reg = <0x5020000 0x10000>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 resets = <&serdes_wiz2 0>; 548 reset-names = "sierra_reset"; 549 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 550 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 551 }; 552 }; 553 554 serdes_wiz3: wiz@5030000 { 555 compatible = "ti,j721e-wiz-16g"; 556 #address-cells = <1>; 557 #size-cells = <1>; 558 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 559 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; 560 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 561 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 562 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 563 num-lanes = <2>; 564 #reset-cells = <1>; 565 ranges = <0x5030000 0x0 0x5030000 0x10000>; 566 567 wiz3_pll0_refclk: pll0-refclk { 568 clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; 569 #clock-cells = <0>; 570 assigned-clocks = <&wiz3_pll0_refclk>; 571 assigned-clock-parents = <&k3_clks 295 9>; 572 }; 573 574 wiz3_pll1_refclk: pll1-refclk { 575 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; 576 #clock-cells = <0>; 577 assigned-clocks = <&wiz3_pll1_refclk>; 578 assigned-clock-parents = <&k3_clks 295 0>; 579 }; 580 581 wiz3_refclk_dig: refclk-dig { 582 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 583 #clock-cells = <0>; 584 assigned-clocks = <&wiz3_refclk_dig>; 585 assigned-clock-parents = <&k3_clks 295 9>; 586 }; 587 588 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 589 clocks = <&wiz3_refclk_dig>; 590 #clock-cells = <0>; 591 }; 592 593 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 594 clocks = <&wiz3_pll1_refclk>; 595 #clock-cells = <0>; 596 }; 597 598 serdes3: serdes@5030000 { 599 compatible = "ti,sierra-phy-t0"; 600 reg-names = "serdes"; 601 reg = <0x5030000 0x10000>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 resets = <&serdes_wiz3 0>; 605 reset-names = "sierra_reset"; 606 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 607 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 608 }; 609 }; 610 611 pcie0_rc: pcie@2900000 { 612 compatible = "ti,j721e-pcie-host"; 613 reg = <0x00 0x02900000 0x00 0x1000>, 614 <0x00 0x02907000 0x00 0x400>, 615 <0x00 0x0d000000 0x00 0x00800000>, 616 <0x00 0x10000000 0x00 0x00001000>; 617 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 618 interrupt-names = "link_state"; 619 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 620 device_type = "pci"; 621 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 622 max-link-speed = <3>; 623 num-lanes = <2>; 624 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 625 clocks = <&k3_clks 239 1>; 626 clock-names = "fck"; 627 #address-cells = <3>; 628 #size-cells = <2>; 629 bus-range = <0x0 0xf>; 630 vendor-id = <0x104c>; 631 device-id = <0xb00d>; 632 msi-map = <0x0 &gic_its 0x0 0x10000>; 633 dma-coherent; 634 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 635 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 636 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 637 }; 638 639 pcie0_ep: pcie-ep@2900000 { 640 compatible = "ti,j721e-pcie-ep"; 641 reg = <0x00 0x02900000 0x00 0x1000>, 642 <0x00 0x02907000 0x00 0x400>, 643 <0x00 0x0d000000 0x00 0x00800000>, 644 <0x00 0x10000000 0x00 0x08000000>; 645 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 646 interrupt-names = "link_state"; 647 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 648 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 649 max-link-speed = <3>; 650 num-lanes = <2>; 651 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 652 clocks = <&k3_clks 239 1>; 653 clock-names = "fck"; 654 cdns,max-outbound-regions = <16>; 655 max-functions = /bits/ 8 <6>; 656 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 657 dma-coherent; 658 }; 659 660 pcie1_rc: pcie@2910000 { 661 compatible = "ti,j721e-pcie-host"; 662 reg = <0x00 0x02910000 0x00 0x1000>, 663 <0x00 0x02917000 0x00 0x400>, 664 <0x00 0x0d800000 0x00 0x00800000>, 665 <0x00 0x18000000 0x00 0x00001000>; 666 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 667 interrupt-names = "link_state"; 668 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 669 device_type = "pci"; 670 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 671 max-link-speed = <3>; 672 num-lanes = <2>; 673 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 674 clocks = <&k3_clks 240 1>; 675 clock-names = "fck"; 676 #address-cells = <3>; 677 #size-cells = <2>; 678 bus-range = <0x0 0xf>; 679 vendor-id = <0x104c>; 680 device-id = <0xb00d>; 681 msi-map = <0x0 &gic_its 0x10000 0x10000>; 682 dma-coherent; 683 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 684 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 685 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 686 }; 687 688 pcie1_ep: pcie-ep@2910000 { 689 compatible = "ti,j721e-pcie-ep"; 690 reg = <0x00 0x02910000 0x00 0x1000>, 691 <0x00 0x02917000 0x00 0x400>, 692 <0x00 0x0d800000 0x00 0x00800000>, 693 <0x00 0x18000000 0x00 0x08000000>; 694 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 695 interrupt-names = "link_state"; 696 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 697 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 698 max-link-speed = <3>; 699 num-lanes = <2>; 700 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 701 clocks = <&k3_clks 240 1>; 702 clock-names = "fck"; 703 cdns,max-outbound-regions = <16>; 704 max-functions = /bits/ 8 <6>; 705 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 706 dma-coherent; 707 }; 708 709 pcie2_rc: pcie@2920000 { 710 compatible = "ti,j721e-pcie-host"; 711 reg = <0x00 0x02920000 0x00 0x1000>, 712 <0x00 0x02927000 0x00 0x400>, 713 <0x00 0x0e000000 0x00 0x00800000>, 714 <0x44 0x00000000 0x00 0x00001000>; 715 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 716 interrupt-names = "link_state"; 717 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 718 device_type = "pci"; 719 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 720 max-link-speed = <3>; 721 num-lanes = <2>; 722 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 723 clocks = <&k3_clks 241 1>; 724 clock-names = "fck"; 725 #address-cells = <3>; 726 #size-cells = <2>; 727 bus-range = <0x0 0xf>; 728 vendor-id = <0x104c>; 729 device-id = <0xb00d>; 730 msi-map = <0x0 &gic_its 0x20000 0x10000>; 731 dma-coherent; 732 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 733 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 734 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 735 }; 736 737 pcie2_ep: pcie-ep@2920000 { 738 compatible = "ti,j721e-pcie-ep"; 739 reg = <0x00 0x02920000 0x00 0x1000>, 740 <0x00 0x02927000 0x00 0x400>, 741 <0x00 0x0e000000 0x00 0x00800000>, 742 <0x44 0x00000000 0x00 0x08000000>; 743 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 744 interrupt-names = "link_state"; 745 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 746 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 747 max-link-speed = <3>; 748 num-lanes = <2>; 749 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 750 clocks = <&k3_clks 241 1>; 751 clock-names = "fck"; 752 cdns,max-outbound-regions = <16>; 753 max-functions = /bits/ 8 <6>; 754 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 755 dma-coherent; 756 }; 757 758 pcie3_rc: pcie@2930000 { 759 compatible = "ti,j721e-pcie-host"; 760 reg = <0x00 0x02930000 0x00 0x1000>, 761 <0x00 0x02937000 0x00 0x400>, 762 <0x00 0x0e800000 0x00 0x00800000>, 763 <0x44 0x10000000 0x00 0x00001000>; 764 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 765 interrupt-names = "link_state"; 766 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 767 device_type = "pci"; 768 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 769 max-link-speed = <3>; 770 num-lanes = <2>; 771 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 772 clocks = <&k3_clks 242 1>; 773 clock-names = "fck"; 774 #address-cells = <3>; 775 #size-cells = <2>; 776 bus-range = <0x0 0xf>; 777 vendor-id = <0x104c>; 778 device-id = <0xb00d>; 779 msi-map = <0x0 &gic_its 0x30000 0x10000>; 780 dma-coherent; 781 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 782 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 783 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 784 }; 785 786 pcie3_ep: pcie-ep@2930000 { 787 compatible = "ti,j721e-pcie-ep"; 788 reg = <0x00 0x02930000 0x00 0x1000>, 789 <0x00 0x02937000 0x00 0x400>, 790 <0x00 0x0e800000 0x00 0x00800000>, 791 <0x44 0x10000000 0x00 0x08000000>; 792 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 793 interrupt-names = "link_state"; 794 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 795 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 796 max-link-speed = <3>; 797 num-lanes = <2>; 798 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 799 clocks = <&k3_clks 242 1>; 800 clock-names = "fck"; 801 cdns,max-outbound-regions = <16>; 802 max-functions = /bits/ 8 <6>; 803 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 804 dma-coherent; 805 #address-cells = <2>; 806 #size-cells = <2>; 807 }; 808 809 main_uart0: serial@2800000 { 810 compatible = "ti,j721e-uart", "ti,am654-uart"; 811 reg = <0x00 0x02800000 0x00 0x100>; 812 reg-shift = <2>; 813 reg-io-width = <4>; 814 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 815 clock-frequency = <48000000>; 816 current-speed = <115200>; 817 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 818 clocks = <&k3_clks 146 0>; 819 clock-names = "fclk"; 820 }; 821 822 main_uart1: serial@2810000 { 823 compatible = "ti,j721e-uart", "ti,am654-uart"; 824 reg = <0x00 0x02810000 0x00 0x100>; 825 reg-shift = <2>; 826 reg-io-width = <4>; 827 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 828 clock-frequency = <48000000>; 829 current-speed = <115200>; 830 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&k3_clks 278 0>; 832 clock-names = "fclk"; 833 }; 834 835 main_uart2: serial@2820000 { 836 compatible = "ti,j721e-uart", "ti,am654-uart"; 837 reg = <0x00 0x02820000 0x00 0x100>; 838 reg-shift = <2>; 839 reg-io-width = <4>; 840 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 841 clock-frequency = <48000000>; 842 current-speed = <115200>; 843 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 844 clocks = <&k3_clks 279 0>; 845 clock-names = "fclk"; 846 }; 847 848 main_uart3: serial@2830000 { 849 compatible = "ti,j721e-uart", "ti,am654-uart"; 850 reg = <0x00 0x02830000 0x00 0x100>; 851 reg-shift = <2>; 852 reg-io-width = <4>; 853 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 854 clock-frequency = <48000000>; 855 current-speed = <115200>; 856 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 857 clocks = <&k3_clks 280 0>; 858 clock-names = "fclk"; 859 }; 860 861 main_uart4: serial@2840000 { 862 compatible = "ti,j721e-uart", "ti,am654-uart"; 863 reg = <0x00 0x02840000 0x00 0x100>; 864 reg-shift = <2>; 865 reg-io-width = <4>; 866 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 867 clock-frequency = <48000000>; 868 current-speed = <115200>; 869 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 870 clocks = <&k3_clks 281 0>; 871 clock-names = "fclk"; 872 }; 873 874 main_uart5: serial@2850000 { 875 compatible = "ti,j721e-uart", "ti,am654-uart"; 876 reg = <0x00 0x02850000 0x00 0x100>; 877 reg-shift = <2>; 878 reg-io-width = <4>; 879 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 880 clock-frequency = <48000000>; 881 current-speed = <115200>; 882 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 883 clocks = <&k3_clks 282 0>; 884 clock-names = "fclk"; 885 }; 886 887 main_uart6: serial@2860000 { 888 compatible = "ti,j721e-uart", "ti,am654-uart"; 889 reg = <0x00 0x02860000 0x00 0x100>; 890 reg-shift = <2>; 891 reg-io-width = <4>; 892 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 893 clock-frequency = <48000000>; 894 current-speed = <115200>; 895 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 896 clocks = <&k3_clks 283 0>; 897 clock-names = "fclk"; 898 }; 899 900 main_uart7: serial@2870000 { 901 compatible = "ti,j721e-uart", "ti,am654-uart"; 902 reg = <0x00 0x02870000 0x00 0x100>; 903 reg-shift = <2>; 904 reg-io-width = <4>; 905 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 906 clock-frequency = <48000000>; 907 current-speed = <115200>; 908 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 909 clocks = <&k3_clks 284 0>; 910 clock-names = "fclk"; 911 }; 912 913 main_uart8: serial@2880000 { 914 compatible = "ti,j721e-uart", "ti,am654-uart"; 915 reg = <0x00 0x02880000 0x00 0x100>; 916 reg-shift = <2>; 917 reg-io-width = <4>; 918 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 919 clock-frequency = <48000000>; 920 current-speed = <115200>; 921 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 922 clocks = <&k3_clks 285 0>; 923 clock-names = "fclk"; 924 }; 925 926 main_uart9: serial@2890000 { 927 compatible = "ti,j721e-uart", "ti,am654-uart"; 928 reg = <0x00 0x02890000 0x00 0x100>; 929 reg-shift = <2>; 930 reg-io-width = <4>; 931 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 932 clock-frequency = <48000000>; 933 current-speed = <115200>; 934 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 935 clocks = <&k3_clks 286 0>; 936 clock-names = "fclk"; 937 }; 938 939 main_gpio0: gpio@600000 { 940 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 941 reg = <0x0 0x00600000 0x0 0x100>; 942 gpio-controller; 943 #gpio-cells = <2>; 944 interrupt-parent = <&main_gpio_intr>; 945 interrupts = <256>, <257>, <258>, <259>, 946 <260>, <261>, <262>, <263>; 947 interrupt-controller; 948 #interrupt-cells = <2>; 949 ti,ngpio = <128>; 950 ti,davinci-gpio-unbanked = <0>; 951 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 952 clocks = <&k3_clks 105 0>; 953 clock-names = "gpio"; 954 }; 955 956 main_gpio1: gpio@601000 { 957 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 958 reg = <0x0 0x00601000 0x0 0x100>; 959 gpio-controller; 960 #gpio-cells = <2>; 961 interrupt-parent = <&main_gpio_intr>; 962 interrupts = <288>, <289>, <290>; 963 interrupt-controller; 964 #interrupt-cells = <2>; 965 ti,ngpio = <36>; 966 ti,davinci-gpio-unbanked = <0>; 967 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 968 clocks = <&k3_clks 106 0>; 969 clock-names = "gpio"; 970 }; 971 972 main_gpio2: gpio@610000 { 973 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 974 reg = <0x0 0x00610000 0x0 0x100>; 975 gpio-controller; 976 #gpio-cells = <2>; 977 interrupt-parent = <&main_gpio_intr>; 978 interrupts = <264>, <265>, <266>, <267>, 979 <268>, <269>, <270>, <271>; 980 interrupt-controller; 981 #interrupt-cells = <2>; 982 ti,ngpio = <128>; 983 ti,davinci-gpio-unbanked = <0>; 984 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 985 clocks = <&k3_clks 107 0>; 986 clock-names = "gpio"; 987 }; 988 989 main_gpio3: gpio@611000 { 990 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 991 reg = <0x0 0x00611000 0x0 0x100>; 992 gpio-controller; 993 #gpio-cells = <2>; 994 interrupt-parent = <&main_gpio_intr>; 995 interrupts = <292>, <293>, <294>; 996 interrupt-controller; 997 #interrupt-cells = <2>; 998 ti,ngpio = <36>; 999 ti,davinci-gpio-unbanked = <0>; 1000 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1001 clocks = <&k3_clks 108 0>; 1002 clock-names = "gpio"; 1003 }; 1004 1005 main_gpio4: gpio@620000 { 1006 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1007 reg = <0x0 0x00620000 0x0 0x100>; 1008 gpio-controller; 1009 #gpio-cells = <2>; 1010 interrupt-parent = <&main_gpio_intr>; 1011 interrupts = <272>, <273>, <274>, <275>, 1012 <276>, <277>, <278>, <279>; 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 ti,ngpio = <128>; 1016 ti,davinci-gpio-unbanked = <0>; 1017 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1018 clocks = <&k3_clks 109 0>; 1019 clock-names = "gpio"; 1020 }; 1021 1022 main_gpio5: gpio@621000 { 1023 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1024 reg = <0x0 0x00621000 0x0 0x100>; 1025 gpio-controller; 1026 #gpio-cells = <2>; 1027 interrupt-parent = <&main_gpio_intr>; 1028 interrupts = <296>, <297>, <298>; 1029 interrupt-controller; 1030 #interrupt-cells = <2>; 1031 ti,ngpio = <36>; 1032 ti,davinci-gpio-unbanked = <0>; 1033 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1034 clocks = <&k3_clks 110 0>; 1035 clock-names = "gpio"; 1036 }; 1037 1038 main_gpio6: gpio@630000 { 1039 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1040 reg = <0x0 0x00630000 0x0 0x100>; 1041 gpio-controller; 1042 #gpio-cells = <2>; 1043 interrupt-parent = <&main_gpio_intr>; 1044 interrupts = <280>, <281>, <282>, <283>, 1045 <284>, <285>, <286>, <287>; 1046 interrupt-controller; 1047 #interrupt-cells = <2>; 1048 ti,ngpio = <128>; 1049 ti,davinci-gpio-unbanked = <0>; 1050 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1051 clocks = <&k3_clks 111 0>; 1052 clock-names = "gpio"; 1053 }; 1054 1055 main_gpio7: gpio@631000 { 1056 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1057 reg = <0x0 0x00631000 0x0 0x100>; 1058 gpio-controller; 1059 #gpio-cells = <2>; 1060 interrupt-parent = <&main_gpio_intr>; 1061 interrupts = <300>, <301>, <302>; 1062 interrupt-controller; 1063 #interrupt-cells = <2>; 1064 ti,ngpio = <36>; 1065 ti,davinci-gpio-unbanked = <0>; 1066 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1067 clocks = <&k3_clks 112 0>; 1068 clock-names = "gpio"; 1069 }; 1070 1071 main_sdhci0: sdhci@4f80000 { 1072 compatible = "ti,j721e-sdhci-8bit"; 1073 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1074 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1076 clock-names = "clk_xin", "clk_ahb"; 1077 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 1078 assigned-clocks = <&k3_clks 91 1>; 1079 assigned-clock-parents = <&k3_clks 91 2>; 1080 bus-width = <8>; 1081 mmc-hs400-1_8v; 1082 mmc-ddr-1_8v; 1083 ti,otap-del-sel = <0x2>; 1084 ti,trm-icp = <0x8>; 1085 ti,strobe-sel = <0x77>; 1086 dma-coherent; 1087 }; 1088 1089 main_sdhci1: sdhci@4fb0000 { 1090 compatible = "ti,j721e-sdhci-4bit"; 1091 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1092 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1094 clock-names = "clk_xin", "clk_ahb"; 1095 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 1096 assigned-clocks = <&k3_clks 92 0>; 1097 assigned-clock-parents = <&k3_clks 92 1>; 1098 ti,otap-del-sel = <0x2>; 1099 ti,trm-icp = <0x8>; 1100 ti,clkbuf-sel = <0x7>; 1101 dma-coherent; 1102 no-1-8-v; 1103 }; 1104 1105 main_sdhci2: sdhci@4f98000 { 1106 compatible = "ti,j721e-sdhci-4bit"; 1107 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1108 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1109 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1110 clock-names = "clk_xin", "clk_ahb"; 1111 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 1112 assigned-clocks = <&k3_clks 93 0>; 1113 assigned-clock-parents = <&k3_clks 93 1>; 1114 ti,otap-del-sel = <0x2>; 1115 ti,trm-icp = <0x8>; 1116 ti,clkbuf-sel = <0x7>; 1117 dma-coherent; 1118 no-1-8-v; 1119 }; 1120 1121 usbss0: cdns-usb@4104000 { 1122 compatible = "ti,j721e-usb"; 1123 reg = <0x00 0x4104000 0x00 0x100>; 1124 dma-coherent; 1125 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1126 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1127 clock-names = "ref", "lpm"; 1128 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1129 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges; 1133 1134 usb0: usb@6000000 { 1135 compatible = "cdns,usb3"; 1136 reg = <0x00 0x6000000 0x00 0x10000>, 1137 <0x00 0x6010000 0x00 0x10000>, 1138 <0x00 0x6020000 0x00 0x10000>; 1139 reg-names = "otg", "xhci", "dev"; 1140 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1141 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1142 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1143 interrupt-names = "host", 1144 "peripheral", 1145 "otg"; 1146 maximum-speed = "super-speed"; 1147 dr_mode = "otg"; 1148 }; 1149 }; 1150 1151 usbss1: cdns-usb@4114000 { 1152 compatible = "ti,j721e-usb"; 1153 reg = <0x00 0x4114000 0x00 0x100>; 1154 dma-coherent; 1155 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1156 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1157 clock-names = "ref", "lpm"; 1158 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1159 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1160 #address-cells = <2>; 1161 #size-cells = <2>; 1162 ranges; 1163 1164 usb1: usb@6400000 { 1165 compatible = "cdns,usb3"; 1166 reg = <0x00 0x6400000 0x00 0x10000>, 1167 <0x00 0x6410000 0x00 0x10000>, 1168 <0x00 0x6420000 0x00 0x10000>; 1169 reg-names = "otg", "xhci", "dev"; 1170 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1171 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1173 interrupt-names = "host", 1174 "peripheral", 1175 "otg"; 1176 maximum-speed = "super-speed"; 1177 dr_mode = "otg"; 1178 }; 1179 }; 1180 1181 main_i2c0: i2c@2000000 { 1182 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1183 reg = <0x0 0x2000000 0x0 0x100>; 1184 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 clock-names = "fck"; 1188 clocks = <&k3_clks 187 0>; 1189 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1190 }; 1191 1192 main_i2c1: i2c@2010000 { 1193 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1194 reg = <0x0 0x2010000 0x0 0x100>; 1195 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 clock-names = "fck"; 1199 clocks = <&k3_clks 188 0>; 1200 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1201 }; 1202 1203 main_i2c2: i2c@2020000 { 1204 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1205 reg = <0x0 0x2020000 0x0 0x100>; 1206 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 clock-names = "fck"; 1210 clocks = <&k3_clks 189 0>; 1211 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1212 }; 1213 1214 main_i2c3: i2c@2030000 { 1215 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1216 reg = <0x0 0x2030000 0x0 0x100>; 1217 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 clock-names = "fck"; 1221 clocks = <&k3_clks 190 0>; 1222 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1223 }; 1224 1225 main_i2c4: i2c@2040000 { 1226 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1227 reg = <0x0 0x2040000 0x0 0x100>; 1228 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 clock-names = "fck"; 1232 clocks = <&k3_clks 191 0>; 1233 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1234 }; 1235 1236 main_i2c5: i2c@2050000 { 1237 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1238 reg = <0x0 0x2050000 0x0 0x100>; 1239 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 clock-names = "fck"; 1243 clocks = <&k3_clks 192 0>; 1244 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1245 }; 1246 1247 main_i2c6: i2c@2060000 { 1248 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1249 reg = <0x0 0x2060000 0x0 0x100>; 1250 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 clock-names = "fck"; 1254 clocks = <&k3_clks 193 0>; 1255 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1256 }; 1257 1258 ufs_wrapper: ufs-wrapper@4e80000 { 1259 compatible = "ti,j721e-ufs"; 1260 reg = <0x0 0x4e80000 0x0 0x100>; 1261 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1262 clocks = <&k3_clks 277 1>; 1263 assigned-clocks = <&k3_clks 277 1>; 1264 assigned-clock-parents = <&k3_clks 277 4>; 1265 ranges; 1266 #address-cells = <2>; 1267 #size-cells = <2>; 1268 1269 ufs@4e84000 { 1270 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1271 reg = <0x0 0x4e84000 0x0 0x10000>; 1272 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1273 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1274 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1275 clock-names = "core_clk", "phy_clk", "ref_clk"; 1276 dma-coherent; 1277 }; 1278 }; 1279 1280 dss: dss@04a00000 { 1281 compatible = "ti,j721e-dss"; 1282 reg = 1283 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1284 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1285 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1286 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1287 1288 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1289 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1290 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1291 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1292 1293 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1294 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1295 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1296 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1297 1298 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1299 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1300 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1301 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1302 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1303 1304 reg-names = "common_m", "common_s0", 1305 "common_s1", "common_s2", 1306 "vidl1", "vidl2","vid1","vid2", 1307 "ovr1", "ovr2", "ovr3", "ovr4", 1308 "vp1", "vp2", "vp3", "vp4", 1309 "wb"; 1310 1311 clocks = <&k3_clks 152 0>, 1312 <&k3_clks 152 1>, 1313 <&k3_clks 152 4>, 1314 <&k3_clks 152 9>, 1315 <&k3_clks 152 13>; 1316 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1317 1318 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1319 1320 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1324 interrupt-names = "common_m", 1325 "common_s0", 1326 "common_s1", 1327 "common_s2"; 1328 1329 status = "disabled"; 1330 1331 dss_ports: ports { 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 }; 1335 }; 1336 1337 mcasp0: mcasp@2b00000 { 1338 compatible = "ti,am33xx-mcasp-audio"; 1339 reg = <0x0 0x02b00000 0x0 0x2000>, 1340 <0x0 0x02b08000 0x0 0x1000>; 1341 reg-names = "mpu","dat"; 1342 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1344 interrupt-names = "tx", "rx"; 1345 1346 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1347 dma-names = "tx", "rx"; 1348 1349 clocks = <&k3_clks 174 1>; 1350 clock-names = "fck"; 1351 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1352 1353 status = "disabled"; 1354 }; 1355 1356 mcasp1: mcasp@2b10000 { 1357 compatible = "ti,am33xx-mcasp-audio"; 1358 reg = <0x0 0x02b10000 0x0 0x2000>, 1359 <0x0 0x02b18000 0x0 0x1000>; 1360 reg-names = "mpu","dat"; 1361 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1363 interrupt-names = "tx", "rx"; 1364 1365 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1366 dma-names = "tx", "rx"; 1367 1368 clocks = <&k3_clks 175 1>; 1369 clock-names = "fck"; 1370 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1371 1372 status = "disabled"; 1373 }; 1374 1375 mcasp2: mcasp@2b20000 { 1376 compatible = "ti,am33xx-mcasp-audio"; 1377 reg = <0x0 0x02b20000 0x0 0x2000>, 1378 <0x0 0x02b28000 0x0 0x1000>; 1379 reg-names = "mpu","dat"; 1380 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1382 interrupt-names = "tx", "rx"; 1383 1384 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1385 dma-names = "tx", "rx"; 1386 1387 clocks = <&k3_clks 176 1>; 1388 clock-names = "fck"; 1389 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1390 1391 status = "disabled"; 1392 }; 1393 1394 mcasp3: mcasp@2b30000 { 1395 compatible = "ti,am33xx-mcasp-audio"; 1396 reg = <0x0 0x02b30000 0x0 0x2000>, 1397 <0x0 0x02b38000 0x0 0x1000>; 1398 reg-names = "mpu","dat"; 1399 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1401 interrupt-names = "tx", "rx"; 1402 1403 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1404 dma-names = "tx", "rx"; 1405 1406 clocks = <&k3_clks 177 1>; 1407 clock-names = "fck"; 1408 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1409 1410 status = "disabled"; 1411 }; 1412 1413 mcasp4: mcasp@2b40000 { 1414 compatible = "ti,am33xx-mcasp-audio"; 1415 reg = <0x0 0x02b40000 0x0 0x2000>, 1416 <0x0 0x02b48000 0x0 0x1000>; 1417 reg-names = "mpu","dat"; 1418 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1420 interrupt-names = "tx", "rx"; 1421 1422 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1423 dma-names = "tx", "rx"; 1424 1425 clocks = <&k3_clks 178 1>; 1426 clock-names = "fck"; 1427 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1428 1429 status = "disabled"; 1430 }; 1431 1432 mcasp5: mcasp@2b50000 { 1433 compatible = "ti,am33xx-mcasp-audio"; 1434 reg = <0x0 0x02b50000 0x0 0x2000>, 1435 <0x0 0x02b58000 0x0 0x1000>; 1436 reg-names = "mpu","dat"; 1437 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1439 interrupt-names = "tx", "rx"; 1440 1441 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1442 dma-names = "tx", "rx"; 1443 1444 clocks = <&k3_clks 179 1>; 1445 clock-names = "fck"; 1446 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1447 1448 status = "disabled"; 1449 }; 1450 1451 mcasp6: mcasp@2b60000 { 1452 compatible = "ti,am33xx-mcasp-audio"; 1453 reg = <0x0 0x02b60000 0x0 0x2000>, 1454 <0x0 0x02b68000 0x0 0x1000>; 1455 reg-names = "mpu","dat"; 1456 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1458 interrupt-names = "tx", "rx"; 1459 1460 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1461 dma-names = "tx", "rx"; 1462 1463 clocks = <&k3_clks 180 1>; 1464 clock-names = "fck"; 1465 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1466 1467 status = "disabled"; 1468 }; 1469 1470 mcasp7: mcasp@2b70000 { 1471 compatible = "ti,am33xx-mcasp-audio"; 1472 reg = <0x0 0x02b70000 0x0 0x2000>, 1473 <0x0 0x02b78000 0x0 0x1000>; 1474 reg-names = "mpu","dat"; 1475 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1477 interrupt-names = "tx", "rx"; 1478 1479 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1480 dma-names = "tx", "rx"; 1481 1482 clocks = <&k3_clks 181 1>; 1483 clock-names = "fck"; 1484 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1485 1486 status = "disabled"; 1487 }; 1488 1489 mcasp8: mcasp@2b80000 { 1490 compatible = "ti,am33xx-mcasp-audio"; 1491 reg = <0x0 0x02b80000 0x0 0x2000>, 1492 <0x0 0x02b88000 0x0 0x1000>; 1493 reg-names = "mpu","dat"; 1494 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "tx", "rx"; 1497 1498 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1499 dma-names = "tx", "rx"; 1500 1501 clocks = <&k3_clks 182 1>; 1502 clock-names = "fck"; 1503 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1504 1505 status = "disabled"; 1506 }; 1507 1508 mcasp9: mcasp@2b90000 { 1509 compatible = "ti,am33xx-mcasp-audio"; 1510 reg = <0x0 0x02b90000 0x0 0x2000>, 1511 <0x0 0x02b98000 0x0 0x1000>; 1512 reg-names = "mpu","dat"; 1513 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1515 interrupt-names = "tx", "rx"; 1516 1517 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1518 dma-names = "tx", "rx"; 1519 1520 clocks = <&k3_clks 183 1>; 1521 clock-names = "fck"; 1522 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1523 1524 status = "disabled"; 1525 }; 1526 1527 mcasp10: mcasp@2ba0000 { 1528 compatible = "ti,am33xx-mcasp-audio"; 1529 reg = <0x0 0x02ba0000 0x0 0x2000>, 1530 <0x0 0x02ba8000 0x0 0x1000>; 1531 reg-names = "mpu","dat"; 1532 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1534 interrupt-names = "tx", "rx"; 1535 1536 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1537 dma-names = "tx", "rx"; 1538 1539 clocks = <&k3_clks 184 1>; 1540 clock-names = "fck"; 1541 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1542 1543 status = "disabled"; 1544 }; 1545 1546 mcasp11: mcasp@2bb0000 { 1547 compatible = "ti,am33xx-mcasp-audio"; 1548 reg = <0x0 0x02bb0000 0x0 0x2000>, 1549 <0x0 0x02bb8000 0x0 0x1000>; 1550 reg-names = "mpu","dat"; 1551 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1553 interrupt-names = "tx", "rx"; 1554 1555 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1556 dma-names = "tx", "rx"; 1557 1558 clocks = <&k3_clks 185 1>; 1559 clock-names = "fck"; 1560 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1561 1562 status = "disabled"; 1563 }; 1564 1565 watchdog0: watchdog@2200000 { 1566 compatible = "ti,j7-rti-wdt"; 1567 reg = <0x0 0x2200000 0x0 0x100>; 1568 clocks = <&k3_clks 252 1>; 1569 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1570 assigned-clocks = <&k3_clks 252 1>; 1571 assigned-clock-parents = <&k3_clks 252 5>; 1572 }; 1573 1574 watchdog1: watchdog@2210000 { 1575 compatible = "ti,j7-rti-wdt"; 1576 reg = <0x0 0x2210000 0x0 0x100>; 1577 clocks = <&k3_clks 253 1>; 1578 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1579 assigned-clocks = <&k3_clks 253 1>; 1580 assigned-clock-parents = <&k3_clks 253 5>; 1581 }; 1582 1583 c66_0: dsp@4d80800000 { 1584 compatible = "ti,j721e-c66-dsp"; 1585 reg = <0x4d 0x80800000 0x00 0x00048000>, 1586 <0x4d 0x80e00000 0x00 0x00008000>, 1587 <0x4d 0x80f00000 0x00 0x00008000>; 1588 reg-names = "l2sram", "l1pram", "l1dram"; 1589 ti,sci = <&dmsc>; 1590 ti,sci-dev-id = <142>; 1591 ti,sci-proc-ids = <0x03 0xff>; 1592 resets = <&k3_reset 142 1>; 1593 firmware-name = "j7-c66_0-fw"; 1594 }; 1595 1596 c66_1: dsp@4d81800000 { 1597 compatible = "ti,j721e-c66-dsp"; 1598 reg = <0x4d 0x81800000 0x00 0x00048000>, 1599 <0x4d 0x81e00000 0x00 0x00008000>, 1600 <0x4d 0x81f00000 0x00 0x00008000>; 1601 reg-names = "l2sram", "l1pram", "l1dram"; 1602 ti,sci = <&dmsc>; 1603 ti,sci-dev-id = <143>; 1604 ti,sci-proc-ids = <0x04 0xff>; 1605 resets = <&k3_reset 143 1>; 1606 firmware-name = "j7-c66_1-fw"; 1607 }; 1608 1609 c71_0: dsp@64800000 { 1610 compatible = "ti,j721e-c71-dsp"; 1611 reg = <0x00 0x64800000 0x00 0x00080000>, 1612 <0x00 0x64e00000 0x00 0x0000c000>; 1613 reg-names = "l2sram", "l1dram"; 1614 ti,sci = <&dmsc>; 1615 ti,sci-dev-id = <15>; 1616 ti,sci-proc-ids = <0x30 0xff>; 1617 resets = <&k3_reset 15 1>; 1618 firmware-name = "j7-c71_0-fw"; 1619 }; 1620}; 1621