xref: /openbmc/linux/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi (revision e379ba840a7e2c8fb275722226154339077b8f37) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j721e.dtsi"
9
10/ {
11	memory@80000000 {
12		device_type = "memory";
13		/* 4G RAM */
14		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15		      <0x00000008 0x80000000 0x00000000 0x80000000>;
16	};
17
18	reserved_memory: reserved-memory {
19		#address-cells = <2>;
20		#size-cells = <2>;
21		ranges;
22
23		secure_ddr: optee@9e800000 {
24			reg = <0x00 0x9e800000 0x00 0x01800000>;
25			alignment = <0x1000>;
26			no-map;
27		};
28
29		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
30			compatible = "shared-dma-pool";
31			reg = <0x00 0xa6000000 0x00 0x100000>;
32			no-map;
33		};
34
35		c66_0_memory_region: c66-memory@a6100000 {
36			compatible = "shared-dma-pool";
37			reg = <0x00 0xa6100000 0x00 0xf00000>;
38			no-map;
39		};
40
41		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
42			compatible = "shared-dma-pool";
43			reg = <0x00 0xa7000000 0x00 0x100000>;
44			no-map;
45		};
46
47		c66_1_memory_region: c66-memory@a7100000 {
48			compatible = "shared-dma-pool";
49			reg = <0x00 0xa7100000 0x00 0xf00000>;
50			no-map;
51		};
52	};
53};
54
55&wkup_pmx0 {
56	wkup_i2c0_pins_default: wkup_i2c0_pins_default {
57		pinctrl-single,pins = <
58			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
59			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
60		>;
61	};
62
63	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
64		pinctrl-single,pins = <
65			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
66			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
67			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
68			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
69			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
70			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
71			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
72			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
73			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
74			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
75			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
76		>;
77	};
78};
79
80&ospi0 {
81	pinctrl-names = "default";
82	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
83
84	flash@0{
85		compatible = "jedec,spi-nor";
86		reg = <0x0>;
87		spi-tx-bus-width = <1>;
88		spi-rx-bus-width = <8>;
89		spi-max-frequency = <40000000>;
90		cdns,tshsl-ns = <60>;
91		cdns,tsd2d-ns = <60>;
92		cdns,tchsh-ns = <60>;
93		cdns,tslch-ns = <60>;
94		cdns,read-delay = <0>;
95		#address-cells = <1>;
96		#size-cells = <1>;
97	};
98};
99
100&mailbox0_cluster0 {
101	interrupts = <436>;
102
103	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
104		ti,mbox-rx = <0 0 0>;
105		ti,mbox-tx = <1 0 0>;
106	};
107
108	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
109		ti,mbox-rx = <2 0 0>;
110		ti,mbox-tx = <3 0 0>;
111	};
112};
113
114&mailbox0_cluster1 {
115	interrupts = <432>;
116
117	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
118		ti,mbox-rx = <0 0 0>;
119		ti,mbox-tx = <1 0 0>;
120	};
121
122	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
123		ti,mbox-rx = <2 0 0>;
124		ti,mbox-tx = <3 0 0>;
125	};
126};
127
128&mailbox0_cluster2 {
129	interrupts = <428>;
130
131	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
132		ti,mbox-rx = <0 0 0>;
133		ti,mbox-tx = <1 0 0>;
134	};
135
136	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
137		ti,mbox-rx = <2 0 0>;
138		ti,mbox-tx = <3 0 0>;
139	};
140};
141
142&mailbox0_cluster3 {
143	interrupts = <424>;
144
145	mbox_c66_0: mbox-c66-0 {
146		ti,mbox-rx = <0 0 0>;
147		ti,mbox-tx = <1 0 0>;
148	};
149
150	mbox_c66_1: mbox-c66-1 {
151		ti,mbox-rx = <2 0 0>;
152		ti,mbox-tx = <3 0 0>;
153	};
154};
155
156&mailbox0_cluster4 {
157	interrupts = <420>;
158
159	mbox_c71_0: mbox-c71-0 {
160		ti,mbox-rx = <0 0 0>;
161		ti,mbox-tx = <1 0 0>;
162	};
163};
164
165&mailbox0_cluster5 {
166	status = "disabled";
167};
168
169&mailbox0_cluster6 {
170	status = "disabled";
171};
172
173&mailbox0_cluster7 {
174	status = "disabled";
175};
176
177&mailbox0_cluster8 {
178	status = "disabled";
179};
180
181&mailbox0_cluster9 {
182	status = "disabled";
183};
184
185&mailbox0_cluster10 {
186	status = "disabled";
187};
188
189&mailbox0_cluster11 {
190	status = "disabled";
191};
192
193&c66_0 {
194	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
195	memory-region = <&c66_0_dma_memory_region>,
196			<&c66_0_memory_region>;
197};
198
199&c66_1 {
200	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
201	memory-region = <&c66_1_dma_memory_region>,
202			<&c66_1_memory_region>;
203};
204