1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e.dtsi" 9 10/ { 11 memory@80000000 { 12 device_type = "memory"; 13 /* 4G RAM */ 14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 15 <0x00000008 0x80000000 0x00000000 0x80000000>; 16 }; 17 18 reserved_memory: reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 secure_ddr: optee@9e800000 { 24 reg = <0x00 0x9e800000 0x00 0x01800000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 }; 29}; 30 31&wkup_pmx0 { 32 wkup_i2c0_pins_default: wkup_i2c0_pins_default { 33 pinctrl-single,pins = < 34 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 35 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 36 >; 37 }; 38 39 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 40 pinctrl-single,pins = < 41 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 42 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 43 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 44 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 45 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 46 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 47 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 48 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 49 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 50 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 51 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 52 >; 53 }; 54}; 55 56&ospi0 { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 59 60 flash@0{ 61 compatible = "jedec,spi-nor"; 62 reg = <0x0>; 63 spi-tx-bus-width = <1>; 64 spi-rx-bus-width = <8>; 65 spi-max-frequency = <40000000>; 66 cdns,tshsl-ns = <60>; 67 cdns,tsd2d-ns = <60>; 68 cdns,tchsh-ns = <60>; 69 cdns,tslch-ns = <60>; 70 cdns,read-delay = <0>; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 }; 74}; 75 76&mailbox0_cluster0 { 77 interrupts = <436>; 78 79 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 80 ti,mbox-rx = <0 0 0>; 81 ti,mbox-tx = <1 0 0>; 82 }; 83 84 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 85 ti,mbox-rx = <2 0 0>; 86 ti,mbox-tx = <3 0 0>; 87 }; 88}; 89 90&mailbox0_cluster1 { 91 interrupts = <432>; 92 93 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 94 ti,mbox-rx = <0 0 0>; 95 ti,mbox-tx = <1 0 0>; 96 }; 97 98 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 99 ti,mbox-rx = <2 0 0>; 100 ti,mbox-tx = <3 0 0>; 101 }; 102}; 103 104&mailbox0_cluster2 { 105 interrupts = <428>; 106 107 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 108 ti,mbox-rx = <0 0 0>; 109 ti,mbox-tx = <1 0 0>; 110 }; 111 112 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 113 ti,mbox-rx = <2 0 0>; 114 ti,mbox-tx = <3 0 0>; 115 }; 116}; 117 118&mailbox0_cluster3 { 119 interrupts = <424>; 120 121 mbox_c66_0: mbox-c66-0 { 122 ti,mbox-rx = <0 0 0>; 123 ti,mbox-tx = <1 0 0>; 124 }; 125 126 mbox_c66_1: mbox-c66-1 { 127 ti,mbox-rx = <2 0 0>; 128 ti,mbox-tx = <3 0 0>; 129 }; 130}; 131 132&mailbox0_cluster4 { 133 interrupts = <420>; 134 135 mbox_c71_0: mbox-c71-0 { 136 ti,mbox-rx = <0 0 0>; 137 ti,mbox-tx = <1 0 0>; 138 }; 139}; 140 141&mailbox0_cluster5 { 142 status = "disabled"; 143}; 144 145&mailbox0_cluster6 { 146 status = "disabled"; 147}; 148 149&mailbox0_cluster7 { 150 status = "disabled"; 151}; 152 153&mailbox0_cluster8 { 154 status = "disabled"; 155}; 156 157&mailbox0_cluster9 { 158 status = "disabled"; 159}; 160 161&mailbox0_cluster10 { 162 status = "disabled"; 163}; 164 165&mailbox0_cluster11 { 166 status = "disabled"; 167}; 168