1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/mux-j721e-wiz.h> 10 11&cbass_main { 12 msmc_ram: sram@70000000 { 13 compatible = "mmio-sram"; 14 reg = <0x0 0x70000000 0x0 0x800000>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x0 0x0 0x70000000 0x800000>; 18 19 atf-sram@0 { 20 reg = <0x0 0x20000>; 21 }; 22 }; 23 24 scm_conf: scm-conf@100000 { 25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x0 0x0 0x00100000 0x1c000>; 30 31 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 32 compatible = "mmio-mux"; 33 reg = <0x00004080 0x50>; 34 #mux-control-cells = <1>; 35 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 36 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 37 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 38 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 39 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 40 /* SERDES4 lane0/1/2/3 select */ 41 idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, 42 <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, 43 <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, 44 <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>, 45 <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; 46 }; 47 48 usb_serdes_mux: mux-controller@4000 { 49 compatible = "mmio-mux"; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 52 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 53 }; 54 }; 55 56 gic500: interrupt-controller@1800000 { 57 compatible = "arm,gic-v3"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 #interrupt-cells = <3>; 62 interrupt-controller; 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 64 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 65 66 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 67 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 68 69 gic_its: msi-controller@1820000 { 70 compatible = "arm,gic-v3-its"; 71 reg = <0x00 0x01820000 0x00 0x10000>; 72 socionext,synquacer-pre-its = <0x1000000 0x400000>; 73 msi-controller; 74 #msi-cells = <1>; 75 }; 76 }; 77 78 main_gpio_intr: interrupt-controller0 { 79 compatible = "ti,sci-intr"; 80 ti,intr-trigger-type = <1>; 81 interrupt-controller; 82 interrupt-parent = <&gic500>; 83 #interrupt-cells = <1>; 84 ti,sci = <&dmsc>; 85 ti,sci-dev-id = <131>; 86 ti,interrupt-ranges = <8 392 56>; 87 }; 88 89 main_navss { 90 compatible = "simple-mfd"; 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 dma-coherent; 95 dma-ranges; 96 97 ti,sci-dev-id = <199>; 98 99 main_navss_intr: interrupt-controller1 { 100 compatible = "ti,sci-intr"; 101 ti,intr-trigger-type = <4>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 #interrupt-cells = <1>; 105 ti,sci = <&dmsc>; 106 ti,sci-dev-id = <213>; 107 ti,interrupt-ranges = <0 64 64>, 108 <64 448 64>, 109 <128 672 64>; 110 }; 111 112 main_udmass_inta: interrupt-controller@33d00000 { 113 compatible = "ti,sci-inta"; 114 reg = <0x0 0x33d00000 0x0 0x100000>; 115 interrupt-controller; 116 interrupt-parent = <&main_navss_intr>; 117 msi-controller; 118 ti,sci = <&dmsc>; 119 ti,sci-dev-id = <209>; 120 ti,interrupt-ranges = <0 0 256>; 121 }; 122 123 secure_proxy_main: mailbox@32c00000 { 124 compatible = "ti,am654-secure-proxy"; 125 #mbox-cells = <1>; 126 reg-names = "target_data", "rt", "scfg"; 127 reg = <0x00 0x32c00000 0x00 0x100000>, 128 <0x00 0x32400000 0x00 0x100000>, 129 <0x00 0x32800000 0x00 0x100000>; 130 interrupt-names = "rx_011"; 131 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 132 }; 133 134 smmu0: iommu@36600000 { 135 compatible = "arm,smmu-v3"; 136 reg = <0x0 0x36600000 0x0 0x100000>; 137 interrupt-parent = <&gic500>; 138 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 139 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 140 interrupt-names = "eventq", "gerror"; 141 #iommu-cells = <1>; 142 }; 143 144 hwspinlock: spinlock@30e00000 { 145 compatible = "ti,am654-hwspinlock"; 146 reg = <0x00 0x30e00000 0x00 0x1000>; 147 #hwlock-cells = <1>; 148 }; 149 150 mailbox0_cluster0: mailbox@31f80000 { 151 compatible = "ti,am654-mailbox"; 152 reg = <0x00 0x31f80000 0x00 0x200>; 153 #mbox-cells = <1>; 154 ti,mbox-num-users = <4>; 155 ti,mbox-num-fifos = <16>; 156 interrupt-parent = <&main_navss_intr>; 157 }; 158 159 mailbox0_cluster1: mailbox@31f81000 { 160 compatible = "ti,am654-mailbox"; 161 reg = <0x00 0x31f81000 0x00 0x200>; 162 #mbox-cells = <1>; 163 ti,mbox-num-users = <4>; 164 ti,mbox-num-fifos = <16>; 165 interrupt-parent = <&main_navss_intr>; 166 }; 167 168 mailbox0_cluster2: mailbox@31f82000 { 169 compatible = "ti,am654-mailbox"; 170 reg = <0x00 0x31f82000 0x00 0x200>; 171 #mbox-cells = <1>; 172 ti,mbox-num-users = <4>; 173 ti,mbox-num-fifos = <16>; 174 interrupt-parent = <&main_navss_intr>; 175 }; 176 177 mailbox0_cluster3: mailbox@31f83000 { 178 compatible = "ti,am654-mailbox"; 179 reg = <0x00 0x31f83000 0x00 0x200>; 180 #mbox-cells = <1>; 181 ti,mbox-num-users = <4>; 182 ti,mbox-num-fifos = <16>; 183 interrupt-parent = <&main_navss_intr>; 184 }; 185 186 mailbox0_cluster4: mailbox@31f84000 { 187 compatible = "ti,am654-mailbox"; 188 reg = <0x00 0x31f84000 0x00 0x200>; 189 #mbox-cells = <1>; 190 ti,mbox-num-users = <4>; 191 ti,mbox-num-fifos = <16>; 192 interrupt-parent = <&main_navss_intr>; 193 }; 194 195 mailbox0_cluster5: mailbox@31f85000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f85000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 }; 203 204 mailbox0_cluster6: mailbox@31f86000 { 205 compatible = "ti,am654-mailbox"; 206 reg = <0x00 0x31f86000 0x00 0x200>; 207 #mbox-cells = <1>; 208 ti,mbox-num-users = <4>; 209 ti,mbox-num-fifos = <16>; 210 interrupt-parent = <&main_navss_intr>; 211 }; 212 213 mailbox0_cluster7: mailbox@31f87000 { 214 compatible = "ti,am654-mailbox"; 215 reg = <0x00 0x31f87000 0x00 0x200>; 216 #mbox-cells = <1>; 217 ti,mbox-num-users = <4>; 218 ti,mbox-num-fifos = <16>; 219 interrupt-parent = <&main_navss_intr>; 220 }; 221 222 mailbox0_cluster8: mailbox@31f88000 { 223 compatible = "ti,am654-mailbox"; 224 reg = <0x00 0x31f88000 0x00 0x200>; 225 #mbox-cells = <1>; 226 ti,mbox-num-users = <4>; 227 ti,mbox-num-fifos = <16>; 228 interrupt-parent = <&main_navss_intr>; 229 }; 230 231 mailbox0_cluster9: mailbox@31f89000 { 232 compatible = "ti,am654-mailbox"; 233 reg = <0x00 0x31f89000 0x00 0x200>; 234 #mbox-cells = <1>; 235 ti,mbox-num-users = <4>; 236 ti,mbox-num-fifos = <16>; 237 interrupt-parent = <&main_navss_intr>; 238 }; 239 240 mailbox0_cluster10: mailbox@31f8a000 { 241 compatible = "ti,am654-mailbox"; 242 reg = <0x00 0x31f8a000 0x00 0x200>; 243 #mbox-cells = <1>; 244 ti,mbox-num-users = <4>; 245 ti,mbox-num-fifos = <16>; 246 interrupt-parent = <&main_navss_intr>; 247 }; 248 249 mailbox0_cluster11: mailbox@31f8b000 { 250 compatible = "ti,am654-mailbox"; 251 reg = <0x00 0x31f8b000 0x00 0x200>; 252 #mbox-cells = <1>; 253 ti,mbox-num-users = <4>; 254 ti,mbox-num-fifos = <16>; 255 interrupt-parent = <&main_navss_intr>; 256 }; 257 258 main_ringacc: ringacc@3c000000 { 259 compatible = "ti,am654-navss-ringacc"; 260 reg = <0x0 0x3c000000 0x0 0x400000>, 261 <0x0 0x38000000 0x0 0x400000>, 262 <0x0 0x31120000 0x0 0x100>, 263 <0x0 0x33000000 0x0 0x40000>; 264 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 265 ti,num-rings = <1024>; 266 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 267 ti,sci = <&dmsc>; 268 ti,sci-dev-id = <211>; 269 msi-parent = <&main_udmass_inta>; 270 }; 271 272 main_udmap: dma-controller@31150000 { 273 compatible = "ti,j721e-navss-main-udmap"; 274 reg = <0x0 0x31150000 0x0 0x100>, 275 <0x0 0x34000000 0x0 0x100000>, 276 <0x0 0x35000000 0x0 0x100000>; 277 reg-names = "gcfg", "rchanrt", "tchanrt"; 278 msi-parent = <&main_udmass_inta>; 279 #dma-cells = <1>; 280 281 ti,sci = <&dmsc>; 282 ti,sci-dev-id = <212>; 283 ti,ringacc = <&main_ringacc>; 284 285 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 286 <0x0f>, /* TX_HCHAN */ 287 <0x10>; /* TX_UHCHAN */ 288 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 289 <0x0b>, /* RX_HCHAN */ 290 <0x0c>; /* RX_UHCHAN */ 291 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 292 }; 293 294 cpts@310d0000 { 295 compatible = "ti,j721e-cpts"; 296 reg = <0x0 0x310d0000 0x0 0x400>; 297 reg-names = "cpts"; 298 clocks = <&k3_clks 201 1>; 299 clock-names = "cpts"; 300 interrupts-extended = <&main_navss_intr 391>; 301 interrupt-names = "cpts"; 302 ti,cpts-periodic-outputs = <6>; 303 ti,cpts-ext-ts-inputs = <8>; 304 }; 305 }; 306 307 main_crypto: crypto@4e00000 { 308 compatible = "ti,j721e-sa2ul"; 309 reg = <0x0 0x4e00000 0x0 0x1200>; 310 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 311 #address-cells = <2>; 312 #size-cells = <2>; 313 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 314 315 status = "okay"; 316 317 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 318 <&main_udmap 0x4001>; 319 dma-names = "tx", "rx1", "rx2"; 320 dma-coherent; 321 322 rng: rng@4e10000 { 323 compatible = "inside-secure,safexcel-eip76"; 324 reg = <0x0 0x4e10000 0x0 0x7d>; 325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&k3_clks 264 1>; 327 }; 328 }; 329 330 main_pmx0: pinmux@11c000 { 331 compatible = "pinctrl-single"; 332 /* Proxy 0 addressing */ 333 reg = <0x0 0x11c000 0x0 0x2b4>; 334 #pinctrl-cells = <1>; 335 pinctrl-single,register-width = <32>; 336 pinctrl-single,function-mask = <0xffffffff>; 337 }; 338 339 dummy_cmn_refclk: dummy-cmn-refclk { 340 #clock-cells = <0>; 341 compatible = "fixed-clock"; 342 clock-frequency = <100000000>; 343 }; 344 345 dummy_cmn_refclk1: dummy-cmn-refclk1 { 346 #clock-cells = <0>; 347 compatible = "fixed-clock"; 348 clock-frequency = <100000000>; 349 }; 350 351 serdes_wiz0: wiz@5000000 { 352 compatible = "ti,j721e-wiz-16g"; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 357 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 358 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 359 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 360 num-lanes = <2>; 361 #reset-cells = <1>; 362 ranges = <0x5000000 0x0 0x5000000 0x10000>; 363 364 wiz0_pll0_refclk: pll0-refclk { 365 clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; 366 #clock-cells = <0>; 367 assigned-clocks = <&wiz0_pll0_refclk>; 368 assigned-clock-parents = <&k3_clks 292 11>; 369 }; 370 371 wiz0_pll1_refclk: pll1-refclk { 372 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; 373 #clock-cells = <0>; 374 assigned-clocks = <&wiz0_pll1_refclk>; 375 assigned-clock-parents = <&k3_clks 292 0>; 376 }; 377 378 wiz0_refclk_dig: refclk-dig { 379 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 380 #clock-cells = <0>; 381 assigned-clocks = <&wiz0_refclk_dig>; 382 assigned-clock-parents = <&k3_clks 292 11>; 383 }; 384 385 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 386 clocks = <&wiz0_refclk_dig>; 387 #clock-cells = <0>; 388 }; 389 390 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 391 clocks = <&wiz0_pll1_refclk>; 392 #clock-cells = <0>; 393 }; 394 395 serdes0: serdes@5000000 { 396 compatible = "ti,sierra-phy-t0"; 397 reg-names = "serdes"; 398 reg = <0x5000000 0x10000>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 resets = <&serdes_wiz0 0>; 402 reset-names = "sierra_reset"; 403 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 404 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 405 }; 406 }; 407 408 serdes_wiz1: wiz@5010000 { 409 compatible = "ti,j721e-wiz-16g"; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 413 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; 414 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 415 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 416 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 417 num-lanes = <2>; 418 #reset-cells = <1>; 419 ranges = <0x5010000 0x0 0x5010000 0x10000>; 420 421 wiz1_pll0_refclk: pll0-refclk { 422 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 423 #clock-cells = <0>; 424 assigned-clocks = <&wiz1_pll0_refclk>; 425 assigned-clock-parents = <&k3_clks 293 13>; 426 }; 427 428 wiz1_pll1_refclk: pll1-refclk { 429 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 430 #clock-cells = <0>; 431 assigned-clocks = <&wiz1_pll1_refclk>; 432 assigned-clock-parents = <&k3_clks 293 0>; 433 }; 434 435 wiz1_refclk_dig: refclk-dig { 436 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 437 #clock-cells = <0>; 438 assigned-clocks = <&wiz1_refclk_dig>; 439 assigned-clock-parents = <&k3_clks 293 13>; 440 }; 441 442 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 443 clocks = <&wiz1_refclk_dig>; 444 #clock-cells = <0>; 445 }; 446 447 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 448 clocks = <&wiz1_pll1_refclk>; 449 #clock-cells = <0>; 450 }; 451 452 serdes1: serdes@5010000 { 453 compatible = "ti,sierra-phy-t0"; 454 reg-names = "serdes"; 455 reg = <0x5010000 0x10000>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 resets = <&serdes_wiz1 0>; 459 reset-names = "sierra_reset"; 460 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 461 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 462 }; 463 }; 464 465 serdes_wiz2: wiz@5020000 { 466 compatible = "ti,j721e-wiz-16g"; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 470 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; 471 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 472 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 473 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 474 num-lanes = <2>; 475 #reset-cells = <1>; 476 ranges = <0x5020000 0x0 0x5020000 0x10000>; 477 478 wiz2_pll0_refclk: pll0-refclk { 479 clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; 480 #clock-cells = <0>; 481 assigned-clocks = <&wiz2_pll0_refclk>; 482 assigned-clock-parents = <&k3_clks 294 11>; 483 }; 484 485 wiz2_pll1_refclk: pll1-refclk { 486 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; 487 #clock-cells = <0>; 488 assigned-clocks = <&wiz2_pll1_refclk>; 489 assigned-clock-parents = <&k3_clks 294 0>; 490 }; 491 492 wiz2_refclk_dig: refclk-dig { 493 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 494 #clock-cells = <0>; 495 assigned-clocks = <&wiz2_refclk_dig>; 496 assigned-clock-parents = <&k3_clks 294 11>; 497 }; 498 499 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 500 clocks = <&wiz2_refclk_dig>; 501 #clock-cells = <0>; 502 }; 503 504 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 505 clocks = <&wiz2_pll1_refclk>; 506 #clock-cells = <0>; 507 }; 508 509 serdes2: serdes@5020000 { 510 compatible = "ti,sierra-phy-t0"; 511 reg-names = "serdes"; 512 reg = <0x5020000 0x10000>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 resets = <&serdes_wiz2 0>; 516 reset-names = "sierra_reset"; 517 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 518 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 519 }; 520 }; 521 522 serdes_wiz3: wiz@5030000 { 523 compatible = "ti,j721e-wiz-16g"; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 527 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; 528 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 529 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 530 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 531 num-lanes = <2>; 532 #reset-cells = <1>; 533 ranges = <0x5030000 0x0 0x5030000 0x10000>; 534 535 wiz3_pll0_refclk: pll0-refclk { 536 clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; 537 #clock-cells = <0>; 538 assigned-clocks = <&wiz3_pll0_refclk>; 539 assigned-clock-parents = <&k3_clks 295 9>; 540 }; 541 542 wiz3_pll1_refclk: pll1-refclk { 543 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; 544 #clock-cells = <0>; 545 assigned-clocks = <&wiz3_pll1_refclk>; 546 assigned-clock-parents = <&k3_clks 295 0>; 547 }; 548 549 wiz3_refclk_dig: refclk-dig { 550 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 551 #clock-cells = <0>; 552 assigned-clocks = <&wiz3_refclk_dig>; 553 assigned-clock-parents = <&k3_clks 295 9>; 554 }; 555 556 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 557 clocks = <&wiz3_refclk_dig>; 558 #clock-cells = <0>; 559 }; 560 561 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 562 clocks = <&wiz3_pll1_refclk>; 563 #clock-cells = <0>; 564 }; 565 566 serdes3: serdes@5030000 { 567 compatible = "ti,sierra-phy-t0"; 568 reg-names = "serdes"; 569 reg = <0x5030000 0x10000>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 resets = <&serdes_wiz3 0>; 573 reset-names = "sierra_reset"; 574 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 575 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 576 }; 577 }; 578 579 main_uart0: serial@2800000 { 580 compatible = "ti,j721e-uart", "ti,am654-uart"; 581 reg = <0x00 0x02800000 0x00 0x100>; 582 reg-shift = <2>; 583 reg-io-width = <4>; 584 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 585 clock-frequency = <48000000>; 586 current-speed = <115200>; 587 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 588 clocks = <&k3_clks 146 0>; 589 clock-names = "fclk"; 590 }; 591 592 main_uart1: serial@2810000 { 593 compatible = "ti,j721e-uart", "ti,am654-uart"; 594 reg = <0x00 0x02810000 0x00 0x100>; 595 reg-shift = <2>; 596 reg-io-width = <4>; 597 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 598 clock-frequency = <48000000>; 599 current-speed = <115200>; 600 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 601 clocks = <&k3_clks 278 0>; 602 clock-names = "fclk"; 603 }; 604 605 main_uart2: serial@2820000 { 606 compatible = "ti,j721e-uart", "ti,am654-uart"; 607 reg = <0x00 0x02820000 0x00 0x100>; 608 reg-shift = <2>; 609 reg-io-width = <4>; 610 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 611 clock-frequency = <48000000>; 612 current-speed = <115200>; 613 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 614 clocks = <&k3_clks 279 0>; 615 clock-names = "fclk"; 616 }; 617 618 main_uart3: serial@2830000 { 619 compatible = "ti,j721e-uart", "ti,am654-uart"; 620 reg = <0x00 0x02830000 0x00 0x100>; 621 reg-shift = <2>; 622 reg-io-width = <4>; 623 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 624 clock-frequency = <48000000>; 625 current-speed = <115200>; 626 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 627 clocks = <&k3_clks 280 0>; 628 clock-names = "fclk"; 629 }; 630 631 main_uart4: serial@2840000 { 632 compatible = "ti,j721e-uart", "ti,am654-uart"; 633 reg = <0x00 0x02840000 0x00 0x100>; 634 reg-shift = <2>; 635 reg-io-width = <4>; 636 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 637 clock-frequency = <48000000>; 638 current-speed = <115200>; 639 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 640 clocks = <&k3_clks 281 0>; 641 clock-names = "fclk"; 642 }; 643 644 main_uart5: serial@2850000 { 645 compatible = "ti,j721e-uart", "ti,am654-uart"; 646 reg = <0x00 0x02850000 0x00 0x100>; 647 reg-shift = <2>; 648 reg-io-width = <4>; 649 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 650 clock-frequency = <48000000>; 651 current-speed = <115200>; 652 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 653 clocks = <&k3_clks 282 0>; 654 clock-names = "fclk"; 655 }; 656 657 main_uart6: serial@2860000 { 658 compatible = "ti,j721e-uart", "ti,am654-uart"; 659 reg = <0x00 0x02860000 0x00 0x100>; 660 reg-shift = <2>; 661 reg-io-width = <4>; 662 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 663 clock-frequency = <48000000>; 664 current-speed = <115200>; 665 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 666 clocks = <&k3_clks 283 0>; 667 clock-names = "fclk"; 668 }; 669 670 main_uart7: serial@2870000 { 671 compatible = "ti,j721e-uart", "ti,am654-uart"; 672 reg = <0x00 0x02870000 0x00 0x100>; 673 reg-shift = <2>; 674 reg-io-width = <4>; 675 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 676 clock-frequency = <48000000>; 677 current-speed = <115200>; 678 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 679 clocks = <&k3_clks 284 0>; 680 clock-names = "fclk"; 681 }; 682 683 main_uart8: serial@2880000 { 684 compatible = "ti,j721e-uart", "ti,am654-uart"; 685 reg = <0x00 0x02880000 0x00 0x100>; 686 reg-shift = <2>; 687 reg-io-width = <4>; 688 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 689 clock-frequency = <48000000>; 690 current-speed = <115200>; 691 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 692 clocks = <&k3_clks 285 0>; 693 clock-names = "fclk"; 694 }; 695 696 main_uart9: serial@2890000 { 697 compatible = "ti,j721e-uart", "ti,am654-uart"; 698 reg = <0x00 0x02890000 0x00 0x100>; 699 reg-shift = <2>; 700 reg-io-width = <4>; 701 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 702 clock-frequency = <48000000>; 703 current-speed = <115200>; 704 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 705 clocks = <&k3_clks 286 0>; 706 clock-names = "fclk"; 707 }; 708 709 main_gpio0: gpio@600000 { 710 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 711 reg = <0x0 0x00600000 0x0 0x100>; 712 gpio-controller; 713 #gpio-cells = <2>; 714 interrupt-parent = <&main_gpio_intr>; 715 interrupts = <256>, <257>, <258>, <259>, 716 <260>, <261>, <262>, <263>; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 ti,ngpio = <128>; 720 ti,davinci-gpio-unbanked = <0>; 721 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 722 clocks = <&k3_clks 105 0>; 723 clock-names = "gpio"; 724 }; 725 726 main_gpio1: gpio@601000 { 727 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 728 reg = <0x0 0x00601000 0x0 0x100>; 729 gpio-controller; 730 #gpio-cells = <2>; 731 interrupt-parent = <&main_gpio_intr>; 732 interrupts = <288>, <289>, <290>; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 ti,ngpio = <36>; 736 ti,davinci-gpio-unbanked = <0>; 737 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 738 clocks = <&k3_clks 106 0>; 739 clock-names = "gpio"; 740 }; 741 742 main_gpio2: gpio@610000 { 743 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 744 reg = <0x0 0x00610000 0x0 0x100>; 745 gpio-controller; 746 #gpio-cells = <2>; 747 interrupt-parent = <&main_gpio_intr>; 748 interrupts = <264>, <265>, <266>, <267>, 749 <268>, <269>, <270>, <271>; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 ti,ngpio = <128>; 753 ti,davinci-gpio-unbanked = <0>; 754 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 107 0>; 756 clock-names = "gpio"; 757 }; 758 759 main_gpio3: gpio@611000 { 760 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 761 reg = <0x0 0x00611000 0x0 0x100>; 762 gpio-controller; 763 #gpio-cells = <2>; 764 interrupt-parent = <&main_gpio_intr>; 765 interrupts = <292>, <293>, <294>; 766 interrupt-controller; 767 #interrupt-cells = <2>; 768 ti,ngpio = <36>; 769 ti,davinci-gpio-unbanked = <0>; 770 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 771 clocks = <&k3_clks 108 0>; 772 clock-names = "gpio"; 773 }; 774 775 main_gpio4: gpio@620000 { 776 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 777 reg = <0x0 0x00620000 0x0 0x100>; 778 gpio-controller; 779 #gpio-cells = <2>; 780 interrupt-parent = <&main_gpio_intr>; 781 interrupts = <272>, <273>, <274>, <275>, 782 <276>, <277>, <278>, <279>; 783 interrupt-controller; 784 #interrupt-cells = <2>; 785 ti,ngpio = <128>; 786 ti,davinci-gpio-unbanked = <0>; 787 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 788 clocks = <&k3_clks 109 0>; 789 clock-names = "gpio"; 790 }; 791 792 main_gpio5: gpio@621000 { 793 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 794 reg = <0x0 0x00621000 0x0 0x100>; 795 gpio-controller; 796 #gpio-cells = <2>; 797 interrupt-parent = <&main_gpio_intr>; 798 interrupts = <296>, <297>, <298>; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 ti,ngpio = <36>; 802 ti,davinci-gpio-unbanked = <0>; 803 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 804 clocks = <&k3_clks 110 0>; 805 clock-names = "gpio"; 806 }; 807 808 main_gpio6: gpio@630000 { 809 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 810 reg = <0x0 0x00630000 0x0 0x100>; 811 gpio-controller; 812 #gpio-cells = <2>; 813 interrupt-parent = <&main_gpio_intr>; 814 interrupts = <280>, <281>, <282>, <283>, 815 <284>, <285>, <286>, <287>; 816 interrupt-controller; 817 #interrupt-cells = <2>; 818 ti,ngpio = <128>; 819 ti,davinci-gpio-unbanked = <0>; 820 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 821 clocks = <&k3_clks 111 0>; 822 clock-names = "gpio"; 823 }; 824 825 main_gpio7: gpio@631000 { 826 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 827 reg = <0x0 0x00631000 0x0 0x100>; 828 gpio-controller; 829 #gpio-cells = <2>; 830 interrupt-parent = <&main_gpio_intr>; 831 interrupts = <300>, <301>, <302>; 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 ti,ngpio = <36>; 835 ti,davinci-gpio-unbanked = <0>; 836 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 837 clocks = <&k3_clks 112 0>; 838 clock-names = "gpio"; 839 }; 840 841 main_sdhci0: sdhci@4f80000 { 842 compatible = "ti,j721e-sdhci-8bit"; 843 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 844 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 845 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 846 clock-names = "clk_xin", "clk_ahb"; 847 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 848 assigned-clocks = <&k3_clks 91 1>; 849 assigned-clock-parents = <&k3_clks 91 2>; 850 bus-width = <8>; 851 mmc-hs400-1_8v; 852 mmc-ddr-1_8v; 853 ti,otap-del-sel = <0x2>; 854 ti,trm-icp = <0x8>; 855 ti,strobe-sel = <0x77>; 856 dma-coherent; 857 }; 858 859 main_sdhci1: sdhci@4fb0000 { 860 compatible = "ti,j721e-sdhci-4bit"; 861 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 862 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 863 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 864 clock-names = "clk_xin", "clk_ahb"; 865 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 866 assigned-clocks = <&k3_clks 92 0>; 867 assigned-clock-parents = <&k3_clks 92 1>; 868 ti,otap-del-sel = <0x2>; 869 ti,trm-icp = <0x8>; 870 ti,clkbuf-sel = <0x7>; 871 dma-coherent; 872 no-1-8-v; 873 }; 874 875 main_sdhci2: sdhci@4f98000 { 876 compatible = "ti,j721e-sdhci-4bit"; 877 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 878 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 879 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 880 clock-names = "clk_xin", "clk_ahb"; 881 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 882 assigned-clocks = <&k3_clks 93 0>; 883 assigned-clock-parents = <&k3_clks 93 1>; 884 ti,otap-del-sel = <0x2>; 885 ti,trm-icp = <0x8>; 886 ti,clkbuf-sel = <0x7>; 887 dma-coherent; 888 no-1-8-v; 889 }; 890 891 usbss0: cdns_usb@4104000 { 892 compatible = "ti,j721e-usb"; 893 reg = <0x00 0x4104000 0x00 0x100>; 894 dma-coherent; 895 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 896 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 897 clock-names = "ref", "lpm"; 898 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 899 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 900 #address-cells = <2>; 901 #size-cells = <2>; 902 ranges; 903 904 usb0: usb@6000000 { 905 compatible = "cdns,usb3"; 906 reg = <0x00 0x6000000 0x00 0x10000>, 907 <0x00 0x6010000 0x00 0x10000>, 908 <0x00 0x6020000 0x00 0x10000>; 909 reg-names = "otg", "xhci", "dev"; 910 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 911 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 912 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 913 interrupt-names = "host", 914 "peripheral", 915 "otg"; 916 maximum-speed = "super-speed"; 917 dr_mode = "otg"; 918 }; 919 }; 920 921 usbss1: cdns_usb@4114000 { 922 compatible = "ti,j721e-usb"; 923 reg = <0x00 0x4114000 0x00 0x100>; 924 dma-coherent; 925 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 926 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 927 clock-names = "ref", "lpm"; 928 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 929 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 930 #address-cells = <2>; 931 #size-cells = <2>; 932 ranges; 933 934 usb1: usb@6400000 { 935 compatible = "cdns,usb3"; 936 reg = <0x00 0x6400000 0x00 0x10000>, 937 <0x00 0x6410000 0x00 0x10000>, 938 <0x00 0x6420000 0x00 0x10000>; 939 reg-names = "otg", "xhci", "dev"; 940 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 941 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 942 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 943 interrupt-names = "host", 944 "peripheral", 945 "otg"; 946 maximum-speed = "super-speed"; 947 dr_mode = "otg"; 948 }; 949 }; 950 951 main_i2c0: i2c@2000000 { 952 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 953 reg = <0x0 0x2000000 0x0 0x100>; 954 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 clock-names = "fck"; 958 clocks = <&k3_clks 187 0>; 959 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 960 }; 961 962 main_i2c1: i2c@2010000 { 963 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 964 reg = <0x0 0x2010000 0x0 0x100>; 965 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 clock-names = "fck"; 969 clocks = <&k3_clks 188 0>; 970 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 971 }; 972 973 main_i2c2: i2c@2020000 { 974 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 975 reg = <0x0 0x2020000 0x0 0x100>; 976 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 clock-names = "fck"; 980 clocks = <&k3_clks 189 0>; 981 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 982 }; 983 984 main_i2c3: i2c@2030000 { 985 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 986 reg = <0x0 0x2030000 0x0 0x100>; 987 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 clock-names = "fck"; 991 clocks = <&k3_clks 190 0>; 992 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 993 }; 994 995 main_i2c4: i2c@2040000 { 996 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 997 reg = <0x0 0x2040000 0x0 0x100>; 998 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 clock-names = "fck"; 1002 clocks = <&k3_clks 191 0>; 1003 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1004 }; 1005 1006 main_i2c5: i2c@2050000 { 1007 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1008 reg = <0x0 0x2050000 0x0 0x100>; 1009 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clock-names = "fck"; 1013 clocks = <&k3_clks 192 0>; 1014 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1015 }; 1016 1017 main_i2c6: i2c@2060000 { 1018 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1019 reg = <0x0 0x2060000 0x0 0x100>; 1020 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 clock-names = "fck"; 1024 clocks = <&k3_clks 193 0>; 1025 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1026 }; 1027 1028 ufs_wrapper: ufs-wrapper@4e80000 { 1029 compatible = "ti,j721e-ufs"; 1030 reg = <0x0 0x4e80000 0x0 0x100>; 1031 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1032 clocks = <&k3_clks 277 1>; 1033 assigned-clocks = <&k3_clks 277 1>; 1034 assigned-clock-parents = <&k3_clks 277 4>; 1035 ranges; 1036 #address-cells = <2>; 1037 #size-cells = <2>; 1038 1039 ufs@4e84000 { 1040 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1041 reg = <0x0 0x4e84000 0x0 0x10000>; 1042 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1043 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1044 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1045 clock-names = "core_clk", "phy_clk", "ref_clk"; 1046 dma-coherent; 1047 }; 1048 }; 1049 1050 dss: dss@04a00000 { 1051 compatible = "ti,j721e-dss"; 1052 reg = 1053 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1054 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1055 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1056 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1057 1058 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1059 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1060 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1061 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1062 1063 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1064 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1065 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1066 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1067 1068 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1069 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1070 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1071 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1072 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1073 1074 reg-names = "common_m", "common_s0", 1075 "common_s1", "common_s2", 1076 "vidl1", "vidl2","vid1","vid2", 1077 "ovr1", "ovr2", "ovr3", "ovr4", 1078 "vp1", "vp2", "vp3", "vp4", 1079 "wb"; 1080 1081 clocks = <&k3_clks 152 0>, 1082 <&k3_clks 152 1>, 1083 <&k3_clks 152 4>, 1084 <&k3_clks 152 9>, 1085 <&k3_clks 152 13>; 1086 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1087 1088 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1089 1090 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1094 interrupt-names = "common_m", 1095 "common_s0", 1096 "common_s1", 1097 "common_s2"; 1098 1099 status = "disabled"; 1100 1101 dss_ports: ports { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 }; 1105 }; 1106 1107 mcasp0: mcasp@2b00000 { 1108 compatible = "ti,am33xx-mcasp-audio"; 1109 reg = <0x0 0x02b00000 0x0 0x2000>, 1110 <0x0 0x02b08000 0x0 0x1000>; 1111 reg-names = "mpu","dat"; 1112 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1114 interrupt-names = "tx", "rx"; 1115 1116 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1117 dma-names = "tx", "rx"; 1118 1119 clocks = <&k3_clks 174 1>; 1120 clock-names = "fck"; 1121 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1122 1123 status = "disabled"; 1124 }; 1125 1126 mcasp1: mcasp@2b10000 { 1127 compatible = "ti,am33xx-mcasp-audio"; 1128 reg = <0x0 0x02b10000 0x0 0x2000>, 1129 <0x0 0x02b18000 0x0 0x1000>; 1130 reg-names = "mpu","dat"; 1131 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1133 interrupt-names = "tx", "rx"; 1134 1135 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1136 dma-names = "tx", "rx"; 1137 1138 clocks = <&k3_clks 175 1>; 1139 clock-names = "fck"; 1140 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1141 1142 status = "disabled"; 1143 }; 1144 1145 mcasp2: mcasp@2b20000 { 1146 compatible = "ti,am33xx-mcasp-audio"; 1147 reg = <0x0 0x02b20000 0x0 0x2000>, 1148 <0x0 0x02b28000 0x0 0x1000>; 1149 reg-names = "mpu","dat"; 1150 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1152 interrupt-names = "tx", "rx"; 1153 1154 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1155 dma-names = "tx", "rx"; 1156 1157 clocks = <&k3_clks 176 1>; 1158 clock-names = "fck"; 1159 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1160 1161 status = "disabled"; 1162 }; 1163 1164 mcasp3: mcasp@2b30000 { 1165 compatible = "ti,am33xx-mcasp-audio"; 1166 reg = <0x0 0x02b30000 0x0 0x2000>, 1167 <0x0 0x02b38000 0x0 0x1000>; 1168 reg-names = "mpu","dat"; 1169 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "tx", "rx"; 1172 1173 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1174 dma-names = "tx", "rx"; 1175 1176 clocks = <&k3_clks 177 1>; 1177 clock-names = "fck"; 1178 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1179 1180 status = "disabled"; 1181 }; 1182 1183 mcasp4: mcasp@2b40000 { 1184 compatible = "ti,am33xx-mcasp-audio"; 1185 reg = <0x0 0x02b40000 0x0 0x2000>, 1186 <0x0 0x02b48000 0x0 0x1000>; 1187 reg-names = "mpu","dat"; 1188 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1190 interrupt-names = "tx", "rx"; 1191 1192 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1193 dma-names = "tx", "rx"; 1194 1195 clocks = <&k3_clks 178 1>; 1196 clock-names = "fck"; 1197 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1198 1199 status = "disabled"; 1200 }; 1201 1202 mcasp5: mcasp@2b50000 { 1203 compatible = "ti,am33xx-mcasp-audio"; 1204 reg = <0x0 0x02b50000 0x0 0x2000>, 1205 <0x0 0x02b58000 0x0 0x1000>; 1206 reg-names = "mpu","dat"; 1207 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1209 interrupt-names = "tx", "rx"; 1210 1211 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1212 dma-names = "tx", "rx"; 1213 1214 clocks = <&k3_clks 179 1>; 1215 clock-names = "fck"; 1216 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1217 1218 status = "disabled"; 1219 }; 1220 1221 mcasp6: mcasp@2b60000 { 1222 compatible = "ti,am33xx-mcasp-audio"; 1223 reg = <0x0 0x02b60000 0x0 0x2000>, 1224 <0x0 0x02b68000 0x0 0x1000>; 1225 reg-names = "mpu","dat"; 1226 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1228 interrupt-names = "tx", "rx"; 1229 1230 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1231 dma-names = "tx", "rx"; 1232 1233 clocks = <&k3_clks 180 1>; 1234 clock-names = "fck"; 1235 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1236 1237 status = "disabled"; 1238 }; 1239 1240 mcasp7: mcasp@2b70000 { 1241 compatible = "ti,am33xx-mcasp-audio"; 1242 reg = <0x0 0x02b70000 0x0 0x2000>, 1243 <0x0 0x02b78000 0x0 0x1000>; 1244 reg-names = "mpu","dat"; 1245 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1247 interrupt-names = "tx", "rx"; 1248 1249 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1250 dma-names = "tx", "rx"; 1251 1252 clocks = <&k3_clks 181 1>; 1253 clock-names = "fck"; 1254 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1255 1256 status = "disabled"; 1257 }; 1258 1259 mcasp8: mcasp@2b80000 { 1260 compatible = "ti,am33xx-mcasp-audio"; 1261 reg = <0x0 0x02b80000 0x0 0x2000>, 1262 <0x0 0x02b88000 0x0 0x1000>; 1263 reg-names = "mpu","dat"; 1264 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1266 interrupt-names = "tx", "rx"; 1267 1268 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1269 dma-names = "tx", "rx"; 1270 1271 clocks = <&k3_clks 182 1>; 1272 clock-names = "fck"; 1273 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1274 1275 status = "disabled"; 1276 }; 1277 1278 mcasp9: mcasp@2b90000 { 1279 compatible = "ti,am33xx-mcasp-audio"; 1280 reg = <0x0 0x02b90000 0x0 0x2000>, 1281 <0x0 0x02b98000 0x0 0x1000>; 1282 reg-names = "mpu","dat"; 1283 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1285 interrupt-names = "tx", "rx"; 1286 1287 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1288 dma-names = "tx", "rx"; 1289 1290 clocks = <&k3_clks 183 1>; 1291 clock-names = "fck"; 1292 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1293 1294 status = "disabled"; 1295 }; 1296 1297 mcasp10: mcasp@2ba0000 { 1298 compatible = "ti,am33xx-mcasp-audio"; 1299 reg = <0x0 0x02ba0000 0x0 0x2000>, 1300 <0x0 0x02ba8000 0x0 0x1000>; 1301 reg-names = "mpu","dat"; 1302 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1304 interrupt-names = "tx", "rx"; 1305 1306 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1307 dma-names = "tx", "rx"; 1308 1309 clocks = <&k3_clks 184 1>; 1310 clock-names = "fck"; 1311 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1312 1313 status = "disabled"; 1314 }; 1315 1316 mcasp11: mcasp@2bb0000 { 1317 compatible = "ti,am33xx-mcasp-audio"; 1318 reg = <0x0 0x02bb0000 0x0 0x2000>, 1319 <0x0 0x02bb8000 0x0 0x1000>; 1320 reg-names = "mpu","dat"; 1321 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1323 interrupt-names = "tx", "rx"; 1324 1325 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1326 dma-names = "tx", "rx"; 1327 1328 clocks = <&k3_clks 185 1>; 1329 clock-names = "fck"; 1330 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1331 1332 status = "disabled"; 1333 }; 1334 1335 watchdog0: watchdog@2200000 { 1336 compatible = "ti,j7-rti-wdt"; 1337 reg = <0x0 0x2200000 0x0 0x100>; 1338 clocks = <&k3_clks 252 1>; 1339 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1340 assigned-clocks = <&k3_clks 252 1>; 1341 assigned-clock-parents = <&k3_clks 252 5>; 1342 }; 1343 1344 watchdog1: watchdog@2210000 { 1345 compatible = "ti,j7-rti-wdt"; 1346 reg = <0x0 0x2210000 0x0 0x100>; 1347 clocks = <&k3_clks 253 1>; 1348 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1349 assigned-clocks = <&k3_clks 253 1>; 1350 assigned-clock-parents = <&k3_clks 253 5>; 1351 }; 1352 1353 c66_0: dsp@4d80800000 { 1354 compatible = "ti,j721e-c66-dsp"; 1355 reg = <0x4d 0x80800000 0x00 0x00048000>, 1356 <0x4d 0x80e00000 0x00 0x00008000>, 1357 <0x4d 0x80f00000 0x00 0x00008000>; 1358 reg-names = "l2sram", "l1pram", "l1dram"; 1359 ti,sci = <&dmsc>; 1360 ti,sci-dev-id = <142>; 1361 ti,sci-proc-ids = <0x03 0xff>; 1362 resets = <&k3_reset 142 1>; 1363 firmware-name = "j7-c66_0-fw"; 1364 }; 1365 1366 c66_1: dsp@4d81800000 { 1367 compatible = "ti,j721e-c66-dsp"; 1368 reg = <0x4d 0x81800000 0x00 0x00048000>, 1369 <0x4d 0x81e00000 0x00 0x00008000>, 1370 <0x4d 0x81f00000 0x00 0x00008000>; 1371 reg-names = "l2sram", "l1pram", "l1dram"; 1372 ti,sci = <&dmsc>; 1373 ti,sci-dev-id = <143>; 1374 ti,sci-proc-ids = <0x04 0xff>; 1375 resets = <&k3_reset 143 1>; 1376 firmware-name = "j7-c66_1-fw"; 1377 }; 1378}; 1379