SPDX: Convert all of our single license tags to Linux Kernel styleWhen U-Boot started using SPDX tags we were among the early adopters andthere weren't a lot of other examples to borrow from. So
SPDX: Convert all of our single license tags to Linux Kernel styleWhen U-Boot started using SPDX tags we were among the early adopters andthere weren't a lot of other examples to borrow from. So we picked thearea of the file that usually had a full license text and replaced itwith an appropriate SPDX-License-Identifier: entry. Since then, theLinux Kernel has adopted SPDX tags and they place it as the very firstline in a file (except where shebangs are used, then it's second line)and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibilityand in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declaredlicense in the tag as both the before and after are identical in tagcontents. There's also a few places where I found we did not have a tagand have introduced one.Signed-off-by: Tom Rini <trini@konsulko.com>
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arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1Adding new handoff for SDRAM ctrcfg.extratime1 which isrequired for stable LPDDR2 operation. Since the board isusing DDR3, the handof
arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1Adding new handoff for SDRAM ctrcfg.extratime1 which isrequired for stable LPDDR2 operation. Since the board isusing DDR3, the handoff is set to default value 0.Signed-off-by: Chin Liang See <clsee@altera.com>Cc: Marek Vasut <marex@denx.de>Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
ARM: socfpga: add support for IS1 boardThis adds support for IS1 board. Pretty usual socfpga board,256MB of RAM, does not have MMC, two SPI chips, one ethernet port, twoadditional ethernet ports
ARM: socfpga: add support for IS1 boardThis adds support for IS1 board. Pretty usual socfpga board,256MB of RAM, does not have MMC, two SPI chips, one ethernet port, twoadditional ethernet ports connected to the FPGA.Signed-off-by: Pavel Machek <pavel@denx.de>