xref: /openbmc/u-boot/drivers/mmc/pxa_mmc_gen.c (revision 35546f6f2014282cc4f9772324b5588bd44a2938)
1  /*
2   * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
3   *
4   * Loosely based on the old code and Linux's PXA MMC driver
5   *
6   * SPDX-License-Identifier:	GPL-2.0+
7   */
8  
9  #include <common.h>
10  #include <asm/arch/hardware.h>
11  #include <asm/arch/regs-mmc.h>
12  #include <asm/errno.h>
13  #include <asm/io.h>
14  #include <malloc.h>
15  #include <mmc.h>
16  
17  /* PXAMMC Generic default config for various CPUs */
18  #if defined(CONFIG_CPU_PXA25X)
19  #define PXAMMC_FIFO_SIZE	1
20  #define PXAMMC_MIN_SPEED	312500
21  #define PXAMMC_MAX_SPEED	20000000
22  #define PXAMMC_HOST_CAPS	(0)
23  #elif defined(CONFIG_CPU_PXA27X)
24  #define PXAMMC_CRC_SKIP
25  #define PXAMMC_FIFO_SIZE	32
26  #define PXAMMC_MIN_SPEED	304000
27  #define PXAMMC_MAX_SPEED	19500000
28  #define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT)
29  #elif defined(CONFIG_CPU_MONAHANS)
30  #define PXAMMC_FIFO_SIZE	32
31  #define PXAMMC_MIN_SPEED	304000
32  #define PXAMMC_MAX_SPEED	26000000
33  #define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT | MMC_MODE_HS)
34  #else
35  #error "This CPU isn't supported by PXA MMC!"
36  #endif
37  
38  #define MMC_STAT_ERRORS							\
39  	(MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN |	\
40  	MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE |		\
41  	MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
42  
43  /* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
44  #define PXA_MMC_TIMEOUT	100
45  
46  struct pxa_mmc_priv {
47  	struct pxa_mmc_regs *regs;
48  };
49  
50  /* Wait for bit to be set */
51  static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
52  {
53  	struct pxa_mmc_priv *priv = mmc->priv;
54  	struct pxa_mmc_regs *regs = priv->regs;
55  	unsigned int timeout = PXA_MMC_TIMEOUT;
56  
57  	/* Wait for bit to be set */
58  	while (--timeout) {
59  		if (readl(&regs->stat) & mask)
60  			break;
61  		udelay(10);
62  	}
63  
64  	if (!timeout)
65  		return -ETIMEDOUT;
66  
67  	return 0;
68  }
69  
70  static int pxa_mmc_stop_clock(struct mmc *mmc)
71  {
72  	struct pxa_mmc_priv *priv = mmc->priv;
73  	struct pxa_mmc_regs *regs = priv->regs;
74  	unsigned int timeout = PXA_MMC_TIMEOUT;
75  
76  	/* If the clock aren't running, exit */
77  	if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
78  		return 0;
79  
80  	/* Tell the controller to turn off the clock */
81  	writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
82  
83  	/* Wait until the clock are off */
84  	while (--timeout) {
85  		if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
86  			break;
87  		udelay(10);
88  	}
89  
90  	/* The clock refused to stop, scream and die a painful death */
91  	if (!timeout)
92  		return -ETIMEDOUT;
93  
94  	/* The clock stopped correctly */
95  	return 0;
96  }
97  
98  static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
99  				uint32_t cmdat)
100  {
101  	struct pxa_mmc_priv *priv = mmc->priv;
102  	struct pxa_mmc_regs *regs = priv->regs;
103  	int ret;
104  
105  	/* The card can send a "busy" response */
106  	if (cmd->resp_type & MMC_RSP_BUSY)
107  		cmdat |= MMC_CMDAT_BUSY;
108  
109  	/* Inform the controller about response type */
110  	switch (cmd->resp_type) {
111  	case MMC_RSP_R1:
112  	case MMC_RSP_R1b:
113  		cmdat |= MMC_CMDAT_R1;
114  		break;
115  	case MMC_RSP_R2:
116  		cmdat |= MMC_CMDAT_R2;
117  		break;
118  	case MMC_RSP_R3:
119  		cmdat |= MMC_CMDAT_R3;
120  		break;
121  	default:
122  		break;
123  	}
124  
125  	/* Load command and it's arguments into the controller */
126  	writel(cmd->cmdidx, &regs->cmd);
127  	writel(cmd->cmdarg >> 16, &regs->argh);
128  	writel(cmd->cmdarg & 0xffff, &regs->argl);
129  	writel(cmdat, &regs->cmdat);
130  
131  	/* Start the controller clock and wait until they are started */
132  	writel(MMC_STRPCL_START_CLK, &regs->strpcl);
133  
134  	ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
135  	if (ret)
136  		return ret;
137  
138  	/* Correct and happy end */
139  	return 0;
140  }
141  
142  static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
143  {
144  	struct pxa_mmc_priv *priv = mmc->priv;
145  	struct pxa_mmc_regs *regs = priv->regs;
146  	uint32_t a, b, c;
147  	int i;
148  	int stat;
149  
150  	/* Read the controller status */
151  	stat = readl(&regs->stat);
152  
153  	/*
154  	 * Linux says:
155  	 * Did I mention this is Sick.  We always need to
156  	 * discard the upper 8 bits of the first 16-bit word.
157  	 */
158  	a = readl(&regs->res) & 0xffff;
159  	for (i = 0; i < 4; i++) {
160  		b = readl(&regs->res) & 0xffff;
161  		c = readl(&regs->res) & 0xffff;
162  		cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
163  		a = c;
164  	}
165  
166  	/* The command response didn't arrive */
167  	if (stat & MMC_STAT_TIME_OUT_RESPONSE)
168  		return -ETIMEDOUT;
169  	else if (stat & MMC_STAT_RES_CRC_ERROR
170  			&& cmd->resp_type & MMC_RSP_CRC) {
171  #ifdef	PXAMMC_CRC_SKIP
172  		if (cmd->resp_type & MMC_RSP_136
173  				&& cmd->response[0] & (1 << 31))
174  			printf("Ignoring CRC, this may be dangerous!\n");
175  		else
176  #endif
177  		return -EILSEQ;
178  	}
179  
180  	/* The command response was successfully read */
181  	return 0;
182  }
183  
184  static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
185  {
186  	struct pxa_mmc_priv *priv = mmc->priv;
187  	struct pxa_mmc_regs *regs = priv->regs;
188  	uint32_t len;
189  	uint32_t *buf = (uint32_t *)data->dest;
190  	int size;
191  	int ret;
192  
193  	len = data->blocks * data->blocksize;
194  
195  	while (len) {
196  		/* The controller has data ready */
197  		if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
198  			size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
199  			len -= size;
200  			size /= 4;
201  
202  			/* Read data into the buffer */
203  			while (size--)
204  				*buf++ = readl(&regs->rxfifo);
205  
206  		}
207  
208  		if (readl(&regs->stat) & MMC_STAT_ERRORS)
209  			return -EIO;
210  	}
211  
212  	/* Wait for the transmission-done interrupt */
213  	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
214  	if (ret)
215  		return ret;
216  
217  	return 0;
218  }
219  
220  static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
221  {
222  	struct pxa_mmc_priv *priv = mmc->priv;
223  	struct pxa_mmc_regs *regs = priv->regs;
224  	uint32_t len;
225  	uint32_t *buf = (uint32_t *)data->src;
226  	int size;
227  	int ret;
228  
229  	len = data->blocks * data->blocksize;
230  
231  	while (len) {
232  		/* The controller is ready to receive data */
233  		if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
234  			size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
235  			len -= size;
236  			size /= 4;
237  
238  			while (size--)
239  				writel(*buf++, &regs->txfifo);
240  
241  			if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
242  				writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
243  		}
244  
245  		if (readl(&regs->stat) & MMC_STAT_ERRORS)
246  			return -EIO;
247  	}
248  
249  	/* Wait for the transmission-done interrupt */
250  	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
251  	if (ret)
252  		return ret;
253  
254  	/* Wait until the data are really written to the card */
255  	ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
256  	if (ret)
257  		return ret;
258  
259  	return 0;
260  }
261  
262  static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
263  				struct mmc_data *data)
264  {
265  	struct pxa_mmc_priv *priv = mmc->priv;
266  	struct pxa_mmc_regs *regs = priv->regs;
267  	uint32_t cmdat = 0;
268  	int ret;
269  
270  	/* Stop the controller */
271  	ret = pxa_mmc_stop_clock(mmc);
272  	if (ret)
273  		return ret;
274  
275  	/* If we're doing data transfer, configure the controller accordingly */
276  	if (data) {
277  		writel(data->blocks, &regs->nob);
278  		writel(data->blocksize, &regs->blklen);
279  		/* This delay can be optimized, but stick with max value */
280  		writel(0xffff, &regs->rdto);
281  		cmdat |= MMC_CMDAT_DATA_EN;
282  		if (data->flags & MMC_DATA_WRITE)
283  			cmdat |= MMC_CMDAT_WRITE;
284  	}
285  
286  	/* Run in 4bit mode if the card can do it */
287  	if (mmc->bus_width == 4)
288  		cmdat |= MMC_CMDAT_SD_4DAT;
289  
290  	/* Execute the command */
291  	ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
292  	if (ret)
293  		return ret;
294  
295  	/* Wait until the command completes */
296  	ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
297  	if (ret)
298  		return ret;
299  
300  	/* Read back the result */
301  	ret = pxa_mmc_cmd_done(mmc, cmd);
302  	if (ret)
303  		return ret;
304  
305  	/* In case there was a data transfer scheduled, do it */
306  	if (data) {
307  		if (data->flags & MMC_DATA_WRITE)
308  			pxa_mmc_do_write_xfer(mmc, data);
309  		else
310  			pxa_mmc_do_read_xfer(mmc, data);
311  	}
312  
313  	return 0;
314  }
315  
316  static void pxa_mmc_set_ios(struct mmc *mmc)
317  {
318  	struct pxa_mmc_priv *priv = mmc->priv;
319  	struct pxa_mmc_regs *regs = priv->regs;
320  	uint32_t tmp;
321  	uint32_t pxa_mmc_clock;
322  
323  	if (!mmc->clock) {
324  		pxa_mmc_stop_clock(mmc);
325  		return;
326  	}
327  
328  	/* PXA3xx can do 26MHz with special settings. */
329  	if (mmc->clock == 26000000) {
330  		writel(0x7, &regs->clkrt);
331  		return;
332  	}
333  
334  	/* Set clock to the card the usual way. */
335  	pxa_mmc_clock = 0;
336  	tmp = mmc->cfg->f_max / mmc->clock;
337  	tmp += tmp % 2;
338  
339  	while (tmp > 1) {
340  		pxa_mmc_clock++;
341  		tmp >>= 1;
342  	}
343  
344  	writel(pxa_mmc_clock, &regs->clkrt);
345  }
346  
347  static int pxa_mmc_init(struct mmc *mmc)
348  {
349  	struct pxa_mmc_priv *priv = mmc->priv;
350  	struct pxa_mmc_regs *regs = priv->regs;
351  
352  	/* Make sure the clock are stopped */
353  	pxa_mmc_stop_clock(mmc);
354  
355  	/* Turn off SPI mode */
356  	writel(0, &regs->spi);
357  
358  	/* Set up maximum timeout to wait for command response */
359  	writel(MMC_RES_TO_MAX_MASK, &regs->resto);
360  
361  	/* Mask all interrupts */
362  	writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
363  		&regs->i_mask);
364  	return 0;
365  }
366  
367  static const struct mmc_ops pxa_mmc_ops = {
368  	.send_cmd	= pxa_mmc_request,
369  	.set_ios	= pxa_mmc_set_ios,
370  	.init		= pxa_mmc_init,
371  };
372  
373  static struct mmc_config pxa_mmc_cfg = {
374  	.name		= "PXA MMC",
375  	.ops		= &pxa_mmc_ops,
376  	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
377  	.f_max		= PXAMMC_MAX_SPEED,
378  	.f_min		= PXAMMC_MIN_SPEED,
379  	.host_caps	= PXAMMC_HOST_CAPS,
380  	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
381  };
382  
383  int pxa_mmc_register(int card_index)
384  {
385  	struct mmc *mmc;
386  	struct pxa_mmc_priv *priv;
387  	uint32_t reg;
388  	int ret = -ENOMEM;
389  
390  	priv = malloc(sizeof(struct pxa_mmc_priv));
391  	if (!priv)
392  		goto err0;
393  
394  	memset(priv, 0, sizeof(*priv));
395  
396  	switch (card_index) {
397  	case 0:
398  		priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
399  		break;
400  	case 1:
401  		priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
402  		break;
403  	default:
404  		ret = -EINVAL;
405  		printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
406  			card_index);
407  		goto err1;
408  	}
409  
410  #ifndef	CONFIG_CPU_MONAHANS	/* PXA2xx */
411  	reg = readl(CKEN);
412  	reg |= CKEN12_MMC;
413  	writel(reg, CKEN);
414  #else				/* PXA3xx */
415  	reg = readl(CKENA);
416  	reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
417  	writel(reg, CKENA);
418  #endif
419  
420  	mmc = mmc_create(&pxa_mmc_cfg, priv);
421  	if (mmc == NULL)
422  		goto err1;
423  
424  	return 0;
425  
426  err1:
427  	free(priv);
428  err0:
429  	return ret;
430  }
431