[update] add ECC enable message

[update] ecc off by default

[fix] fix build error when ASPEED_ECC is off

[update] correct the ecc range

[add] add ECC setting

[update] revise the mapping of the VGA size

read VGA size configuration from strap register (SCU500)

Merge branch 'ryan_port' into aspeed-dev-v2019.04

[fix] do not check PHY status on FPGA

update copyright

Merge branch 'feature/dram_palladium' into aspeed-dev-v2019.04

[update] decrease the number of test to speed up boot
time

[update] add palladium ram support

[update] check ddr-phy init complete before CPU
starting access DRAM

[add] add config for PALLADIUM RAM model

[update] remove redundant debug message

add 10ms delay after PHY init.

[update] revise sdram training procedure

[fix] spl config define

[add] add aspeed palladium config for sdram driver

[new] workaround: add SPL_TINY for g6
secure boot verify

[fix] correct the bit-operation

[fix] fix the VGA and SDRAM capacity calculation

[update] refactor mc test

[update] refactor sdram mc test print format

[update] revise sdrammc_test

[update] verify test result and report error