xref: /openbmc/u-boot/arch/arm/dts/ast2600.dtsi (revision 62b04a6f33f489d51893e7fce2cfd1e3a756accf)
1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include <dt-bindings/gpio/aspeed-gpio.h>
4#include "skeleton.dtsi"
5
6/ {
7	model = "Aspeed BMC";
8	compatible = "aspeed,ast2600";
9	#address-cells = <1>;
10	#size-cells = <1>;
11	interrupt-parent = <&gic>;
12
13	aliases {
14		i2c0 = &i2c0;
15		i2c1 = &i2c1;
16		i2c2 = &i2c2;
17		i2c3 = &i2c3;
18		i2c4 = &i2c4;
19		i2c5 = &i2c5;
20		i2c6 = &i2c6;
21		i2c7 = &i2c7;
22		i2c8 = &i2c8;
23		i2c9 = &i2c9;
24		i2c10 = &i2c10;
25		i2c11 = &i2c11;
26		i2c12 = &i2c12;
27		i2c13 = &i2c13;
28		i2c14 = &i2c14;
29		i2c15 = &i2c15;
30		serial0 = &uart1;
31		serial1 = &uart2;
32		serial2 = &uart3;
33		serial3 = &uart4;
34		serial4 = &uart5;
35		serial5 = &uart6;
36		serial6 = &uart7;
37		serial7 = &uart8;
38		serial8 = &uart9;
39		serial9 = &uart10;
40		serial10 = &uart11;
41		serial11 = &uart12;
42		serial12 = &uart13;
43	};
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48		enable-method = "aspeed,ast2600-smp";
49
50		cpu@0 {
51			compatible = "arm,cortex-a7";
52			device_type = "cpu";
53			reg = <0>;
54			clock-frequency = <48000000>;
55		};
56
57		cpu@1 {
58			compatible = "arm,cortex-a7";
59			device_type = "cpu";
60			reg = <1>;
61			clock-frequency = <48000000>;
62		};
63
64	};
65
66	timer {
67		compatible = "arm,armv7-timer";
68		interrupt-parent = <&gic>;
69		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
70				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
73		clock-frequency = <25000000>;
74	};
75
76	memory@80000000 {
77		device_type = "memory";
78		reg = <0x80000000 0>;
79	};
80
81	reserved-memory {
82		#address-cells = <1>;
83		#size-cells = <1>;
84		ranges;
85
86		gfx_memory: framebuffer {
87			size = <0x01000000>;
88			alignment = <0x01000000>;
89			compatible = "shared-dma-pool";
90			reusable;
91		};
92
93		video_memory: video {
94			size = <0x04000000>;
95			alignment = <0x01000000>;
96			compatible = "shared-dma-pool";
97			no-map;
98		};
99	};
100
101	ahb {
102		compatible = "simple-bus";
103		#address-cells = <1>;
104		#size-cells = <1>;
105		device_type = "soc";
106		ranges;
107
108		gic: interrupt-controller@40461000 {
109				compatible = "arm,cortex-a7-gic";
110				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
111				#interrupt-cells = <3>;
112				interrupt-controller;
113				interrupt-parent = <&gic>;
114				reg = <0x40461000 0x1000>,
115					<0x40462000 0x1000>,
116					<0x40464000 0x2000>,
117					<0x40466000 0x2000>;
118		};
119
120		ahbc: ahbc@1e600000 {
121			compatible = "aspeed,aspeed-ahbc";
122			reg = < 0x1e600000 0x100>;
123		};
124
125		fmc: flash-controller@1e620000 {
126			reg = < 0x1e620000 0xc4
127				0x20000000 0x10000000 >;
128			#address-cells = <1>;
129			#size-cells = <0>;
130			compatible = "aspeed,ast2600-fmc";
131			status = "disabled";
132			interrupts = <19>;
133			clocks = <&scu ASPEED_CLK_AHB>;
134			flash@0 {
135				reg = < 0 >;
136				compatible = "jedec,spi-nor";
137				status = "disabled";
138			};
139			flash@1 {
140				reg = < 1 >;
141				compatible = "jedec,spi-nor";
142				status = "disabled";
143			};
144			flash@2 {
145				reg = < 2 >;
146				compatible = "jedec,spi-nor";
147				status = "disabled";
148			};
149		};
150
151		spi1: flash-controller@1e630000 {
152			reg = < 0x1e630000 0xc4
153				0x30000000 0x08000000 >;
154			#address-cells = <1>;
155			#size-cells = <0>;
156			compatible = "aspeed,ast2600-spi";
157			clocks = <&scu ASPEED_CLK_AHB>;
158			status = "disabled";
159			flash@0 {
160				reg = < 0 >;
161				compatible = "jedec,spi-nor";
162				status = "disabled";
163			};
164			flash@1 {
165				reg = < 1 >;
166				compatible = "jedec,spi-nor";
167				status = "disabled";
168			};
169		};
170
171		spi2: flash-controller@1e631000 {
172			reg = < 0x1e631000 0xc4
173				0x38000000 0x08000000 >;
174			#address-cells = <1>;
175			#size-cells = <0>;
176			compatible = "aspeed,ast2600-spi";
177			clocks = <&scu ASPEED_CLK_AHB>;
178			status = "disabled";
179			flash@0 {
180				reg = < 0 >;
181				compatible = "jedec,spi-nor";
182				status = "disabled";
183			};
184			flash@1 {
185				reg = < 1 >;
186				compatible = "jedec,spi-nor";
187				status = "disabled";
188			};
189		};
190
191		edac: sdram@1e6e0000 {
192			compatible = "aspeed,ast2600-sdram-edac";
193			reg = <0x1e6e0000 0x174>;
194			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
195		};
196
197		mdio: ethernet@1e650000 {
198			compatible = "aspeed,aspeed-mdio";
199			reg = <0x1e650000 0x40>;
200			resets = <&rst ASPEED_RESET_MII>;
201			status = "disabled";
202		};
203
204#ifdef CONFIG_FPGA_ASPEED
205		mac0: ftgmac@1e660000 {
206			compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
207			reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
208			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
209			clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
210			status = "disabled";
211		};
212#else
213		mac1: ftgmac@1e680000 {
214			compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
215			reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
216			#address-cells = <1>;
217			#size-cells = <0>;
218			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
219			clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
220#if 0
221			phy-handle = <&phy0>;
222#endif
223			status = "disabled";
224		};
225
226		mac2: ftgmac@1e670000 {
227			compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
228			reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
229			#address-cells = <1>;
230			#size-cells = <0>;
231			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
232			clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
233#if 0
234			phy-handle = <&phy0>;
235#endif
236			status = "disabled";
237		};
238
239		mac3: ftgmac@1e690000 {
240			compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
241			reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
242			#address-cells = <1>;
243			#size-cells = <0>;
244			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
245			clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
246#if 0
247			phy-handle = <&phy0>;
248#endif
249			status = "disabled";
250		};
251#endif
252
253		apb {
254			compatible = "simple-bus";
255			#address-cells = <1>;
256			#size-cells = <1>;
257			ranges;
258
259			syscon: syscon@1e6e2000 {
260				compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
261				reg = <0x1e6e2000 0x1000>;
262				#address-cells = <1>;
263				#size-cells = <1>;
264				#clock-cells = <1>;
265				#reset-cells = <1>;
266				ranges = <0 0x1e6e2000 0x1000>;
267
268				pinctrl: pinctrl {
269					compatible = "aspeed,g6-pinctrl";
270					aspeed,external-nodes = <&gfx &lhc>;
271
272				};
273
274				vga_scratch: scratch {
275					compatible = "aspeed,bmc-misc";
276				};
277
278				scu_ic0: interrupt-controller@0 {
279					#interrupt-cells = <1>;
280					compatible = "aspeed,ast2600-scu-ic";
281					reg = <0x560 0x10>;
282					interrupt-parent = <&gic>;
283					interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
284					interrupt-controller;
285				};
286
287				scu_ic1: interrupt-controller@1 {
288					#interrupt-cells = <1>;
289					compatible = "aspeed,ast2600-scu-ic";
290					reg = <0x570 0x10>;
291					interrupt-parent = <&gic>;
292					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
293					interrupt-controller;
294				};
295
296			};
297
298			smp-memram@0 {
299				compatible = "aspeed,ast2600-smpmem", "syscon";
300				reg = <0x1e6e2180 0x40>;
301			};
302
303			gfx: display@1e6e6000 {
304				compatible = "aspeed,ast2500-gfx", "syscon";
305				reg = <0x1e6e6000 0x1000>;
306				reg-io-width = <4>;
307			};
308
309			pcie_bridge: pcie_bridge@0x1e6ed000 {
310				compatible = "aspeed,ast2600-pcie";
311				reg = <0x1e6ed000 0x100>, <0x60000000 0x20000000>;
312			};
313
314			sdhci: sdhci@1e740000 {
315                #interrupt-cells = <1>;
316                compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
317                reg = <0x1e740000 0x1000>;
318                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
319                interrupt-controller;
320                clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>;
321                clock-names = "ctrlclk", "extclk";
322                #address-cells = <1>;
323                #size-cells = <1>;
324                ranges = <0x0 0x1e740000 0x1000>;
325
326                sdhci_slot0: sdhci_slot0@100 {
327                        compatible = "aspeed,sdhci-ast2600";
328                        reg = <0x100 0x100>;
329                        interrupts = <0>;
330                        interrupt-parent = <&sdhci>;
331                        sdhci,auto-cmd12;
332                        clocks = <&scu ASPEED_CLK_SDIO>;
333						status = "disabled";
334                };
335
336                sdhci_slot1: sdhci_slot1@200 {
337                        compatible = "aspeed,sdhci-ast2600";
338                        reg = <0x200 0x100>;
339                        interrupts = <1>;
340                        interrupt-parent = <&sdhci>;
341                        sdhci,auto-cmd12;
342                        clocks = <&scu ASPEED_CLK_SDIO>;
343						status = "disabled";
344				};
345			};
346
347			emmc: emmc@1e750000 {
348                #interrupt-cells = <1>;
349                compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
350                reg = <0x1e750000 0x1000>;
351                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
352                interrupt-controller;
353                clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
354                clock-names = "ctrlclk", "extclk";
355                #address-cells = <1>;
356                #size-cells = <1>;
357                ranges = <0x0 0x1e750000 0x1000>;
358
359                emmc_slot0: emmc_slot0@100 {
360                        compatible = "aspeed,emmc-ast2600";
361                        reg = <0x100 0x100>;
362                        interrupts = <0>;
363                        interrupt-parent = <&emmc>;
364                        clocks = <&scu ASPEED_CLK_EMMC>;
365						status = "disabled";
366				};
367			};
368
369			h2x: h2x@1e770000 {
370				compatible = "aspeed,ast2600-h2x";
371				reg = <0x1e770000 0x100>;
372				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
373				resets = <&rst ASPEED_RESET_H2X>;
374			};
375
376			gpio0: gpio@1e780000 {
377				compatible = "aspeed,ast2600-gpio";
378				reg = <0x1e780000 0x1000>;
379				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
380				#gpio-cells = <2>;
381				gpio-controller;
382				interrupt-controller;
383				gpio-ranges = <&pinctrl 0 0 220>;
384			};
385
386			gpio1: gpio@1e780800 {
387				compatible = "aspeed,ast2600-gpio";
388				reg = <0x1e780800 0x800>;
389				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
390				#gpio-cells = <2>;
391				gpio-controller;
392				interrupt-controller;
393				gpio-ranges = <&pinctrl 0 0 208>;
394			};
395
396			uart1: serial@1e783000 {
397				compatible = "ns16550a";
398				reg = <0x1e783000 0x20>;
399				reg-shift = <2>;
400				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
401				clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
402				clock-frequency = <1846154>;
403				no-loopback-test;
404				status = "disabled";
405			};
406
407			uart5: serial@1e784000 {
408				compatible = "ns16550a";
409				reg = <0x1e784000 0x1000>;
410				reg-shift = <2>;
411				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
412				clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
413				clock-frequency = <1846154>;
414				no-loopback-test;
415				status = "disabled";
416			};
417
418			wdt1: watchdog@1e785000 {
419				compatible = "aspeed,ast2600-wdt";
420				reg = <0x1e785000 0x40>;
421			};
422
423			wdt2: watchdog@1e785040 {
424				compatible = "aspeed,ast2600-wdt";
425				reg = <0x1e785040 0x40>;
426			};
427
428			wdt3: watchdog@1e785080 {
429				compatible = "aspeed,ast2600-wdt";
430				reg = <0x1e785080 0x40>;
431			};
432
433			wdt4: watchdog@1e7850C0 {
434				compatible = "aspeed,ast2600-wdt";
435				reg = <0x1e7850C0 0x40>;
436			};
437
438			lpc: lpc@1e789000 {
439				compatible = "aspeed,ast-lpc", "simple-mfd", "syscon";
440				reg = <0x1e789000 0x200>;
441
442				#address-cells = <1>;
443				#size-cells = <1>;
444				ranges = <0x0 0x1e789000 0x1000>;
445
446				lpc_bmc: lpc-bmc@0 {
447					compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
448					reg = <0x0 0x80>;
449					reg-io-width = <4>;
450					#address-cells = <1>;
451					#size-cells = <1>;
452					ranges = <0x0 0x0 0x80>;
453
454					kcs1: kcs1@0 {
455						compatible = "aspeed,ast2600-kcs-bmc";
456						reg = <0x0 0x80>;
457						interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
458						kcs_chan = <1>;
459						kcs_addr = <0xCA0>;
460						status = "disabled";
461					};
462
463					kcs2: kcs2@0 {
464						compatible = "aspeed,ast2600-kcs-bmc";
465						reg = <0x0 0x80>;
466						interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
467						kcs_chan = <2>;
468						kcs_addr = <0xCA8>;
469						status = "disabled";
470					};
471
472					kcs3: kcs3@0 {
473						compatible = "aspeed,ast2600-kcs-bmc";
474						reg = <0x0 0x80>;
475						interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
476						kcs_chan = <3>;
477						kcs_addr = <0xCA2>;
478					};
479
480					kcs4: kcs4@0 {
481						compatible = "aspeed,ast2600-kcs-bmc";
482						reg = <0x0 0x120>;
483						interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
484						kcs_chan = <4>;
485						kcs_addr = <0xCA4>;
486						status = "disabled";
487					};
488
489				};
490
491				lpc_host: lpc-host@80 {
492					compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
493					reg = <0x80 0x1e0>;
494					reg-io-width = <4>;
495
496					#address-cells = <1>;
497					#size-cells = <1>;
498					ranges = <0x0 0x80 0x1e0>;
499
500					lpc_ctrl: lpc-ctrl@0 {
501						compatible = "aspeed,ast2600-lpc-ctrl";
502						reg = <0x0 0x80>;
503						status = "disabled";
504					};
505
506					lpc_snoop: lpc-snoop@0 {
507						compatible = "aspeed,ast2600-lpc-snoop";
508						reg = <0x0 0x80>;
509						interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
510						snoop-ports = <0x80>;
511						status = "disabled";
512					};
513
514					lhc: lhc@20 {
515						compatible = "aspeed,ast2600-lhc";
516						reg = <0x20 0x24 0x48 0x8>;
517					};
518
519					lpc_reset: reset-controller@18 {
520						compatible = "aspeed,ast2600-lpc-reset";
521						reg = <0x18 0x4>;
522						#reset-cells = <1>;
523						status = "disabled";
524					};
525
526					ibt: ibt@c0 {
527						compatible = "aspeed,ast2600-ibt-bmc";
528						reg = <0xc0 0x18>;
529						interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
530						status = "disabled";
531					};
532
533					sio_regs: regs {
534						compatible = "aspeed,bmc-misc";
535					};
536
537					mbox: mbox@180 {
538						compatible = "aspeed,ast2600-mbox";
539						reg = <0x180 0x5c>;
540						interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
541						#mbox-cells = <1>;
542						status = "disabled";
543					};
544				};
545			};
546
547			uart2: serial@1e78d000 {
548				compatible = "ns16550a";
549				reg = <0x1e78d000 0x20>;
550				reg-shift = <2>;
551				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
552				clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
553				clock-frequency = <1846154>;
554				no-loopback-test;
555				status = "disabled";
556			};
557
558			uart3: serial@1e78e000 {
559				compatible = "ns16550a";
560				reg = <0x1e78e000 0x20>;
561				reg-shift = <2>;
562				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
563				clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
564				clock-frequency = <1846154>;
565				no-loopback-test;
566				status = "disabled";
567			};
568
569			uart4: serial@1e78f000 {
570				compatible = "ns16550a";
571				reg = <0x1e78f000 0x20>;
572				reg-shift = <2>;
573				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
574				clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
575				clock-frequency = <1846154>;
576				no-loopback-test;
577				status = "disabled";
578			};
579
580			i2c: bus@1e78a000 {
581				compatible = "simple-bus";
582				#address-cells = <1>;
583				#size-cells = <1>;
584				ranges = <0 0x1e78a000 0x1000>;
585			};
586
587			uart6: serial@1e790000 {
588				compatible = "ns16550a";
589				reg = <0x1e790000 0x20>;
590				reg-shift = <2>;
591				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
592				clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
593				clock-frequency = <1846154>;
594				no-loopback-test;
595				status = "disabled";
596			};
597
598			uart7: serial@1e790100 {
599				compatible = "ns16550a";
600				reg = <0x1e790100 0x20>;
601				reg-shift = <2>;
602				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
603				clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
604				clock-frequency = <1846154>;
605				no-loopback-test;
606				status = "disabled";
607			};
608
609			uart8: serial@1e790200 {
610				compatible = "ns16550a";
611				reg = <0x1e790200 0x20>;
612				reg-shift = <2>;
613				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
614				clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
615				clock-frequency = <1846154>;
616				no-loopback-test;
617				status = "disabled";
618			};
619
620			uart9: serial@1e790300 {
621				compatible = "ns16550a";
622				reg = <0x1e790300 0x20>;
623				reg-shift = <2>;
624				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
625				clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
626				clock-frequency = <1846154>;
627				no-loopback-test;
628				status = "disabled";
629			};
630
631			uart10: serial@1e790400 {
632				compatible = "ns16550a";
633				reg = <0x1e790400 0x20>;
634				reg-shift = <2>;
635				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
636				clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
637				clock-frequency = <1846154>;
638				no-loopback-test;
639				status = "disabled";
640			};
641
642			uart11: serial@1e790500 {
643				compatible = "ns16550a";
644				reg = <0x1e790400 0x20>;
645				reg-shift = <2>;
646				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
647				clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
648				clock-frequency = <1846154>;
649				no-loopback-test;
650				status = "disabled";
651			};
652
653			uart12: serial@1e790600 {
654				compatible = "ns16550a";
655				reg = <0x1e790600 0x20>;
656				reg-shift = <2>;
657				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
658				clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
659				clock-frequency = <1846154>;
660				no-loopback-test;
661				status = "disabled";
662			};
663
664			uart13: serial@1e790700 {
665				compatible = "ns16550a";
666				reg = <0x1e790700 0x20>;
667				reg-shift = <2>;
668				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
669				clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
670				clock-frequency = <1846154>;
671				no-loopback-test;
672				status = "disabled";
673			};
674
675
676
677		};
678
679	};
680
681};
682
683&i2c {
684	i2cglobal: i2cg@00 {
685		compatible = "aspeed,ast2600-i2c-global";
686		reg = <0x0 0x40>;
687		resets = <&rst ASPEED_RESET_I2C>;
688#if 0
689		new-mode;
690#endif
691	};
692
693	i2c0: i2c@80 {
694		#address-cells = <1>;
695		#size-cells = <0>;
696		#interrupt-cells = <1>;
697
698		reg = <0x80 0x80 0xC00 0x20>;
699		compatible = "aspeed,ast2600-i2c-bus";
700		bus-frequency = <100000>;
701		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
702		clocks = <&scu ASPEED_CLK_APB2>;
703		status = "disabled";
704	};
705
706	i2c1: i2c@100 {
707		#address-cells = <1>;
708		#size-cells = <0>;
709		#interrupt-cells = <1>;
710
711		reg = <0x100 0x80 0xC20 0x20>;
712		compatible = "aspeed,ast2600-i2c-bus";
713		bus-frequency = <100000>;
714		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
715		clocks = <&scu ASPEED_CLK_APB2>;
716		status = "disabled";
717	};
718
719	i2c2: i2c@180 {
720		#address-cells = <1>;
721		#size-cells = <0>;
722		#interrupt-cells = <1>;
723
724		reg = <0x180 0x80 0xC40 0x20>;
725		compatible = "aspeed,ast2600-i2c-bus";
726		bus-frequency = <100000>;
727		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
728		clocks = <&scu ASPEED_CLK_APB2>;
729	};
730
731	i2c3: i2c@200 {
732		#address-cells = <1>;
733		#size-cells = <0>;
734		#interrupt-cells = <1>;
735
736		reg = <0x200 0x40 0xC60 0x20>;
737		compatible = "aspeed,ast2600-i2c-bus";
738		bus-frequency = <100000>;
739		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
740		clocks = <&scu ASPEED_CLK_APB2>;
741	};
742
743	i2c4: i2c@280 {
744		#address-cells = <1>;
745		#size-cells = <0>;
746		#interrupt-cells = <1>;
747
748		reg = <0x280 0x80 0xC80 0x20>;
749		compatible = "aspeed,ast2600-i2c-bus";
750		bus-frequency = <100000>;
751		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
752		clocks = <&scu ASPEED_CLK_APB2>;
753	};
754
755	i2c5: i2c@300 {
756		#address-cells = <1>;
757		#size-cells = <0>;
758		#interrupt-cells = <1>;
759
760		reg = <0x300 0x40 0xCA0 0x20>;
761		compatible = "aspeed,ast2600-i2c-bus";
762		bus-frequency = <100000>;
763		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
764		clocks = <&scu ASPEED_CLK_APB2>;
765	};
766
767	i2c6: i2c@380 {
768		#address-cells = <1>;
769		#size-cells = <0>;
770		#interrupt-cells = <1>;
771
772		reg = <0x380 0x80 0xCC0 0x20>;
773		compatible = "aspeed,ast2600-i2c-bus";
774		bus-frequency = <100000>;
775		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
776		clocks = <&scu ASPEED_CLK_APB2>;
777	};
778
779	i2c7: i2c@400 {
780		#address-cells = <1>;
781		#size-cells = <0>;
782		#interrupt-cells = <1>;
783
784		reg = <0x400 0x80 0xCE0 0x20>;
785		compatible = "aspeed,ast2600-i2c-bus";
786		bus-frequency = <100000>;
787		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
788		clocks = <&scu ASPEED_CLK_APB2>;
789	};
790
791	i2c8: i2c@480 {
792		#address-cells = <1>;
793		#size-cells = <0>;
794		#interrupt-cells = <1>;
795
796		reg = <0x480 0x80 0xD00 0x20>;
797		compatible = "aspeed,ast2600-i2c-bus";
798		bus-frequency = <100000>;
799		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
800		clocks = <&scu ASPEED_CLK_APB2>;
801	};
802
803	i2c9: i2c@500 {
804		#address-cells = <1>;
805		#size-cells = <0>;
806		#interrupt-cells = <1>;
807
808		reg = <0x500 0x80 0xD20 0x20>;
809		compatible = "aspeed,ast2600-i2c-bus";
810		bus-frequency = <100000>;
811		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
812		clocks = <&scu ASPEED_CLK_APB2>;
813		status = "disabled";
814	};
815
816	i2c10: i2c@580 {
817		#address-cells = <1>;
818		#size-cells = <0>;
819		#interrupt-cells = <1>;
820
821		reg = <0x580 0x80 0xD40 0x20>;
822		compatible = "aspeed,ast2600-i2c-bus";
823		bus-frequency = <100000>;
824		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
825		clocks = <&scu ASPEED_CLK_APB2>;
826		status = "disabled";
827	};
828
829	i2c11: i2c@600 {
830		#address-cells = <1>;
831		#size-cells = <0>;
832		#interrupt-cells = <1>;
833
834		reg = <0x600 0x80 0xD60 0x20>;
835		compatible = "aspeed,ast2600-i2c-bus";
836		bus-frequency = <100000>;
837		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
838		clocks = <&scu ASPEED_CLK_APB2>;
839		status = "disabled";
840	};
841
842	i2c12: i2c@680 {
843		#address-cells = <1>;
844		#size-cells = <0>;
845		#interrupt-cells = <1>;
846
847		reg = <0x680 0x80 0xD80 0x20>;
848		compatible = "aspeed,ast2600-i2c-bus";
849		bus-frequency = <100000>;
850		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
851		clocks = <&scu ASPEED_CLK_APB2>;
852		status = "disabled";
853	};
854
855	i2c13: i2c@700 {
856		#address-cells = <1>;
857		#size-cells = <0>;
858		#interrupt-cells = <1>;
859
860		reg = <0x700 0x80 0xDA0 0x20>;
861		compatible = "aspeed,ast2600-i2c-bus";
862		bus-frequency = <100000>;
863		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
864		clocks = <&scu ASPEED_CLK_APB2>;
865		status = "disabled";
866	};
867
868	i2c14: i2c@780 {
869		#address-cells = <1>;
870		#size-cells = <0>;
871		#interrupt-cells = <1>;
872
873		reg = <0x780 0x80 0xDC0 0x20>;
874		compatible = "aspeed,ast2600-i2c-bus";
875		bus-frequency = <100000>;
876		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
877		clocks = <&scu ASPEED_CLK_APB2>;
878		status = "disabled";
879	};
880
881	i2c15: i2c@800 {
882		#address-cells = <1>;
883		#size-cells = <0>;
884		#interrupt-cells = <1>;
885
886		reg = <0x800 0x80 0xDE0 0x20>;
887		compatible = "aspeed,ast2600-i2c-bus";
888		bus-frequency = <100000>;
889		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
890		clocks = <&scu ASPEED_CLK_APB2>;
891		status = "disabled";
892	};
893
894};
895
896&pinctrl {
897	pinctrl_acpi_default: acpi_default {
898		function = "ACPI";
899		groups = "ACPI";
900	};
901
902	pinctrl_adc0_default: adc0_default {
903		function = "ADC0";
904		groups = "ADC0";
905	};
906
907	pinctrl_adc1_default: adc1_default {
908		function = "ADC1";
909		groups = "ADC1";
910	};
911
912	pinctrl_adc10_default: adc10_default {
913		function = "ADC10";
914		groups = "ADC10";
915	};
916
917	pinctrl_adc11_default: adc11_default {
918		function = "ADC11";
919		groups = "ADC11";
920	};
921
922	pinctrl_adc12_default: adc12_default {
923		function = "ADC12";
924		groups = "ADC12";
925	};
926
927	pinctrl_adc13_default: adc13_default {
928		function = "ADC13";
929		groups = "ADC13";
930	};
931
932	pinctrl_adc14_default: adc14_default {
933		function = "ADC14";
934		groups = "ADC14";
935	};
936
937	pinctrl_adc15_default: adc15_default {
938		function = "ADC15";
939		groups = "ADC15";
940	};
941
942	pinctrl_adc2_default: adc2_default {
943		function = "ADC2";
944		groups = "ADC2";
945	};
946
947	pinctrl_adc3_default: adc3_default {
948		function = "ADC3";
949		groups = "ADC3";
950	};
951
952	pinctrl_adc4_default: adc4_default {
953		function = "ADC4";
954		groups = "ADC4";
955	};
956
957	pinctrl_adc5_default: adc5_default {
958		function = "ADC5";
959		groups = "ADC5";
960	};
961
962	pinctrl_adc6_default: adc6_default {
963		function = "ADC6";
964		groups = "ADC6";
965	};
966
967	pinctrl_adc7_default: adc7_default {
968		function = "ADC7";
969		groups = "ADC7";
970	};
971
972	pinctrl_adc8_default: adc8_default {
973		function = "ADC8";
974		groups = "ADC8";
975	};
976
977	pinctrl_adc9_default: adc9_default {
978		function = "ADC9";
979		groups = "ADC9";
980	};
981
982	pinctrl_bmcint_default: bmcint_default {
983		function = "BMCINT";
984		groups = "BMCINT";
985	};
986
987	pinctrl_ddcclk_default: ddcclk_default {
988		function = "DDCCLK";
989		groups = "DDCCLK";
990	};
991
992	pinctrl_ddcdat_default: ddcdat_default {
993		function = "DDCDAT";
994		groups = "DDCDAT";
995	};
996
997	pinctrl_espi_default: espi_default {
998		function = "ESPI";
999		groups = "ESPI";
1000	};
1001
1002	pinctrl_fwspics1_default: fwspics1_default {
1003		function = "FWSPICS1";
1004		groups = "FWSPICS1";
1005	};
1006
1007	pinctrl_fwspics2_default: fwspics2_default {
1008		function = "FWSPICS2";
1009		groups = "FWSPICS2";
1010	};
1011
1012	pinctrl_gpid0_default: gpid0_default {
1013		function = "GPID0";
1014		groups = "GPID0";
1015	};
1016
1017	pinctrl_gpid2_default: gpid2_default {
1018		function = "GPID2";
1019		groups = "GPID2";
1020	};
1021
1022	pinctrl_gpid4_default: gpid4_default {
1023		function = "GPID4";
1024		groups = "GPID4";
1025	};
1026
1027	pinctrl_gpid6_default: gpid6_default {
1028		function = "GPID6";
1029		groups = "GPID6";
1030	};
1031
1032	pinctrl_gpie0_default: gpie0_default {
1033		function = "GPIE0";
1034		groups = "GPIE0";
1035	};
1036
1037	pinctrl_gpie2_default: gpie2_default {
1038		function = "GPIE2";
1039		groups = "GPIE2";
1040	};
1041
1042	pinctrl_gpie4_default: gpie4_default {
1043		function = "GPIE4";
1044		groups = "GPIE4";
1045	};
1046
1047	pinctrl_gpie6_default: gpie6_default {
1048		function = "GPIE6";
1049		groups = "GPIE6";
1050	};
1051
1052	pinctrl_i2c10_default: i2c10_default {
1053		function = "I2C10";
1054		groups = "I2C10";
1055	};
1056
1057	pinctrl_i2c11_default: i2c11_default {
1058		function = "I2C11";
1059		groups = "I2C11";
1060	};
1061
1062	pinctrl_i2c12_default: i2c12_default {
1063		function = "I2C12";
1064		groups = "I2C12";
1065	};
1066
1067	pinctrl_i2c13_default: i2c13_default {
1068		function = "I2C13";
1069		groups = "I2C13";
1070	};
1071
1072	pinctrl_i2c14_default: i2c14_default {
1073		function = "I2C14";
1074		groups = "I2C14";
1075	};
1076
1077	pinctrl_i2c3_default: i2c3_default {
1078		function = "I2C3";
1079		groups = "I2C3";
1080	};
1081
1082	pinctrl_i2c4_default: i2c4_default {
1083		function = "I2C4";
1084		groups = "I2C4";
1085	};
1086
1087	pinctrl_i2c5_default: i2c5_default {
1088		function = "I2C5";
1089		groups = "I2C5";
1090	};
1091
1092	pinctrl_i2c6_default: i2c6_default {
1093		function = "I2C6";
1094		groups = "I2C6";
1095	};
1096
1097	pinctrl_i2c7_default: i2c7_default {
1098		function = "I2C7";
1099		groups = "I2C7";
1100	};
1101
1102	pinctrl_i2c8_default: i2c8_default {
1103		function = "I2C8";
1104		groups = "I2C8";
1105	};
1106
1107	pinctrl_i2c9_default: i2c9_default {
1108		function = "I2C9";
1109		groups = "I2C9";
1110	};
1111
1112	pinctrl_lad0_default: lad0_default {
1113		function = "LAD0";
1114		groups = "LAD0";
1115	};
1116
1117	pinctrl_lad1_default: lad1_default {
1118		function = "LAD1";
1119		groups = "LAD1";
1120	};
1121
1122	pinctrl_lad2_default: lad2_default {
1123		function = "LAD2";
1124		groups = "LAD2";
1125	};
1126
1127	pinctrl_lad3_default: lad3_default {
1128		function = "LAD3";
1129		groups = "LAD3";
1130	};
1131
1132	pinctrl_lclk_default: lclk_default {
1133		function = "LCLK";
1134		groups = "LCLK";
1135	};
1136
1137	pinctrl_lframe_default: lframe_default {
1138		function = "LFRAME";
1139		groups = "LFRAME";
1140	};
1141
1142	pinctrl_lpchc_default: lpchc_default {
1143		function = "LPCHC";
1144		groups = "LPCHC";
1145	};
1146
1147	pinctrl_lpcpd_default: lpcpd_default {
1148		function = "LPCPD";
1149		groups = "LPCPD";
1150	};
1151
1152	pinctrl_lpcplus_default: lpcplus_default {
1153		function = "LPCPLUS";
1154		groups = "LPCPLUS";
1155	};
1156
1157	pinctrl_lpcpme_default: lpcpme_default {
1158		function = "LPCPME";
1159		groups = "LPCPME";
1160	};
1161
1162	pinctrl_lpcrst_default: lpcrst_default {
1163		function = "LPCRST";
1164		groups = "LPCRST";
1165	};
1166
1167	pinctrl_lpcsmi_default: lpcsmi_default {
1168		function = "LPCSMI";
1169		groups = "LPCSMI";
1170	};
1171
1172	pinctrl_lsirq_default: lsirq_default {
1173		function = "LSIRQ";
1174		groups = "LSIRQ";
1175	};
1176
1177	pinctrl_mac1link_default: mac1link_default {
1178		function = "MAC1LINK";
1179		groups = "MAC1LINK";
1180	};
1181
1182	pinctrl_mac2link_default: mac2link_default {
1183		function = "MAC2LINK";
1184		groups = "MAC2LINK";
1185	};
1186
1187	pinctrl_mac3link_default: mac3link_default {
1188		function = "MAC3LINK";
1189		groups = "MAC3LINK";
1190	};
1191
1192	pinctrl_mac4link_default: mac4link_default {
1193		function = "MAC4LINK";
1194		groups = "MAC4LINK";
1195	};
1196
1197	pinctrl_mdio1_default: mdio1_default {
1198		function = "MDIO1";
1199		groups = "MDIO1";
1200	};
1201
1202	pinctrl_mdio2_default: mdio2_default {
1203		function = "MDIO2";
1204		groups = "MDIO2";
1205	};
1206
1207	pinctrl_mdio3_default: mdio3_default {
1208		function = "MDIO3";
1209		groups = "MDIO3";
1210	};
1211
1212	pinctrl_mdio4_default: mdio4_default {
1213		function = "MDIO4";
1214		groups = "MDIO4";
1215	};
1216
1217	pinctrl_ncts1_default: ncts1_default {
1218		function = "NCTS1";
1219		groups = "NCTS1";
1220	};
1221
1222	pinctrl_ncts2_default: ncts2_default {
1223		function = "NCTS2";
1224		groups = "NCTS2";
1225	};
1226
1227	pinctrl_ncts3_default: ncts3_default {
1228		function = "NCTS3";
1229		groups = "NCTS3";
1230	};
1231
1232	pinctrl_ncts4_default: ncts4_default {
1233		function = "NCTS4";
1234		groups = "NCTS4";
1235	};
1236
1237	pinctrl_ndcd1_default: ndcd1_default {
1238		function = "NDCD1";
1239		groups = "NDCD1";
1240	};
1241
1242	pinctrl_ndcd2_default: ndcd2_default {
1243		function = "NDCD2";
1244		groups = "NDCD2";
1245	};
1246
1247	pinctrl_ndcd3_default: ndcd3_default {
1248		function = "NDCD3";
1249		groups = "NDCD3";
1250	};
1251
1252	pinctrl_ndcd4_default: ndcd4_default {
1253		function = "NDCD4";
1254		groups = "NDCD4";
1255	};
1256
1257	pinctrl_ndsr1_default: ndsr1_default {
1258		function = "NDSR1";
1259		groups = "NDSR1";
1260	};
1261
1262	pinctrl_ndsr2_default: ndsr2_default {
1263		function = "NDSR2";
1264		groups = "NDSR2";
1265	};
1266
1267	pinctrl_ndsr3_default: ndsr3_default {
1268		function = "NDSR3";
1269		groups = "NDSR3";
1270	};
1271
1272	pinctrl_ndsr4_default: ndsr4_default {
1273		function = "NDSR4";
1274		groups = "NDSR4";
1275	};
1276
1277	pinctrl_ndtr1_default: ndtr1_default {
1278		function = "NDTR1";
1279		groups = "NDTR1";
1280	};
1281
1282	pinctrl_ndtr2_default: ndtr2_default {
1283		function = "NDTR2";
1284		groups = "NDTR2";
1285	};
1286
1287	pinctrl_ndtr3_default: ndtr3_default {
1288		function = "NDTR3";
1289		groups = "NDTR3";
1290	};
1291
1292	pinctrl_ndtr4_default: ndtr4_default {
1293		function = "NDTR4";
1294		groups = "NDTR4";
1295	};
1296
1297	pinctrl_nri1_default: nri1_default {
1298		function = "NRI1";
1299		groups = "NRI1";
1300	};
1301
1302	pinctrl_nri2_default: nri2_default {
1303		function = "NRI2";
1304		groups = "NRI2";
1305	};
1306
1307	pinctrl_nri3_default: nri3_default {
1308		function = "NRI3";
1309		groups = "NRI3";
1310	};
1311
1312	pinctrl_nri4_default: nri4_default {
1313		function = "NRI4";
1314		groups = "NRI4";
1315	};
1316
1317	pinctrl_nrts1_default: nrts1_default {
1318		function = "NRTS1";
1319		groups = "NRTS1";
1320	};
1321
1322	pinctrl_nrts2_default: nrts2_default {
1323		function = "NRTS2";
1324		groups = "NRTS2";
1325	};
1326
1327	pinctrl_nrts3_default: nrts3_default {
1328		function = "NRTS3";
1329		groups = "NRTS3";
1330	};
1331
1332	pinctrl_nrts4_default: nrts4_default {
1333		function = "NRTS4";
1334		groups = "NRTS4";
1335	};
1336
1337	pinctrl_oscclk_default: oscclk_default {
1338		function = "OSCCLK";
1339		groups = "OSCCLK";
1340	};
1341
1342	pinctrl_pewake_default: pewake_default {
1343		function = "PEWAKE";
1344		groups = "PEWAKE";
1345	};
1346
1347	pinctrl_pnor_default: pnor_default {
1348		function = "PNOR";
1349		groups = "PNOR";
1350	};
1351
1352	pinctrl_pwm0_default: pwm0_default {
1353		function = "PWM0";
1354		groups = "PWM0";
1355	};
1356
1357	pinctrl_pwm1_default: pwm1_default {
1358		function = "PWM1";
1359		groups = "PWM1";
1360	};
1361
1362	pinctrl_pwm2_default: pwm2_default {
1363		function = "PWM2";
1364		groups = "PWM2";
1365	};
1366
1367	pinctrl_pwm3_default: pwm3_default {
1368		function = "PWM3";
1369		groups = "PWM3";
1370	};
1371
1372	pinctrl_pwm4_default: pwm4_default {
1373		function = "PWM4";
1374		groups = "PWM4";
1375	};
1376
1377	pinctrl_pwm5_default: pwm5_default {
1378		function = "PWM5";
1379		groups = "PWM5";
1380	};
1381
1382	pinctrl_pwm6_default: pwm6_default {
1383		function = "PWM6";
1384		groups = "PWM6";
1385	};
1386
1387	pinctrl_pwm7_default: pwm7_default {
1388		function = "PWM7";
1389		groups = "PWM7";
1390	};
1391
1392	pinctrl_rgmii1_default: rgmii1_default {
1393		function = "RGMII1";
1394		groups = "RGMII1";
1395	};
1396
1397	pinctrl_rgmii2_default: rgmii2_default {
1398		function = "RGMII2";
1399		groups = "RGMII2";
1400	};
1401
1402	pinctrl_rmii1_default: rmii1_default {
1403		function = "RMII1";
1404		groups = "RMII1";
1405	};
1406
1407	pinctrl_rmii2_default: rmii2_default {
1408		function = "RMII2";
1409		groups = "RMII2";
1410	};
1411
1412	pinctrl_rxd1_default: rxd1_default {
1413		function = "RXD1";
1414		groups = "RXD1";
1415	};
1416
1417	pinctrl_rxd2_default: rxd2_default {
1418		function = "RXD2";
1419		groups = "RXD2";
1420	};
1421
1422	pinctrl_rxd3_default: rxd3_default {
1423		function = "RXD3";
1424		groups = "RXD3";
1425	};
1426
1427	pinctrl_rxd4_default: rxd4_default {
1428		function = "RXD4";
1429		groups = "RXD4";
1430	};
1431
1432	pinctrl_salt1_default: salt1_default {
1433		function = "SALT1";
1434		groups = "SALT1";
1435	};
1436
1437	pinctrl_salt10_default: salt10_default {
1438		function = "SALT10";
1439		groups = "SALT10";
1440	};
1441
1442	pinctrl_salt11_default: salt11_default {
1443		function = "SALT11";
1444		groups = "SALT11";
1445	};
1446
1447	pinctrl_salt12_default: salt12_default {
1448		function = "SALT12";
1449		groups = "SALT12";
1450	};
1451
1452	pinctrl_salt13_default: salt13_default {
1453		function = "SALT13";
1454		groups = "SALT13";
1455	};
1456
1457	pinctrl_salt14_default: salt14_default {
1458		function = "SALT14";
1459		groups = "SALT14";
1460	};
1461
1462	pinctrl_salt2_default: salt2_default {
1463		function = "SALT2";
1464		groups = "SALT2";
1465	};
1466
1467	pinctrl_salt3_default: salt3_default {
1468		function = "SALT3";
1469		groups = "SALT3";
1470	};
1471
1472	pinctrl_salt4_default: salt4_default {
1473		function = "SALT4";
1474		groups = "SALT4";
1475	};
1476
1477	pinctrl_salt5_default: salt5_default {
1478		function = "SALT5";
1479		groups = "SALT5";
1480	};
1481
1482	pinctrl_salt6_default: salt6_default {
1483		function = "SALT6";
1484		groups = "SALT6";
1485	};
1486
1487	pinctrl_salt7_default: salt7_default {
1488		function = "SALT7";
1489		groups = "SALT7";
1490	};
1491
1492	pinctrl_salt8_default: salt8_default {
1493		function = "SALT8";
1494		groups = "SALT8";
1495	};
1496
1497	pinctrl_salt9_default: salt9_default {
1498		function = "SALT9";
1499		groups = "SALT9";
1500	};
1501
1502	pinctrl_scl1_default: scl1_default {
1503		function = "SCL1";
1504		groups = "SCL1";
1505	};
1506
1507	pinctrl_scl2_default: scl2_default {
1508		function = "SCL2";
1509		groups = "SCL2";
1510	};
1511
1512	pinctrl_sd1_default: sd1_default {
1513		function = "SD1";
1514		groups = "SD1";
1515	};
1516
1517	pinctrl_sd2_default: sd2_default {
1518		function = "SD2";
1519		groups = "SD2";
1520	};
1521
1522	pinctrl_emmc_default: emmc_default {
1523                function = "EMMC";
1524                groups = "EMMC";
1525        };
1526
1527	pinctrl_sda1_default: sda1_default {
1528		function = "SDA1";
1529		groups = "SDA1";
1530	};
1531
1532	pinctrl_sda2_default: sda2_default {
1533		function = "SDA2";
1534		groups = "SDA2";
1535	};
1536
1537	pinctrl_sgps1_default: sgps1_default {
1538		function = "SGPS1";
1539		groups = "SGPS1";
1540	};
1541
1542	pinctrl_sgps2_default: sgps2_default {
1543		function = "SGPS2";
1544		groups = "SGPS2";
1545	};
1546
1547	pinctrl_sioonctrl_default: sioonctrl_default {
1548		function = "SIOONCTRL";
1549		groups = "SIOONCTRL";
1550	};
1551
1552	pinctrl_siopbi_default: siopbi_default {
1553		function = "SIOPBI";
1554		groups = "SIOPBI";
1555	};
1556
1557	pinctrl_siopbo_default: siopbo_default {
1558		function = "SIOPBO";
1559		groups = "SIOPBO";
1560	};
1561
1562	pinctrl_siopwreq_default: siopwreq_default {
1563		function = "SIOPWREQ";
1564		groups = "SIOPWREQ";
1565	};
1566
1567	pinctrl_siopwrgd_default: siopwrgd_default {
1568		function = "SIOPWRGD";
1569		groups = "SIOPWRGD";
1570	};
1571
1572	pinctrl_sios3_default: sios3_default {
1573		function = "SIOS3";
1574		groups = "SIOS3";
1575	};
1576
1577	pinctrl_sios5_default: sios5_default {
1578		function = "SIOS5";
1579		groups = "SIOS5";
1580	};
1581
1582	pinctrl_siosci_default: siosci_default {
1583		function = "SIOSCI";
1584		groups = "SIOSCI";
1585	};
1586
1587	pinctrl_spi1_default: spi1_default {
1588		function = "SPI1";
1589		groups = "SPI1";
1590	};
1591
1592	pinctrl_spi1cs1_default: spi1cs1_default {
1593		function = "SPI1CS1";
1594		groups = "SPI1CS1";
1595	};
1596
1597	pinctrl_spi1debug_default: spi1debug_default {
1598		function = "SPI1DEBUG";
1599		groups = "SPI1DEBUG";
1600	};
1601
1602	pinctrl_spi1passthru_default: spi1passthru_default {
1603		function = "SPI1PASSTHRU";
1604		groups = "SPI1PASSTHRU";
1605	};
1606
1607	pinctrl_spi2ck_default: spi2ck_default {
1608		function = "SPI2CK";
1609		groups = "SPI2CK";
1610	};
1611
1612	pinctrl_spi2cs0_default: spi2cs0_default {
1613		function = "SPI2CS0";
1614		groups = "SPI2CS0";
1615	};
1616
1617	pinctrl_spi2cs1_default: spi2cs1_default {
1618		function = "SPI2CS1";
1619		groups = "SPI2CS1";
1620	};
1621
1622	pinctrl_spi2miso_default: spi2miso_default {
1623		function = "SPI2MISO";
1624		groups = "SPI2MISO";
1625	};
1626
1627	pinctrl_spi2mosi_default: spi2mosi_default {
1628		function = "SPI2MOSI";
1629		groups = "SPI2MOSI";
1630	};
1631
1632	pinctrl_timer3_default: timer3_default {
1633		function = "TIMER3";
1634		groups = "TIMER3";
1635	};
1636
1637	pinctrl_timer4_default: timer4_default {
1638		function = "TIMER4";
1639		groups = "TIMER4";
1640	};
1641
1642	pinctrl_timer5_default: timer5_default {
1643		function = "TIMER5";
1644		groups = "TIMER5";
1645	};
1646
1647	pinctrl_timer6_default: timer6_default {
1648		function = "TIMER6";
1649		groups = "TIMER6";
1650	};
1651
1652	pinctrl_timer7_default: timer7_default {
1653		function = "TIMER7";
1654		groups = "TIMER7";
1655	};
1656
1657	pinctrl_timer8_default: timer8_default {
1658		function = "TIMER8";
1659		groups = "TIMER8";
1660	};
1661
1662	pinctrl_txd1_default: txd1_default {
1663		function = "TXD1";
1664		groups = "TXD1";
1665	};
1666
1667	pinctrl_txd2_default: txd2_default {
1668		function = "TXD2";
1669		groups = "TXD2";
1670	};
1671
1672	pinctrl_txd3_default: txd3_default {
1673		function = "TXD3";
1674		groups = "TXD3";
1675	};
1676
1677	pinctrl_txd4_default: txd4_default {
1678		function = "TXD4";
1679		groups = "TXD4";
1680	};
1681
1682	pinctrl_uart6_default: uart6_default {
1683		function = "UART6";
1684		groups = "UART6";
1685	};
1686
1687	pinctrl_usbcki_default: usbcki_default {
1688		function = "USBCKI";
1689		groups = "USBCKI";
1690	};
1691
1692	pinctrl_usb2ah_default: usb2ah_default {
1693		function = "USB2AH";
1694		groups = "USB2AH";
1695	};
1696
1697	pinctrl_usb11bhid_default: usb11bhid_default {
1698		function = "USB11BHID";
1699		groups = "USB11BHID";
1700	};
1701
1702	pinctrl_usb2bh_default: usb2bh_default {
1703		function = "USB2BH";
1704		groups = "USB2BH";
1705	};
1706
1707	pinctrl_vgabiosrom_default: vgabiosrom_default {
1708		function = "VGABIOSROM";
1709		groups = "VGABIOSROM";
1710	};
1711
1712	pinctrl_vgahs_default: vgahs_default {
1713		function = "VGAHS";
1714		groups = "VGAHS";
1715	};
1716
1717	pinctrl_vgavs_default: vgavs_default {
1718		function = "VGAVS";
1719		groups = "VGAVS";
1720	};
1721
1722	pinctrl_vpi24_default: vpi24_default {
1723		function = "VPI24";
1724		groups = "VPI24";
1725	};
1726
1727	pinctrl_vpo_default: vpo_default {
1728		function = "VPO";
1729		groups = "VPO";
1730	};
1731
1732	pinctrl_wdtrst1_default: wdtrst1_default {
1733		function = "WDTRST1";
1734		groups = "WDTRST1";
1735	};
1736
1737	pinctrl_wdtrst2_default: wdtrst2_default {
1738		function = "WDTRST2";
1739		groups = "WDTRST2";
1740	};
1741};
1742