xref: /openbmc/u-boot/drivers/ram/aspeed/sdram_ast2600.c (revision eb21c4a78e52accda44b1d4db21c55aaf87f5ab1)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012-2020  ASPEED Technology Inc.
4  *
5  * Copyright 2016 Google, Inc
6  */
7 
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <reset.h>
15 #include <asm/io.h>
16 #include <asm/arch/scu_ast2600.h>
17 #include <asm/arch/sdram_ast2600.h>
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <dt-bindings/clock/ast2600-clock.h>
21 #include "sdram_phy_ast2600.h"
22 
23 /* in order to speed up DRAM init time, write pre-defined values to registers
24  * directly */
25 #define AST2600_SDRAMMC_MANUAL_CLK
26 
27 /* register offset */
28 #define AST_SCU_FPGA_STATUS	0x004
29 #define AST_SCU_HANDSHAKE	0x100
30 #define AST_SCU_MPLL		0x220
31 #define AST_SCU_MPLL_EXT	0x224
32 #define AST_SCU_FPGA_PLL	0x400
33 #define AST_SCU_HW_STRAP	0x500
34 
35 
36 /* bit-field of AST_SCU_HW_STRAP */
37 #define SCU_HWSTRAP_VGAMEM_SHIFT	2
38 #define SCU_HWSTRAP_VGAMEM_MASK		(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
39 #define SCU_HWSTRAP_DDR3		(1 << 25)
40 
41 
42 /* bit-field of AST_SCU_HANDSHAKE */
43 #define SCU_SDRAM_INIT_READY_MASK	BIT(6)
44 #define SCU_SDRAM_INIT_BY_SOC_MASK	BIT(7)
45 
46 /* bit-field of AST_SCU_MPLL */
47 #define SCU_MPLL_RESET			BIT(25)
48 #define SCU_MPLL_BYPASS			BIT(24)
49 #define SCU_MPLL_TURN_OFF		BIT(23)
50 #define SCU_MPLL_FREQ_MASK		GENMASK(22, 0)
51 
52 #define SCU_MPLL_FREQ_400M		0x0008405F
53 #define SCU_MPLL_EXT_400M		0x00000031
54 //#define SCU_MPLL_FREQ_400M		0x0038007F
55 //#define SCU_MPLL_EXT_400M		0x0000003F
56 #define SCU_MPLL_FREQ_200M		0x0078007F
57 #define SCU_MPLL_EXT_200M		0x0000003F
58 
59 /* MPLL configuration */
60 #if defined(CONFIG_ASPEED_DDR4_800)
61 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_200M
62 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_200M
63 #elif defined(CONFIG_ASPEED_DDR4_1600)
64 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_400M
65 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_400M
66 #else
67 #error "undefined DDR4 target rate\n"
68 #endif
69 
70 /* AC timing and SDRAM mode registers */
71 #ifdef CONFIG_FPGA_ASPEED
72 /* mode register settings for FPGA are fixed */
73 #define DDR4_MR01_MODE		0x03010100
74 #define DDR4_MR23_MODE		0x00000000
75 #define DDR4_MR45_MODE		0x04C00000
76 #define DDR4_MR6_MODE		0x00000050
77 #define DDR4_TRFC_FPGA		0x17263434
78 
79 /* FPGA need for an additional initialization procedure: search read window */
80 #define SEARCH_RDWIN_ANCHOR_0   (CONFIG_SYS_SDRAM_BASE + 0x0000)
81 #define SEARCH_RDWIN_ANCHOR_1   (CONFIG_SYS_SDRAM_BASE + 0x0004)
82 #define SEARCH_RDWIN_PTRN_0     0x12345678
83 #define SEARCH_RDWIN_PTRN_1     0xaabbccdd
84 #define SEARCH_RDWIN_PTRN_SUM   0xbcf02355
85 #else
86 /* mode register setting for real chip are derived from the model GDDR4-1600 */
87 #define DDR4_MR01_MODE		0x03010510
88 #define DDR4_MR23_MODE		0x00000000
89 #define DDR4_MR45_MODE		0x04000000
90 #define DDR4_MR6_MODE           0x00000400
91 #define DDR4_TRFC_1600		0x467299f1
92 #define DDR4_TRFC_800		0x23394c78
93 #endif  /* end of "#ifdef CONFIG_FPGA_ASPEED" */
94 
95 #if defined(CONFIG_FPGA_ASPEED)
96 #define DDR4_TRFC			DDR4_TRFC_FPGA
97 #else
98 /* real chip setting */
99 #if defined(CONFIG_ASPEED_DDR4_1600)
100 #define DDR4_TRFC			DDR4_TRFC_1600
101 #define DDR4_PHY_TRAIN_TRFC		0xc30
102 #elif defined(CONFIG_ASPEED_DDR4_800)
103 #define DDR4_TRFC			DDR4_TRFC_800
104 #define DDR4_PHY_TRAIN_TRFC		0x618
105 #else
106 #error "undefined tRFC setting"
107 #endif	/* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
108 #endif	/* end of "#if defined(CONFIG_FPGA_ASPEED)" */
109 
110 /* supported SDRAM size */
111 #define SDRAM_SIZE_1KB		(1024U)
112 #define SDRAM_SIZE_1MB		(SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
113 #define SDRAM_MIN_SIZE		(256 * SDRAM_SIZE_1MB)
114 #define SDRAM_MAX_SIZE		(2048 * SDRAM_SIZE_1MB)
115 
116 
117 DECLARE_GLOBAL_DATA_PTR;
118 
119 /*
120  * Bandwidth configuration parameters for different SDRAM requests.
121  * These are hardcoded settings taken from Aspeed SDK.
122  */
123 #ifdef CONFIG_FPGA_ASPEED
124 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200,
125                                       0x00000140};
126 
127 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888,
128                                             0x88888888};
129 #else
130 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304,
131                                       0x00001240};
132 
133 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444,
134                                             0x44444444};
135 #endif
136 
137 struct dram_info {
138 	struct ram_info info;
139 	struct clk ddr_clk;
140 	struct ast2600_sdrammc_regs *regs;
141 	void __iomem *scu;
142 	struct ast2600_ddr_phy *phy;
143 	void __iomem *phy_setting;
144 	void __iomem *phy_status;
145 	ulong clock_rate;
146 };
147 
148 static void ast2600_sdramphy_kick_training(struct dram_info *info)
149 {
150 #ifndef CONFIG_FPGA_ASPEED
151         struct ast2600_sdrammc_regs *regs = info->regs;
152         u32 data;
153 
154 	writel(0, &regs->phy_ctrl[0]);
155 	udelay(5000);
156         writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
157 	udelay(1000);
158         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
159 	udelay(1000);
160         /* wait for (PLL_LOCKED == 1) and (INIT == 0) */
161 	debug("%s: wait for PHY PLL lock\n", __func__);
162 	while (1) {
163 		data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_PLL_LOCKED;
164 		if (data) {
165 			break;
166 		}
167 	}
168 
169 	debug("%s: wait for PHY init done\n", __func__);
170 	while (1) {
171 		data = readl(&regs->phy_ctrl[0]) | SDRAM_PHYCTRL0_INIT;
172 		if (~data) {
173 			break;
174 		}
175 	}
176 
177 #ifdef CONFIG_ASPEED_DDR4_800
178 	do {
179 		data = readl(0x1e6e0400);
180 	} while((data & 0x7) != 0x7);
181 #endif
182 #endif
183 }
184 
185 /**
186  * @brief	load DDR-PHY configurations table to the PHY registers
187  * @param[in]	p_tbl - pointer to the configuration table
188  * @param[in]	info - pointer to the DRAM info struct
189  *
190  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
191  * system: one is in the SDRAM MC (memory controller) which is used in run
192  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
193  * training.  To make these two configurations align, we overwrite the DDR-PHY
194  * setting by the MC setting before DDR-PHY training.
195 */
196 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
197 {
198 #ifndef CONFIG_FPGA_ASPEED
199 	u32 reg_base = (u32)info->phy_setting;
200 	u32 addr = p_tbl[0];
201         u32 data;
202         int i = 1;
203 
204         debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base,
205                addr);
206 
207         /* load PHY configuration table into PHY-setting registers */
208         while (1) {
209                 if (addr < reg_base) {
210                         debug("invalid DDR-PHY addr: 0x%08x\n", addr);
211                         break;
212                 }
213                 data = p_tbl[i++];
214 
215                 if (DDR_PHY_TBL_END == data) {
216                         break;
217                 } else if (DDR_PHY_TBL_CHG_ADDR == data) {
218                         addr = p_tbl[i++];
219                 } else {
220                         writel(data, addr);
221                         addr += 4;
222                 }
223         }
224 
225 	data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
226 	data |= DDR4_PHY_TRAIN_TRFC;
227 	writel(data, info->phy_setting + 0x84);
228 
229 #ifdef CONFIG_ASPEED_DDR4_800
230 
231 	debug("Overwrite DDR-PHY MRS by MCR config\n");
232 	/* MR0 and MR1 */
233 	data = readl(&info->regs->mr01_mode_setting);
234 	data =
235 	    ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16);
236 	writel(data, reg_base + 0x58);
237 	debug("[%08x] 0x%08x\n", reg_base + 0x58, data);
238 
239 	/* MR2 and MR3 */
240 	data = readl(&info->regs->mr23_mode_setting);
241 	writel(data, reg_base + 0x54);
242 	debug("[%08x] 0x%08x\n", reg_base + 0x54, data);
243 
244 	/* MR4 and MR5 */
245 	data = readl(&info->regs->mr45_mode_setting);
246 	writel(data, reg_base + 0x5c);
247 	debug("[%08x] 0x%08x\n", reg_base + 0x5c, data);
248 
249 	/* MR6 */
250 	data = readl(&info->regs->mr6_mode_setting);
251 	writel(data, reg_base + 0x60);
252 	debug("[%08x] 0x%08x\n", reg_base + 0x60, data);
253 #endif
254 #endif
255 }
256 
257 static void ast2600_sdramphy_show_status(struct dram_info *info)
258 {
259 #ifndef CONFIG_FPGA_ASPEED
260         u32 value, tmp;
261         u32 reg_base = (u32)info->phy_status;
262 
263 	printf("\n");
264 	/* training status */
265         value = readl(reg_base + 0x00);
266 	printf("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
267         if (value & BIT(3)) {
268                 debug("\tinitial PVT calibration fail\n");
269         }
270         if (value & BIT(5)) {
271                 debug("\truntime calibration fail\n");
272         }
273 
274 	/* PU & PD */
275 	value = readl(reg_base + 0x30);
276 	printf("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
277         printf("  PU = 0x%02x\n", value & 0xff);
278         printf("  PD = 0x%02x\n", (value >> 16) & 0xff);
279 
280 	/* read eye window */
281         value = readl(reg_base + 0x68);
282 	printf("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
283 	printf("  rising edge of read data eye training pass window\n");
284 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
285 	printf("    B0:%d%%\n", tmp);
286 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
287         printf("    B1:%d%%\n", tmp);
288 
289 	value = readl(reg_base + 0xC8);
290 	printf("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
291 	printf("  falling edge of read data eye training pass window\n");
292 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
293 	printf("    B0:%d%%\n", tmp);
294 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
295         printf("    B1:%d%%\n", tmp);
296 
297         /* write eye window */
298         value = readl(reg_base + 0x7c);
299 	printf("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
300 	printf("  rising edge of write data eye training pass window\n");
301 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
302 	printf("    B0:%d%%\n", tmp);
303 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
304         printf("    B1:%d%%\n", tmp);
305 
306 	/* read Vref training result */
307         value = readl(reg_base + 0x88);
308 	printf("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
309         printf("  read Vref training result\n");
310 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
311 	printf("    B0:%d%%\n", tmp);
312 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
313         printf("    B1:%d%%\n", tmp);
314 
315         /* write Vref training result */
316         value = readl(reg_base + 0x90);
317 	printf("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
318 	tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127;
319         printf("  write Vref training result = %d%%\n", tmp);
320 
321         /* gate train */
322 	value = readl(reg_base + 0x50);
323 	printf("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
324 	printf("  gate training pass window\n");
325 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
326 	printf("    module 0: %d.%03d\n", (value >> 8) & 0xff, tmp);
327         tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255;
328 	printf("    module 1: %d.%03d\n", (value >> 24) & 0xff, tmp);
329 #endif
330 }
331 
332 #define MC_TEST_PATTERN_N 8
333 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
334     0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
335     0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253};
336 
337 #define DRAM_MapAdr	81000000
338 #define TIMEOUT_DRAM	5000000
339 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
340 {
341 	unsigned int data;
342 	unsigned int timeout = 0;
343 	struct ast2600_sdrammc_regs *regs = info->regs;
344 
345 	writel(0, &regs->ecc_test_ctrl);
346 	if (mode == 0) {
347 		writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl);
348 	} else {
349 		writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl);
350 	}
351 
352 	do {
353 		data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12);
354 
355 		if (data & BIT(13))
356 			return (0);
357 
358 		if (++timeout > TIMEOUT_DRAM) {
359 			printf("Timeout!!\n");
360 			writel(0, &regs->ecc_test_ctrl);
361 
362 			return (0);
363 		}
364 	} while (!data);
365 
366 	writel(0, &regs->ecc_test_ctrl);
367 
368 	return (1);
369 }
370 
371 int ast2600_sdrammc_cbr_test(struct dram_info *info)
372 {
373 	struct ast2600_sdrammc_regs *regs = info->regs;
374 	u32 i;
375 
376 	writel((DRAM_MapAdr | 0x7fffff), &regs->test_addr);
377 
378 	/* single */
379 	for (i=0; i<8; i++) {
380   		if(!ast2600_sdrammc_dg_test(info, i, 0))   return(0);
381 	}
382 
383 	/* burst */
384 	for (i=0; i<8; i++) {
385   		if(!ast2600_sdrammc_dg_test(info, i, i))   return(0);
386 	}
387 
388 	return(1);
389 }
390 
391 static int ast2600_sdrammc_test(struct dram_info *info)
392 {
393 	struct ast2600_sdrammc_regs *regs = info->regs;
394 
395 	u32 pass_cnt = 0;
396 	u32 fail_cnt = 0;
397 	u32 target_cnt = 2;
398 	u32 test_cnt = 0;
399 	u32 pattern;
400 	u32 i = 0;
401 	bool finish = false;
402 
403 	while (finish == false) {
404 		pattern = as2600_sdrammc_test_pattern[i++];
405 		i = i % MC_TEST_PATTERN_N;
406 		printf("Pattern = %08X : ",pattern);
407 		writel(pattern, regs->test_init_val);
408 
409 		if (!ast2600_sdrammc_cbr_test(info)) {
410 			fail_cnt++;
411 		} else {
412 			pass_cnt++;
413 		}
414 
415 		if (++test_cnt == target_cnt) {
416 			finish = true;
417 		}
418 		printf("pass/fail/total %d/%d/%d\n", pass_cnt, fail_cnt,
419 		       target_cnt);
420 	}
421 
422 	return fail_cnt;
423 }
424 
425 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
426 {
427         u32 vga_hwconf;
428         size_t vga_mem_size_base = 8 * 1024 * 1024;
429 
430         vga_hwconf = readl(info->scu + AST_SCU_HW_STRAP) &
431                      SCU_HWSTRAP_VGAMEM_MASK >> SCU_HWSTRAP_VGAMEM_SHIFT;
432 
433         return vga_mem_size_base << vga_hwconf;
434 }
435 #ifdef CONFIG_FPGA_ASPEED
436 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
437 {
438         u32 data;
439         u32 scu_base = (u32)info->scu;
440 
441         writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
442 
443         do {
444                 data = readl(scu_base + AST_SCU_FPGA_STATUS);
445         } while (!(data & 0x100));
446 
447         writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
448 }
449 
450 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
451 {
452         u32 pll, pll_min, pll_max, dat1, offset;
453         u32 win = 0x03, gwin = 0, gwinsize = 0;
454         u32 phy_setting = (u32)info->phy_setting;
455 
456         writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
457         writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
458 
459         while (gwin == 0) {
460                 while (!(win & 0x80)) {
461                         debug("Window = 0x%X\n", win);
462                         writel(win, phy_setting + 0x0000);
463 
464                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
465                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
466                         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
467                                 ast2600_sdrammc_fpga_set_pll(info);
468                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
469                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
470                         }
471 
472                         pll_min = 0xfff;
473                         pll_max = 0x0;
474                         pll = 0;
475                         while (pll_max > 0 || pll < 256) {
476                                 ast2600_sdrammc_fpga_set_pll(info);
477                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
478                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
479                                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
480                                         if (pll_min > pll) {
481                                                 pll_min = pll;
482                                         }
483                                         if (pll_max < pll) {
484                                                 pll_max = pll;
485                                         }
486                                         debug("%3d_(%3d:%3d)\n", pll, pll_min,
487                                                pll_max);
488                                 } else if (pll_max > 0) {
489                                         pll_min = pll_max - pll_min;
490                                         if (gwinsize < pll_min) {
491                                                 gwin = win;
492                                                 gwinsize = pll_min;
493                                         }
494                                         break;
495                                 }
496                                 pll += 1;
497                         }
498 
499                         if (gwin != 0 && pll_max == 0) {
500                                 break;
501                         }
502                         win = win << 1;
503                 }
504                 if (gwin == 0) {
505                         win = 0x7;
506                 }
507         }
508         debug("Set PLL Read Gating Window = %x\n", gwin);
509         writel(gwin, phy_setting + 0x0000);
510 
511         debug("PLL Read Window training\n");
512         pll_min = 0xfff;
513         pll_max = 0x0;
514 
515         debug("Search Window Start\n");
516         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
517         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
518         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
519                 ast2600_sdrammc_fpga_set_pll(info);
520                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
521                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
522         }
523 
524         debug("Search Window Margin\n");
525         pll = 0;
526         while (pll_max > 0 || pll < 256) {
527                 ast2600_sdrammc_fpga_set_pll(info);
528                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
529                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
530                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
531                         if (pll_min > pll) {
532                                 pll_min = pll;
533                         }
534                         if (pll_max < pll) {
535                                 pll_max = pll;
536                         }
537                         debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
538                 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
539                         break;
540                 } else if (pll_max > 0) {
541                         pll_min = 0xfff;
542                         pll_max = 0x0;
543                 }
544                 pll += 1;
545         }
546         if (pll_min < pll_max) {
547                 debug("PLL Read window = %d\n", (pll_max - pll_min));
548                 offset = (pll_max - pll_min) >> 1;
549                 pll_min = 0xfff;
550                 pll = 0;
551                 while (pll < (pll_min + offset)) {
552                         ast2600_sdrammc_fpga_set_pll(info);
553                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
554                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
555                         if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
556                                 if (pll_min > pll) {
557                                         pll_min = pll;
558                                 }
559                                 debug("%d\n", pll);
560                         } else {
561                                 pll_min = 0xfff;
562                                 pll_max = 0x0;
563                         }
564                         pll += 1;
565                 }
566                 return (1);
567         } else {
568                 debug("PLL Read window training fail\n");
569                 return (0);
570         }
571 }
572 #endif  /* end of "#ifdef CONFIG_FPGA_ASPEED" */
573 
574 /*
575  * Find out RAM size and save it in dram_info
576  *
577  * The procedure is taken from Aspeed SDK
578  */
579 static void ast2600_sdrammc_calc_size(struct dram_info *info)
580 {
581 	/* The controller supports 256/512/1024/2048 MB ram */
582 	size_t ram_size = SDRAM_MIN_SIZE;
583 	const int write_test_offset = 0x100000;
584 	u32 test_pattern = 0xdeadbeef;
585 	u32 cap_param = SDRAM_CONF_CAP_2048M;
586 	u32 refresh_timing_param = DDR4_TRFC;
587 	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
588 
589 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
590 	     ram_size >>= 1) {
591 		writel(test_pattern, write_addr_base + (ram_size >> 1));
592 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
593 	}
594 
595 	/* One last write to overwrite all wrapped values */
596 	writel(test_pattern, write_addr_base);
597 
598 	/* Reset the pattern and see which value was really written */
599 	test_pattern = 0xdeadbeef;
600 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
601 	     ram_size >>= 1) {
602 		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
603 			break;
604 
605 		--cap_param;
606 		refresh_timing_param >>= 8;
607 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
608 	}
609 
610 	clrsetbits_le32(&info->regs->ac_timing[1],
611 			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
612 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
613 			 << SDRAM_AC_TRFC_SHIFT));
614 
615 	info->info.base = CONFIG_SYS_SDRAM_BASE;
616 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
617 	clrsetbits_le32(&info->regs->config,
618 			(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
619 			((cap_param & SDRAM_CONF_CAP_MASK)
620 			 << SDRAM_CONF_CAP_SHIFT));
621 }
622 
623 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
624 {
625         const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
626                                MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
627                                MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
628                                (0x1 << MCR34_ODT_EXT_SHIFT);
629 
630 #ifdef CONFIG_ASPEED_DDR4_DUALX8
631 	setbits_le32(&info->regs->config, SDRAM_CONF_DDR4 | SDRAM_CONF_DUALX8);
632 #else
633 	setbits_le32(&info->regs->config, SDRAM_CONF_DDR4);
634 #endif
635 
636         /* init SDRAM-PHY only on real chip */
637 	ast2600_sdramphy_init(ast2600_sdramphy_config, info);
638 	ast2600_sdramphy_kick_training(info);
639         writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
640                &info->regs->power_ctrl);
641 	udelay(500);
642         writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
643 
644         writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
645         writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
646         writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
647         writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
648         writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
649         writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
650         writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
651                &info->regs->mode_setting_control);
652 
653 #ifdef CONFIG_FPGA_ASPEED
654         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
655                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT),
656                &info->regs->refresh_timing);
657 #else
658         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
659                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
660                &info->regs->refresh_timing);
661 #endif
662 
663         /* wait self-refresh idle */
664         while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
665                 ;
666 
667 #ifdef CONFIG_FPGA_ASPEED
668         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
669                    SDRAM_REFRESH_ZQCS_EN |
670                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) |
671                    (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
672                &info->regs->refresh_timing);
673 #else
674         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
675                    SDRAM_REFRESH_ZQCS_EN |
676                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
677                    (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
678                &info->regs->refresh_timing);
679 #endif
680 
681         writel(power_ctrl, &info->regs->power_ctrl);
682 	udelay(500);
683 
684 #ifdef CONFIG_FPGA_ASPEED
685         /* toggle Vref training */
686         setbits_le32(&info->regs->mr6_mode_setting, 0x80);
687         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
688                &info->regs->mode_setting_control);
689         clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
690         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
691                &info->regs->mode_setting_control);
692 #endif
693 	return 0;
694 }
695 
696 static void ast2600_sdrammc_unlock(struct dram_info *info)
697 {
698 	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
699 	while (!readl(&info->regs->protection_key))
700 		;
701 }
702 
703 static void ast2600_sdrammc_lock(struct dram_info *info)
704 {
705 	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
706 	while (readl(&info->regs->protection_key))
707 		;
708 }
709 
710 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
711 {
712 	int i;
713 
714         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
715         writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
716         writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
717                &regs->arbitration_ctrl);
718         writel(0xFFFFFFFF, &regs->req_limit_mask);
719 
720         for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
721                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
722 
723         writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
724 
725         /* FIXME: the sample code does NOT match the datasheet */
726         writel(0x7FFFFFF, &regs->ecc_range_ctrl);
727 
728         writel(0, &regs->ecc_test_ctrl);
729         writel(0, &regs->test_addr);
730         writel(0, &regs->test_fail_dq_bit);
731         writel(0, &regs->test_init_val);
732 
733         writel(0xFFFFFFFF, &regs->req_input_ctrl);
734         writel(0, &regs->req_high_pri_ctrl);
735 
736         udelay(500);
737 
738 	/* set capacity to the max size */
739         clrsetbits_le32(&regs->config, SDRAM_CONF_CAP_MASK,
740                         SDRAM_CONF_CAP_2048M);
741 
742 	/* load controller setting */
743 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
744 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
745 
746 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
747 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
748 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
749 	writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
750 }
751 
752 static int ast2600_sdrammc_probe(struct udevice *dev)
753 {
754 	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
755 	struct ast2600_sdrammc_regs *regs = priv->regs;
756 	struct udevice *clk_dev;
757 	int ret;
758 	uint32_t reg;
759 
760 	/* find SCU base address from clock device */
761 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
762                                           &clk_dev);
763 	if (ret) {
764 		debug("clock device not defined\n");
765 		return ret;
766 	}
767 
768 	priv->scu = devfdt_get_addr_ptr(clk_dev);
769 	if (IS_ERR(priv->scu)) {
770 		debug("%s(): can't get SCU\n", __func__);
771 		return PTR_ERR(priv->scu);
772 	}
773 
774 	if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) {
775 		debug("%s(): DDR SDRAM had been initialized\n", __func__);
776 		ast2600_sdrammc_calc_size(priv);
777 		return 0;
778 	}
779 
780 #ifdef AST2600_SDRAMMC_MANUAL_CLK
781 	reg = readl(priv->scu + AST_SCU_MPLL);
782 	reg &= ~(BIT(24) | GENMASK(22, 0));
783 	reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG);
784 	writel(reg, priv->scu + AST_SCU_MPLL);
785         writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
786 	udelay(100);
787 	reg &= ~(BIT(25) | BIT(23));
788 	writel(reg, priv->scu + AST_SCU_MPLL);
789 	while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)));
790 #else
791 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
792 	if (ret) {
793 		debug("DDR:No CLK\n");
794 		return ret;
795 	}
796 	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
797 #endif
798 
799 #if 0
800 	/* FIXME: enable the following code if reset-driver is ready */
801 	struct reset_ctl reset_ctl;
802 	ret = reset_get_by_index(dev, 0, &reset_ctl);
803 	if (ret) {
804 		debug("%s(): Failed to get reset signal\n", __func__);
805 		return ret;
806 	}
807 
808 	ret = reset_assert(&reset_ctl);
809 	if (ret) {
810 		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
811 		return ret;
812 	}
813 #endif
814 
815 	ast2600_sdrammc_unlock(priv);
816 	ast2600_sdrammc_common_init(regs);
817 
818 	if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) {
819 		debug("Unsupported SDRAM type: DDR3\n");
820 		return -EINVAL;
821 	} else {
822 		ast2600_sdrammc_init_ddr4(priv);
823 	}
824 
825 #ifdef CONFIG_FPGA_ASPEED
826         ast2600_sdrammc_search_read_window(priv);
827 #endif
828 
829 	ast2600_sdramphy_show_status(priv);
830 	ast2600_sdrammc_calc_size(priv);
831 
832 	if (0 != ast2600_sdrammc_test(priv)) {
833 		printf("%s: DDR4 init fail\n", __func__);
834 		return -EINVAL;
835 	}
836 
837 	writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK,
838 	       priv->scu + AST_SCU_HANDSHAKE);
839 
840 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
841 	ast2600_sdrammc_lock(priv);
842 	return 0;
843 }
844 
845 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
846 {
847 	struct dram_info *priv = dev_get_priv(dev);
848 
849 	priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
850 	priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
851 	priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
852 
853 	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
854 					  "clock-frequency", 0);
855 	if (!priv->clock_rate) {
856 		debug("DDR Clock Rate not defined\n");
857 		return -EINVAL;
858 	}
859 
860 	return 0;
861 }
862 
863 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
864 {
865 	struct dram_info *priv = dev_get_priv(dev);
866 
867 	*info = priv->info;
868 
869 	return 0;
870 }
871 
872 static struct ram_ops ast2600_sdrammc_ops = {
873 	.get_info = ast2600_sdrammc_get_info,
874 };
875 
876 static const struct udevice_id ast2600_sdrammc_ids[] = {
877 	{ .compatible = "aspeed,ast2600-sdrammc" },
878 	{ }
879 };
880 
881 U_BOOT_DRIVER(sdrammc_ast2600) = {
882 	.name = "aspeed_ast2600_sdrammc",
883 	.id = UCLASS_RAM,
884 	.of_match = ast2600_sdrammc_ids,
885 	.ops = &ast2600_sdrammc_ops,
886 	.ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
887 	.probe = ast2600_sdrammc_probe,
888 	.priv_auto_alloc_size = sizeof(struct dram_info),
889 };
890