1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/gpio/aspeed-gpio.h> 4#include "skeleton.dtsi" 5 6/ { 7 model = "Aspeed BMC"; 8 compatible = "aspeed,ast2600"; 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 12 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c4 = &i2c4; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 i2c7 = &i2c7; 22 i2c8 = &i2c8; 23 i2c9 = &i2c9; 24 i2c10 = &i2c10; 25 i2c11 = &i2c11; 26 i2c12 = &i2c12; 27 i2c13 = &i2c13; 28 i2c14 = &i2c14; 29 i2c15 = &i2c15; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 serial10 = &uart11; 41 serial11 = &uart12; 42 serial12 = &uart13; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "aspeed,ast2600-smp"; 49 50 cpu@0 { 51 compatible = "arm,cortex-a7"; 52 device_type = "cpu"; 53 reg = <0>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 71 }; 72 73 reserved-memory { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 gfx_memory: framebuffer { 79 size = <0x01000000>; 80 alignment = <0x01000000>; 81 compatible = "shared-dma-pool"; 82 reusable; 83 }; 84 85 video_memory: video { 86 size = <0x04000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 no-map; 90 }; 91 }; 92 93 ahb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 ranges; 99 100 gic: interrupt-controller@40461000 { 101 compatible = "arm,cortex-a7-gic"; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupt-parent = <&gic>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, 109 <0x40466000 0x2000>; 110 }; 111 112 ahbc: ahbc@1e600000 { 113 compatible = "aspeed,aspeed-ahbc"; 114 reg = < 0x1e600000 0x100>; 115 }; 116 117 fmc: flash-controller@1e620000 { 118 reg = < 0x1e620000 0xc4 119 0x20000000 0x10000000 >; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "aspeed,ast2600-fmc"; 123 status = "disabled"; 124 interrupts = <19>; 125 clocks = <&scu ASPEED_CLK_AHB>; 126 num-cs = <3>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2600-spi"; 150 clocks = <&scu ASPEED_CLK_AHB>; 151 num-cs = <2>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x50000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2600-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 num-cs = <3>; 173 status = "disabled"; 174 flash@0 { 175 reg = < 0 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 flash@1 { 180 reg = < 1 >; 181 compatible = "jedec,spi-nor"; 182 status = "disabled"; 183 }; 184 flash@2 { 185 reg = < 1 >; 186 compatible = "jedec,spi-nor"; 187 status = "disabled"; 188 }; 189 }; 190 191 edac: sdram@1e6e0000 { 192 compatible = "aspeed,ast2600-sdram-edac"; 193 reg = <0x1e6e0000 0x174>; 194 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 mdio: ethernet@1e650000 { 198 compatible = "aspeed,aspeed-mdio"; 199 reg = <0x1e650000 0x40>; 200 resets = <&rst ASPEED_RESET_MII>; 201 status = "disabled"; 202 }; 203 204 mac0: ftgmac@1e660000 { 205 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 206 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 207 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 209 status = "disabled"; 210 }; 211 212 mac1: ftgmac@1e680000 { 213 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 214 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 219#if 0 220 phy-handle = <&phy0>; 221#endif 222 status = "disabled"; 223 }; 224 225 mac2: ftgmac@1e670000 { 226 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 227 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 232#if 0 233 phy-handle = <&phy0>; 234#endif 235 status = "disabled"; 236 }; 237 238 mac3: ftgmac@1e690000 { 239 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 240 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 245#if 0 246 phy-handle = <&phy0>; 247#endif 248 status = "disabled"; 249 }; 250 251 apb { 252 compatible = "simple-bus"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges; 256 257 syscon: syscon@1e6e2000 { 258 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 259 reg = <0x1e6e2000 0x1000>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 #clock-cells = <1>; 263 #reset-cells = <1>; 264 ranges = <0 0x1e6e2000 0x1000>; 265 266 pinctrl: pinctrl { 267 compatible = "aspeed,g6-pinctrl"; 268 aspeed,external-nodes = <&gfx &lhc>; 269 270 }; 271 272 vga_scratch: scratch { 273 compatible = "aspeed,bmc-misc"; 274 }; 275 276 scu_ic0: interrupt-controller@0 { 277 #interrupt-cells = <1>; 278 compatible = "aspeed,ast2600-scu-ic"; 279 reg = <0x560 0x10>; 280 interrupt-parent = <&gic>; 281 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-controller; 283 }; 284 285 scu_ic1: interrupt-controller@1 { 286 #interrupt-cells = <1>; 287 compatible = "aspeed,ast2600-scu-ic"; 288 reg = <0x570 0x10>; 289 interrupt-parent = <&gic>; 290 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-controller; 292 }; 293 294 }; 295 296 smp-memram@0 { 297 compatible = "aspeed,ast2600-smpmem", "syscon"; 298 reg = <0x1e6e2180 0x40>; 299 }; 300 301 gfx: display@1e6e6000 { 302 compatible = "aspeed,ast2500-gfx", "syscon"; 303 reg = <0x1e6e6000 0x1000>; 304 reg-io-width = <4>; 305 }; 306 307 pcie_bridge: pcie_bridge@0x1e6ed000 { 308 compatible = "aspeed,ast2600-pcie"; 309 reg = <0x1e6ed000 0x100>, <0x60000000 0x20000000>; 310 }; 311 312 sdhci: sdhci@1e740000 { 313 #interrupt-cells = <1>; 314 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; 315 reg = <0x1e740000 0x1000>; 316 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 317 interrupt-controller; 318 clocks = <&scu ASPEED_CLK_GATE_SDCLK>, <&scu ASPEED_CLK_GATE_SDEXTCLK>; 319 clock-names = "ctrlclk", "extclk"; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges = <0x0 0x1e740000 0x1000>; 323 324 sdhci_slot0: sdhci_slot0@100 { 325 compatible = "aspeed,sdhci-ast2600"; 326 reg = <0x100 0x100>; 327 interrupts = <0>; 328 interrupt-parent = <&sdhci>; 329 sdhci,auto-cmd12; 330 clocks = <&scu ASPEED_CLK_SDIO>; 331 status = "disabled"; 332 }; 333 334 sdhci_slot1: sdhci_slot1@200 { 335 compatible = "aspeed,sdhci-ast2600"; 336 reg = <0x200 0x100>; 337 interrupts = <1>; 338 interrupt-parent = <&sdhci>; 339 sdhci,auto-cmd12; 340 clocks = <&scu ASPEED_CLK_SDIO>; 341 status = "disabled"; 342 }; 343 }; 344 345 emmc: emmc@1e750000 { 346 #interrupt-cells = <1>; 347 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; 348 reg = <0x1e750000 0x1000>; 349 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 350 interrupt-controller; 351 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; 352 clock-names = "ctrlclk", "extclk"; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges = <0x0 0x1e750000 0x1000>; 356 357 emmc_slot0: emmc_slot0@100 { 358 compatible = "aspeed,emmc-ast2600"; 359 reg = <0x100 0x100>; 360 interrupts = <0>; 361 interrupt-parent = <&emmc>; 362 clocks = <&scu ASPEED_CLK_EMMC>; 363 status = "disabled"; 364 }; 365 }; 366 367 h2x: h2x@1e770000 { 368 compatible = "aspeed,ast2600-h2x"; 369 reg = <0x1e770000 0x100>; 370 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 371 resets = <&rst ASPEED_RESET_H2X>; 372 }; 373 374 gpio0: gpio@1e780000 { 375 compatible = "aspeed,ast2600-gpio"; 376 reg = <0x1e780000 0x1000>; 377 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 378 #gpio-cells = <2>; 379 gpio-controller; 380 interrupt-controller; 381 gpio-ranges = <&pinctrl 0 0 220>; 382 }; 383 384 gpio1: gpio@1e780800 { 385 compatible = "aspeed,ast2600-gpio"; 386 reg = <0x1e780800 0x800>; 387 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 388 #gpio-cells = <2>; 389 gpio-controller; 390 interrupt-controller; 391 gpio-ranges = <&pinctrl 0 0 208>; 392 }; 393 394 uart1: serial@1e783000 { 395 compatible = "ns16550a"; 396 reg = <0x1e783000 0x20>; 397 reg-shift = <2>; 398 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 400 clock-frequency = <1846154>; 401 no-loopback-test; 402 status = "disabled"; 403 }; 404 405 uart5: serial@1e784000 { 406 compatible = "ns16550a"; 407 reg = <0x1e784000 0x1000>; 408 reg-shift = <2>; 409 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 411 clock-frequency = <1846154>; 412 no-loopback-test; 413 status = "disabled"; 414 }; 415 416 wdt1: watchdog@1e785000 { 417 compatible = "aspeed,ast2600-wdt"; 418 reg = <0x1e785000 0x40>; 419 }; 420 421 wdt2: watchdog@1e785040 { 422 compatible = "aspeed,ast2600-wdt"; 423 reg = <0x1e785040 0x40>; 424 }; 425 426 wdt3: watchdog@1e785080 { 427 compatible = "aspeed,ast2600-wdt"; 428 reg = <0x1e785080 0x40>; 429 }; 430 431 wdt4: watchdog@1e7850C0 { 432 compatible = "aspeed,ast2600-wdt"; 433 reg = <0x1e7850C0 0x40>; 434 }; 435 436 lpc: lpc@1e789000 { 437 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 438 reg = <0x1e789000 0x200>; 439 440 #address-cells = <1>; 441 #size-cells = <1>; 442 ranges = <0x0 0x1e789000 0x1000>; 443 444 lpc_bmc: lpc-bmc@0 { 445 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 446 reg = <0x0 0x80>; 447 reg-io-width = <4>; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges = <0x0 0x0 0x80>; 451 452 kcs1: kcs1@0 { 453 compatible = "aspeed,ast2600-kcs-bmc"; 454 reg = <0x0 0x80>; 455 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 456 kcs_chan = <1>; 457 kcs_addr = <0xCA0>; 458 status = "disabled"; 459 }; 460 461 kcs2: kcs2@0 { 462 compatible = "aspeed,ast2600-kcs-bmc"; 463 reg = <0x0 0x80>; 464 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 465 kcs_chan = <2>; 466 kcs_addr = <0xCA8>; 467 status = "disabled"; 468 }; 469 470 kcs3: kcs3@0 { 471 compatible = "aspeed,ast2600-kcs-bmc"; 472 reg = <0x0 0x80>; 473 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 474 kcs_chan = <3>; 475 kcs_addr = <0xCA2>; 476 }; 477 478 kcs4: kcs4@0 { 479 compatible = "aspeed,ast2600-kcs-bmc"; 480 reg = <0x0 0x120>; 481 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 482 kcs_chan = <4>; 483 kcs_addr = <0xCA4>; 484 status = "disabled"; 485 }; 486 487 }; 488 489 lpc_host: lpc-host@80 { 490 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 491 reg = <0x80 0x1e0>; 492 reg-io-width = <4>; 493 494 #address-cells = <1>; 495 #size-cells = <1>; 496 ranges = <0x0 0x80 0x1e0>; 497 498 lpc_ctrl: lpc-ctrl@0 { 499 compatible = "aspeed,ast2600-lpc-ctrl"; 500 reg = <0x0 0x80>; 501 status = "disabled"; 502 }; 503 504 lpc_snoop: lpc-snoop@0 { 505 compatible = "aspeed,ast2600-lpc-snoop"; 506 reg = <0x0 0x80>; 507 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 508 snoop-ports = <0x80>; 509 status = "disabled"; 510 }; 511 512 lhc: lhc@20 { 513 compatible = "aspeed,ast2600-lhc"; 514 reg = <0x20 0x24 0x48 0x8>; 515 }; 516 517 lpc_reset: reset-controller@18 { 518 compatible = "aspeed,ast2600-lpc-reset"; 519 reg = <0x18 0x4>; 520 #reset-cells = <1>; 521 status = "disabled"; 522 }; 523 524 ibt: ibt@c0 { 525 compatible = "aspeed,ast2600-ibt-bmc"; 526 reg = <0xc0 0x18>; 527 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 528 status = "disabled"; 529 }; 530 531 sio_regs: regs { 532 compatible = "aspeed,bmc-misc"; 533 }; 534 535 mbox: mbox@180 { 536 compatible = "aspeed,ast2600-mbox"; 537 reg = <0x180 0x5c>; 538 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 539 #mbox-cells = <1>; 540 status = "disabled"; 541 }; 542 }; 543 }; 544 545 uart2: serial@1e78d000 { 546 compatible = "ns16550a"; 547 reg = <0x1e78d000 0x20>; 548 reg-shift = <2>; 549 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 551 clock-frequency = <1846154>; 552 no-loopback-test; 553 status = "disabled"; 554 }; 555 556 uart3: serial@1e78e000 { 557 compatible = "ns16550a"; 558 reg = <0x1e78e000 0x20>; 559 reg-shift = <2>; 560 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 562 clock-frequency = <1846154>; 563 no-loopback-test; 564 status = "disabled"; 565 }; 566 567 uart4: serial@1e78f000 { 568 compatible = "ns16550a"; 569 reg = <0x1e78f000 0x20>; 570 reg-shift = <2>; 571 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 573 clock-frequency = <1846154>; 574 no-loopback-test; 575 status = "disabled"; 576 }; 577 578 i2c: bus@1e78a000 { 579 compatible = "simple-bus"; 580 #address-cells = <1>; 581 #size-cells = <1>; 582 ranges = <0 0x1e78a000 0x1000>; 583 }; 584 585 uart6: serial@1e790000 { 586 compatible = "ns16550a"; 587 reg = <0x1e790000 0x20>; 588 reg-shift = <2>; 589 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 591 clock-frequency = <1846154>; 592 no-loopback-test; 593 status = "disabled"; 594 }; 595 596 uart7: serial@1e790100 { 597 compatible = "ns16550a"; 598 reg = <0x1e790100 0x20>; 599 reg-shift = <2>; 600 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 602 clock-frequency = <1846154>; 603 no-loopback-test; 604 status = "disabled"; 605 }; 606 607 uart8: serial@1e790200 { 608 compatible = "ns16550a"; 609 reg = <0x1e790200 0x20>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 613 clock-frequency = <1846154>; 614 no-loopback-test; 615 status = "disabled"; 616 }; 617 618 uart9: serial@1e790300 { 619 compatible = "ns16550a"; 620 reg = <0x1e790300 0x20>; 621 reg-shift = <2>; 622 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 624 clock-frequency = <1846154>; 625 no-loopback-test; 626 status = "disabled"; 627 }; 628 629 uart10: serial@1e790400 { 630 compatible = "ns16550a"; 631 reg = <0x1e790400 0x20>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 635 clock-frequency = <1846154>; 636 no-loopback-test; 637 status = "disabled"; 638 }; 639 640 uart11: serial@1e790500 { 641 compatible = "ns16550a"; 642 reg = <0x1e790400 0x20>; 643 reg-shift = <2>; 644 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 646 clock-frequency = <1846154>; 647 no-loopback-test; 648 status = "disabled"; 649 }; 650 651 uart12: serial@1e790600 { 652 compatible = "ns16550a"; 653 reg = <0x1e790600 0x20>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 657 clock-frequency = <1846154>; 658 no-loopback-test; 659 status = "disabled"; 660 }; 661 662 uart13: serial@1e790700 { 663 compatible = "ns16550a"; 664 reg = <0x1e790700 0x20>; 665 reg-shift = <2>; 666 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 668 clock-frequency = <1846154>; 669 no-loopback-test; 670 status = "disabled"; 671 }; 672 673 674 675 }; 676 677 }; 678 679}; 680 681&i2c { 682 i2cglobal: i2cg@00 { 683 compatible = "aspeed,ast2600-i2c-global"; 684 reg = <0x0 0x40>; 685 resets = <&rst ASPEED_RESET_I2C>; 686#if 0 687 new-mode; 688#endif 689 }; 690 691 i2c0: i2c@80 { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 #interrupt-cells = <1>; 695 696 reg = <0x80 0x80 0xC00 0x20>; 697 compatible = "aspeed,ast2600-i2c-bus"; 698 bus-frequency = <100000>; 699 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&scu ASPEED_CLK_APB2>; 701 status = "disabled"; 702 }; 703 704 i2c1: i2c@100 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 #interrupt-cells = <1>; 708 709 reg = <0x100 0x80 0xC20 0x20>; 710 compatible = "aspeed,ast2600-i2c-bus"; 711 bus-frequency = <100000>; 712 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&scu ASPEED_CLK_APB2>; 714 status = "disabled"; 715 }; 716 717 i2c2: i2c@180 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 #interrupt-cells = <1>; 721 722 reg = <0x180 0x80 0xC40 0x20>; 723 compatible = "aspeed,ast2600-i2c-bus"; 724 bus-frequency = <100000>; 725 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&scu ASPEED_CLK_APB2>; 727 }; 728 729 i2c3: i2c@200 { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 #interrupt-cells = <1>; 733 734 reg = <0x200 0x40 0xC60 0x20>; 735 compatible = "aspeed,ast2600-i2c-bus"; 736 bus-frequency = <100000>; 737 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&scu ASPEED_CLK_APB2>; 739 }; 740 741 i2c4: i2c@280 { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 #interrupt-cells = <1>; 745 746 reg = <0x280 0x80 0xC80 0x20>; 747 compatible = "aspeed,ast2600-i2c-bus"; 748 bus-frequency = <100000>; 749 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&scu ASPEED_CLK_APB2>; 751 }; 752 753 i2c5: i2c@300 { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 #interrupt-cells = <1>; 757 758 reg = <0x300 0x40 0xCA0 0x20>; 759 compatible = "aspeed,ast2600-i2c-bus"; 760 bus-frequency = <100000>; 761 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&scu ASPEED_CLK_APB2>; 763 }; 764 765 i2c6: i2c@380 { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 #interrupt-cells = <1>; 769 770 reg = <0x380 0x80 0xCC0 0x20>; 771 compatible = "aspeed,ast2600-i2c-bus"; 772 bus-frequency = <100000>; 773 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&scu ASPEED_CLK_APB2>; 775 }; 776 777 i2c7: i2c@400 { 778 #address-cells = <1>; 779 #size-cells = <0>; 780 #interrupt-cells = <1>; 781 782 reg = <0x400 0x80 0xCE0 0x20>; 783 compatible = "aspeed,ast2600-i2c-bus"; 784 bus-frequency = <100000>; 785 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&scu ASPEED_CLK_APB2>; 787 }; 788 789 i2c8: i2c@480 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 #interrupt-cells = <1>; 793 794 reg = <0x480 0x80 0xD00 0x20>; 795 compatible = "aspeed,ast2600-i2c-bus"; 796 bus-frequency = <100000>; 797 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&scu ASPEED_CLK_APB2>; 799 }; 800 801 i2c9: i2c@500 { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #interrupt-cells = <1>; 805 806 reg = <0x500 0x80 0xD20 0x20>; 807 compatible = "aspeed,ast2600-i2c-bus"; 808 bus-frequency = <100000>; 809 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&scu ASPEED_CLK_APB2>; 811 status = "disabled"; 812 }; 813 814 i2c10: i2c@580 { 815 #address-cells = <1>; 816 #size-cells = <0>; 817 #interrupt-cells = <1>; 818 819 reg = <0x580 0x80 0xD40 0x20>; 820 compatible = "aspeed,ast2600-i2c-bus"; 821 bus-frequency = <100000>; 822 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&scu ASPEED_CLK_APB2>; 824 status = "disabled"; 825 }; 826 827 i2c11: i2c@600 { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 #interrupt-cells = <1>; 831 832 reg = <0x600 0x80 0xD60 0x20>; 833 compatible = "aspeed,ast2600-i2c-bus"; 834 bus-frequency = <100000>; 835 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&scu ASPEED_CLK_APB2>; 837 status = "disabled"; 838 }; 839 840 i2c12: i2c@680 { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 #interrupt-cells = <1>; 844 845 reg = <0x680 0x80 0xD80 0x20>; 846 compatible = "aspeed,ast2600-i2c-bus"; 847 bus-frequency = <100000>; 848 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&scu ASPEED_CLK_APB2>; 850 status = "disabled"; 851 }; 852 853 i2c13: i2c@700 { 854 #address-cells = <1>; 855 #size-cells = <0>; 856 #interrupt-cells = <1>; 857 858 reg = <0x700 0x80 0xDA0 0x20>; 859 compatible = "aspeed,ast2600-i2c-bus"; 860 bus-frequency = <100000>; 861 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&scu ASPEED_CLK_APB2>; 863 status = "disabled"; 864 }; 865 866 i2c14: i2c@780 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 #interrupt-cells = <1>; 870 871 reg = <0x780 0x80 0xDC0 0x20>; 872 compatible = "aspeed,ast2600-i2c-bus"; 873 bus-frequency = <100000>; 874 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&scu ASPEED_CLK_APB2>; 876 status = "disabled"; 877 }; 878 879 i2c15: i2c@800 { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 #interrupt-cells = <1>; 883 884 reg = <0x800 0x80 0xDE0 0x20>; 885 compatible = "aspeed,ast2600-i2c-bus"; 886 bus-frequency = <100000>; 887 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&scu ASPEED_CLK_APB2>; 889 status = "disabled"; 890 }; 891 892}; 893 894&pinctrl { 895 pinctrl_fmcquad_default: fmcquad_default { 896 function = "FMCQUAD"; 897 groups = "FMCQUAD"; 898 }; 899 900 pinctrl_spi1_default: spi1_default { 901 function = "SPI1"; 902 groups = "SPI1"; 903 }; 904 905 pinctrl_spi1abr_default: spi1abr_default { 906 function = "SPI1ABR"; 907 groups = "SPI1ABR"; 908 }; 909 910 pinctrl_spi1cs1_default: spi1cs1_default { 911 function = "SPI1CS1"; 912 groups = "SPI1CS1"; 913 }; 914 915 pinctrl_spi1wp_default: spi1wp_default { 916 function = "SPI1WP"; 917 groups = "SPI1WP"; 918 }; 919 920 pinctrl_spi1quad_default: spi1quad_default { 921 function = "SPI1QUAD"; 922 groups = "SPI1QUAD"; 923 }; 924 925 pinctrl_spi2_default: spi2_default { 926 function = "SPI2"; 927 groups = "SPI2"; 928 }; 929 930 pinctrl_spi2cs1_default: spi2cs1_default { 931 function = "SPI2CS1"; 932 groups = "SPI2CS1"; 933 }; 934 935 pinctrl_spi2cs2_default: spi2cs2_default { 936 function = "SPI2CS2"; 937 groups = "SPI2CS2"; 938 }; 939 940 pinctrl_spi2quad_default: spi2quad_default { 941 function = "SPI2QUAD"; 942 groups = "SPI2QUAD"; 943 }; 944 945 pinctrl_acpi_default: acpi_default { 946 function = "ACPI"; 947 groups = "ACPI"; 948 }; 949 950 pinctrl_adc0_default: adc0_default { 951 function = "ADC0"; 952 groups = "ADC0"; 953 }; 954 955 pinctrl_adc1_default: adc1_default { 956 function = "ADC1"; 957 groups = "ADC1"; 958 }; 959 960 pinctrl_adc10_default: adc10_default { 961 function = "ADC10"; 962 groups = "ADC10"; 963 }; 964 965 pinctrl_adc11_default: adc11_default { 966 function = "ADC11"; 967 groups = "ADC11"; 968 }; 969 970 pinctrl_adc12_default: adc12_default { 971 function = "ADC12"; 972 groups = "ADC12"; 973 }; 974 975 pinctrl_adc13_default: adc13_default { 976 function = "ADC13"; 977 groups = "ADC13"; 978 }; 979 980 pinctrl_adc14_default: adc14_default { 981 function = "ADC14"; 982 groups = "ADC14"; 983 }; 984 985 pinctrl_adc15_default: adc15_default { 986 function = "ADC15"; 987 groups = "ADC15"; 988 }; 989 990 pinctrl_adc2_default: adc2_default { 991 function = "ADC2"; 992 groups = "ADC2"; 993 }; 994 995 pinctrl_adc3_default: adc3_default { 996 function = "ADC3"; 997 groups = "ADC3"; 998 }; 999 1000 pinctrl_adc4_default: adc4_default { 1001 function = "ADC4"; 1002 groups = "ADC4"; 1003 }; 1004 1005 pinctrl_adc5_default: adc5_default { 1006 function = "ADC5"; 1007 groups = "ADC5"; 1008 }; 1009 1010 pinctrl_adc6_default: adc6_default { 1011 function = "ADC6"; 1012 groups = "ADC6"; 1013 }; 1014 1015 pinctrl_adc7_default: adc7_default { 1016 function = "ADC7"; 1017 groups = "ADC7"; 1018 }; 1019 1020 pinctrl_adc8_default: adc8_default { 1021 function = "ADC8"; 1022 groups = "ADC8"; 1023 }; 1024 1025 pinctrl_adc9_default: adc9_default { 1026 function = "ADC9"; 1027 groups = "ADC9"; 1028 }; 1029 1030 pinctrl_bmcint_default: bmcint_default { 1031 function = "BMCINT"; 1032 groups = "BMCINT"; 1033 }; 1034 1035 pinctrl_ddcclk_default: ddcclk_default { 1036 function = "DDCCLK"; 1037 groups = "DDCCLK"; 1038 }; 1039 1040 pinctrl_ddcdat_default: ddcdat_default { 1041 function = "DDCDAT"; 1042 groups = "DDCDAT"; 1043 }; 1044 1045 pinctrl_espi_default: espi_default { 1046 function = "ESPI"; 1047 groups = "ESPI"; 1048 }; 1049 1050 pinctrl_fwspics1_default: fwspics1_default { 1051 function = "FWSPICS1"; 1052 groups = "FWSPICS1"; 1053 }; 1054 1055 pinctrl_fwspics2_default: fwspics2_default { 1056 function = "FWSPICS2"; 1057 groups = "FWSPICS2"; 1058 }; 1059 1060 pinctrl_gpid0_default: gpid0_default { 1061 function = "GPID0"; 1062 groups = "GPID0"; 1063 }; 1064 1065 pinctrl_gpid2_default: gpid2_default { 1066 function = "GPID2"; 1067 groups = "GPID2"; 1068 }; 1069 1070 pinctrl_gpid4_default: gpid4_default { 1071 function = "GPID4"; 1072 groups = "GPID4"; 1073 }; 1074 1075 pinctrl_gpid6_default: gpid6_default { 1076 function = "GPID6"; 1077 groups = "GPID6"; 1078 }; 1079 1080 pinctrl_gpie0_default: gpie0_default { 1081 function = "GPIE0"; 1082 groups = "GPIE0"; 1083 }; 1084 1085 pinctrl_gpie2_default: gpie2_default { 1086 function = "GPIE2"; 1087 groups = "GPIE2"; 1088 }; 1089 1090 pinctrl_gpie4_default: gpie4_default { 1091 function = "GPIE4"; 1092 groups = "GPIE4"; 1093 }; 1094 1095 pinctrl_gpie6_default: gpie6_default { 1096 function = "GPIE6"; 1097 groups = "GPIE6"; 1098 }; 1099 1100 pinctrl_i2c10_default: i2c10_default { 1101 function = "I2C10"; 1102 groups = "I2C10"; 1103 }; 1104 1105 pinctrl_i2c11_default: i2c11_default { 1106 function = "I2C11"; 1107 groups = "I2C11"; 1108 }; 1109 1110 pinctrl_i2c12_default: i2c12_default { 1111 function = "I2C12"; 1112 groups = "I2C12"; 1113 }; 1114 1115 pinctrl_i2c13_default: i2c13_default { 1116 function = "I2C13"; 1117 groups = "I2C13"; 1118 }; 1119 1120 pinctrl_i2c14_default: i2c14_default { 1121 function = "I2C14"; 1122 groups = "I2C14"; 1123 }; 1124 1125 pinctrl_i2c3_default: i2c3_default { 1126 function = "I2C3"; 1127 groups = "I2C3"; 1128 }; 1129 1130 pinctrl_i2c4_default: i2c4_default { 1131 function = "I2C4"; 1132 groups = "I2C4"; 1133 }; 1134 1135 pinctrl_i2c5_default: i2c5_default { 1136 function = "I2C5"; 1137 groups = "I2C5"; 1138 }; 1139 1140 pinctrl_i2c6_default: i2c6_default { 1141 function = "I2C6"; 1142 groups = "I2C6"; 1143 }; 1144 1145 pinctrl_i2c7_default: i2c7_default { 1146 function = "I2C7"; 1147 groups = "I2C7"; 1148 }; 1149 1150 pinctrl_i2c8_default: i2c8_default { 1151 function = "I2C8"; 1152 groups = "I2C8"; 1153 }; 1154 1155 pinctrl_i2c9_default: i2c9_default { 1156 function = "I2C9"; 1157 groups = "I2C9"; 1158 }; 1159 1160 pinctrl_lad0_default: lad0_default { 1161 function = "LAD0"; 1162 groups = "LAD0"; 1163 }; 1164 1165 pinctrl_lad1_default: lad1_default { 1166 function = "LAD1"; 1167 groups = "LAD1"; 1168 }; 1169 1170 pinctrl_lad2_default: lad2_default { 1171 function = "LAD2"; 1172 groups = "LAD2"; 1173 }; 1174 1175 pinctrl_lad3_default: lad3_default { 1176 function = "LAD3"; 1177 groups = "LAD3"; 1178 }; 1179 1180 pinctrl_lclk_default: lclk_default { 1181 function = "LCLK"; 1182 groups = "LCLK"; 1183 }; 1184 1185 pinctrl_lframe_default: lframe_default { 1186 function = "LFRAME"; 1187 groups = "LFRAME"; 1188 }; 1189 1190 pinctrl_lpchc_default: lpchc_default { 1191 function = "LPCHC"; 1192 groups = "LPCHC"; 1193 }; 1194 1195 pinctrl_lpcpd_default: lpcpd_default { 1196 function = "LPCPD"; 1197 groups = "LPCPD"; 1198 }; 1199 1200 pinctrl_lpcplus_default: lpcplus_default { 1201 function = "LPCPLUS"; 1202 groups = "LPCPLUS"; 1203 }; 1204 1205 pinctrl_lpcpme_default: lpcpme_default { 1206 function = "LPCPME"; 1207 groups = "LPCPME"; 1208 }; 1209 1210 pinctrl_lpcrst_default: lpcrst_default { 1211 function = "LPCRST"; 1212 groups = "LPCRST"; 1213 }; 1214 1215 pinctrl_lpcsmi_default: lpcsmi_default { 1216 function = "LPCSMI"; 1217 groups = "LPCSMI"; 1218 }; 1219 1220 pinctrl_lsirq_default: lsirq_default { 1221 function = "LSIRQ"; 1222 groups = "LSIRQ"; 1223 }; 1224 1225 pinctrl_mac1link_default: mac1link_default { 1226 function = "MAC1LINK"; 1227 groups = "MAC1LINK"; 1228 }; 1229 1230 pinctrl_mac2link_default: mac2link_default { 1231 function = "MAC2LINK"; 1232 groups = "MAC2LINK"; 1233 }; 1234 1235 pinctrl_mac3link_default: mac3link_default { 1236 function = "MAC3LINK"; 1237 groups = "MAC3LINK"; 1238 }; 1239 1240 pinctrl_mac4link_default: mac4link_default { 1241 function = "MAC4LINK"; 1242 groups = "MAC4LINK"; 1243 }; 1244 1245 pinctrl_mdio1_default: mdio1_default { 1246 function = "MDIO1"; 1247 groups = "MDIO1"; 1248 }; 1249 1250 pinctrl_mdio2_default: mdio2_default { 1251 function = "MDIO2"; 1252 groups = "MDIO2"; 1253 }; 1254 1255 pinctrl_mdio3_default: mdio3_default { 1256 function = "MDIO3"; 1257 groups = "MDIO3"; 1258 }; 1259 1260 pinctrl_mdio4_default: mdio4_default { 1261 function = "MDIO4"; 1262 groups = "MDIO4"; 1263 }; 1264 1265 pinctrl_ncts1_default: ncts1_default { 1266 function = "NCTS1"; 1267 groups = "NCTS1"; 1268 }; 1269 1270 pinctrl_ncts2_default: ncts2_default { 1271 function = "NCTS2"; 1272 groups = "NCTS2"; 1273 }; 1274 1275 pinctrl_ncts3_default: ncts3_default { 1276 function = "NCTS3"; 1277 groups = "NCTS3"; 1278 }; 1279 1280 pinctrl_ncts4_default: ncts4_default { 1281 function = "NCTS4"; 1282 groups = "NCTS4"; 1283 }; 1284 1285 pinctrl_ndcd1_default: ndcd1_default { 1286 function = "NDCD1"; 1287 groups = "NDCD1"; 1288 }; 1289 1290 pinctrl_ndcd2_default: ndcd2_default { 1291 function = "NDCD2"; 1292 groups = "NDCD2"; 1293 }; 1294 1295 pinctrl_ndcd3_default: ndcd3_default { 1296 function = "NDCD3"; 1297 groups = "NDCD3"; 1298 }; 1299 1300 pinctrl_ndcd4_default: ndcd4_default { 1301 function = "NDCD4"; 1302 groups = "NDCD4"; 1303 }; 1304 1305 pinctrl_ndsr1_default: ndsr1_default { 1306 function = "NDSR1"; 1307 groups = "NDSR1"; 1308 }; 1309 1310 pinctrl_ndsr2_default: ndsr2_default { 1311 function = "NDSR2"; 1312 groups = "NDSR2"; 1313 }; 1314 1315 pinctrl_ndsr3_default: ndsr3_default { 1316 function = "NDSR3"; 1317 groups = "NDSR3"; 1318 }; 1319 1320 pinctrl_ndsr4_default: ndsr4_default { 1321 function = "NDSR4"; 1322 groups = "NDSR4"; 1323 }; 1324 1325 pinctrl_ndtr1_default: ndtr1_default { 1326 function = "NDTR1"; 1327 groups = "NDTR1"; 1328 }; 1329 1330 pinctrl_ndtr2_default: ndtr2_default { 1331 function = "NDTR2"; 1332 groups = "NDTR2"; 1333 }; 1334 1335 pinctrl_ndtr3_default: ndtr3_default { 1336 function = "NDTR3"; 1337 groups = "NDTR3"; 1338 }; 1339 1340 pinctrl_ndtr4_default: ndtr4_default { 1341 function = "NDTR4"; 1342 groups = "NDTR4"; 1343 }; 1344 1345 pinctrl_nri1_default: nri1_default { 1346 function = "NRI1"; 1347 groups = "NRI1"; 1348 }; 1349 1350 pinctrl_nri2_default: nri2_default { 1351 function = "NRI2"; 1352 groups = "NRI2"; 1353 }; 1354 1355 pinctrl_nri3_default: nri3_default { 1356 function = "NRI3"; 1357 groups = "NRI3"; 1358 }; 1359 1360 pinctrl_nri4_default: nri4_default { 1361 function = "NRI4"; 1362 groups = "NRI4"; 1363 }; 1364 1365 pinctrl_nrts1_default: nrts1_default { 1366 function = "NRTS1"; 1367 groups = "NRTS1"; 1368 }; 1369 1370 pinctrl_nrts2_default: nrts2_default { 1371 function = "NRTS2"; 1372 groups = "NRTS2"; 1373 }; 1374 1375 pinctrl_nrts3_default: nrts3_default { 1376 function = "NRTS3"; 1377 groups = "NRTS3"; 1378 }; 1379 1380 pinctrl_nrts4_default: nrts4_default { 1381 function = "NRTS4"; 1382 groups = "NRTS4"; 1383 }; 1384 1385 pinctrl_oscclk_default: oscclk_default { 1386 function = "OSCCLK"; 1387 groups = "OSCCLK"; 1388 }; 1389 1390 pinctrl_pewake_default: pewake_default { 1391 function = "PEWAKE"; 1392 groups = "PEWAKE"; 1393 }; 1394 1395 pinctrl_pnor_default: pnor_default { 1396 function = "PNOR"; 1397 groups = "PNOR"; 1398 }; 1399 1400 pinctrl_pwm0_default: pwm0_default { 1401 function = "PWM0"; 1402 groups = "PWM0"; 1403 }; 1404 1405 pinctrl_pwm1_default: pwm1_default { 1406 function = "PWM1"; 1407 groups = "PWM1"; 1408 }; 1409 1410 pinctrl_pwm2_default: pwm2_default { 1411 function = "PWM2"; 1412 groups = "PWM2"; 1413 }; 1414 1415 pinctrl_pwm3_default: pwm3_default { 1416 function = "PWM3"; 1417 groups = "PWM3"; 1418 }; 1419 1420 pinctrl_pwm4_default: pwm4_default { 1421 function = "PWM4"; 1422 groups = "PWM4"; 1423 }; 1424 1425 pinctrl_pwm5_default: pwm5_default { 1426 function = "PWM5"; 1427 groups = "PWM5"; 1428 }; 1429 1430 pinctrl_pwm6_default: pwm6_default { 1431 function = "PWM6"; 1432 groups = "PWM6"; 1433 }; 1434 1435 pinctrl_pwm7_default: pwm7_default { 1436 function = "PWM7"; 1437 groups = "PWM7"; 1438 }; 1439 1440 pinctrl_rgmii1_default: rgmii1_default { 1441 function = "RGMII1"; 1442 groups = "RGMII1"; 1443 }; 1444 1445 pinctrl_rgmii2_default: rgmii2_default { 1446 function = "RGMII2"; 1447 groups = "RGMII2"; 1448 }; 1449 1450 pinctrl_rmii1_default: rmii1_default { 1451 function = "RMII1"; 1452 groups = "RMII1"; 1453 }; 1454 1455 pinctrl_rmii2_default: rmii2_default { 1456 function = "RMII2"; 1457 groups = "RMII2"; 1458 }; 1459 1460 pinctrl_rxd1_default: rxd1_default { 1461 function = "RXD1"; 1462 groups = "RXD1"; 1463 }; 1464 1465 pinctrl_rxd2_default: rxd2_default { 1466 function = "RXD2"; 1467 groups = "RXD2"; 1468 }; 1469 1470 pinctrl_rxd3_default: rxd3_default { 1471 function = "RXD3"; 1472 groups = "RXD3"; 1473 }; 1474 1475 pinctrl_rxd4_default: rxd4_default { 1476 function = "RXD4"; 1477 groups = "RXD4"; 1478 }; 1479 1480 pinctrl_salt1_default: salt1_default { 1481 function = "SALT1"; 1482 groups = "SALT1"; 1483 }; 1484 1485 pinctrl_salt10_default: salt10_default { 1486 function = "SALT10"; 1487 groups = "SALT10"; 1488 }; 1489 1490 pinctrl_salt11_default: salt11_default { 1491 function = "SALT11"; 1492 groups = "SALT11"; 1493 }; 1494 1495 pinctrl_salt12_default: salt12_default { 1496 function = "SALT12"; 1497 groups = "SALT12"; 1498 }; 1499 1500 pinctrl_salt13_default: salt13_default { 1501 function = "SALT13"; 1502 groups = "SALT13"; 1503 }; 1504 1505 pinctrl_salt14_default: salt14_default { 1506 function = "SALT14"; 1507 groups = "SALT14"; 1508 }; 1509 1510 pinctrl_salt2_default: salt2_default { 1511 function = "SALT2"; 1512 groups = "SALT2"; 1513 }; 1514 1515 pinctrl_salt3_default: salt3_default { 1516 function = "SALT3"; 1517 groups = "SALT3"; 1518 }; 1519 1520 pinctrl_salt4_default: salt4_default { 1521 function = "SALT4"; 1522 groups = "SALT4"; 1523 }; 1524 1525 pinctrl_salt5_default: salt5_default { 1526 function = "SALT5"; 1527 groups = "SALT5"; 1528 }; 1529 1530 pinctrl_salt6_default: salt6_default { 1531 function = "SALT6"; 1532 groups = "SALT6"; 1533 }; 1534 1535 pinctrl_salt7_default: salt7_default { 1536 function = "SALT7"; 1537 groups = "SALT7"; 1538 }; 1539 1540 pinctrl_salt8_default: salt8_default { 1541 function = "SALT8"; 1542 groups = "SALT8"; 1543 }; 1544 1545 pinctrl_salt9_default: salt9_default { 1546 function = "SALT9"; 1547 groups = "SALT9"; 1548 }; 1549 1550 pinctrl_scl1_default: scl1_default { 1551 function = "SCL1"; 1552 groups = "SCL1"; 1553 }; 1554 1555 pinctrl_scl2_default: scl2_default { 1556 function = "SCL2"; 1557 groups = "SCL2"; 1558 }; 1559 1560 pinctrl_sd1_default: sd1_default { 1561 function = "SD1"; 1562 groups = "SD1"; 1563 }; 1564 1565 pinctrl_sd2_default: sd2_default { 1566 function = "SD2"; 1567 groups = "SD2"; 1568 }; 1569 1570 pinctrl_emmc_default: emmc_default { 1571 function = "EMMC"; 1572 groups = "EMMC"; 1573 }; 1574 1575 pinctrl_sda1_default: sda1_default { 1576 function = "SDA1"; 1577 groups = "SDA1"; 1578 }; 1579 1580 pinctrl_sda2_default: sda2_default { 1581 function = "SDA2"; 1582 groups = "SDA2"; 1583 }; 1584 1585 pinctrl_sgps1_default: sgps1_default { 1586 function = "SGPS1"; 1587 groups = "SGPS1"; 1588 }; 1589 1590 pinctrl_sgps2_default: sgps2_default { 1591 function = "SGPS2"; 1592 groups = "SGPS2"; 1593 }; 1594 1595 pinctrl_sioonctrl_default: sioonctrl_default { 1596 function = "SIOONCTRL"; 1597 groups = "SIOONCTRL"; 1598 }; 1599 1600 pinctrl_siopbi_default: siopbi_default { 1601 function = "SIOPBI"; 1602 groups = "SIOPBI"; 1603 }; 1604 1605 pinctrl_siopbo_default: siopbo_default { 1606 function = "SIOPBO"; 1607 groups = "SIOPBO"; 1608 }; 1609 1610 pinctrl_siopwreq_default: siopwreq_default { 1611 function = "SIOPWREQ"; 1612 groups = "SIOPWREQ"; 1613 }; 1614 1615 pinctrl_siopwrgd_default: siopwrgd_default { 1616 function = "SIOPWRGD"; 1617 groups = "SIOPWRGD"; 1618 }; 1619 1620 pinctrl_sios3_default: sios3_default { 1621 function = "SIOS3"; 1622 groups = "SIOS3"; 1623 }; 1624 1625 pinctrl_sios5_default: sios5_default { 1626 function = "SIOS5"; 1627 groups = "SIOS5"; 1628 }; 1629 1630 pinctrl_siosci_default: siosci_default { 1631 function = "SIOSCI"; 1632 groups = "SIOSCI"; 1633 }; 1634 1635 pinctrl_spi1_default: spi1_default { 1636 function = "SPI1"; 1637 groups = "SPI1"; 1638 }; 1639 1640 pinctrl_spi1cs1_default: spi1cs1_default { 1641 function = "SPI1CS1"; 1642 groups = "SPI1CS1"; 1643 }; 1644 1645 pinctrl_spi1debug_default: spi1debug_default { 1646 function = "SPI1DEBUG"; 1647 groups = "SPI1DEBUG"; 1648 }; 1649 1650 pinctrl_spi1passthru_default: spi1passthru_default { 1651 function = "SPI1PASSTHRU"; 1652 groups = "SPI1PASSTHRU"; 1653 }; 1654 1655 pinctrl_spi2ck_default: spi2ck_default { 1656 function = "SPI2CK"; 1657 groups = "SPI2CK"; 1658 }; 1659 1660 pinctrl_spi2cs0_default: spi2cs0_default { 1661 function = "SPI2CS0"; 1662 groups = "SPI2CS0"; 1663 }; 1664 1665 pinctrl_spi2cs1_default: spi2cs1_default { 1666 function = "SPI2CS1"; 1667 groups = "SPI2CS1"; 1668 }; 1669 1670 pinctrl_spi2miso_default: spi2miso_default { 1671 function = "SPI2MISO"; 1672 groups = "SPI2MISO"; 1673 }; 1674 1675 pinctrl_spi2mosi_default: spi2mosi_default { 1676 function = "SPI2MOSI"; 1677 groups = "SPI2MOSI"; 1678 }; 1679 1680 pinctrl_timer3_default: timer3_default { 1681 function = "TIMER3"; 1682 groups = "TIMER3"; 1683 }; 1684 1685 pinctrl_timer4_default: timer4_default { 1686 function = "TIMER4"; 1687 groups = "TIMER4"; 1688 }; 1689 1690 pinctrl_timer5_default: timer5_default { 1691 function = "TIMER5"; 1692 groups = "TIMER5"; 1693 }; 1694 1695 pinctrl_timer6_default: timer6_default { 1696 function = "TIMER6"; 1697 groups = "TIMER6"; 1698 }; 1699 1700 pinctrl_timer7_default: timer7_default { 1701 function = "TIMER7"; 1702 groups = "TIMER7"; 1703 }; 1704 1705 pinctrl_timer8_default: timer8_default { 1706 function = "TIMER8"; 1707 groups = "TIMER8"; 1708 }; 1709 1710 pinctrl_txd1_default: txd1_default { 1711 function = "TXD1"; 1712 groups = "TXD1"; 1713 }; 1714 1715 pinctrl_txd2_default: txd2_default { 1716 function = "TXD2"; 1717 groups = "TXD2"; 1718 }; 1719 1720 pinctrl_txd3_default: txd3_default { 1721 function = "TXD3"; 1722 groups = "TXD3"; 1723 }; 1724 1725 pinctrl_txd4_default: txd4_default { 1726 function = "TXD4"; 1727 groups = "TXD4"; 1728 }; 1729 1730 pinctrl_uart6_default: uart6_default { 1731 function = "UART6"; 1732 groups = "UART6"; 1733 }; 1734 1735 pinctrl_usbcki_default: usbcki_default { 1736 function = "USBCKI"; 1737 groups = "USBCKI"; 1738 }; 1739 1740 pinctrl_usb2ah_default: usb2ah_default { 1741 function = "USB2AH"; 1742 groups = "USB2AH"; 1743 }; 1744 1745 pinctrl_usb11bhid_default: usb11bhid_default { 1746 function = "USB11BHID"; 1747 groups = "USB11BHID"; 1748 }; 1749 1750 pinctrl_usb2bh_default: usb2bh_default { 1751 function = "USB2BH"; 1752 groups = "USB2BH"; 1753 }; 1754 1755 pinctrl_vgabiosrom_default: vgabiosrom_default { 1756 function = "VGABIOSROM"; 1757 groups = "VGABIOSROM"; 1758 }; 1759 1760 pinctrl_vgahs_default: vgahs_default { 1761 function = "VGAHS"; 1762 groups = "VGAHS"; 1763 }; 1764 1765 pinctrl_vgavs_default: vgavs_default { 1766 function = "VGAVS"; 1767 groups = "VGAVS"; 1768 }; 1769 1770 pinctrl_vpi24_default: vpi24_default { 1771 function = "VPI24"; 1772 groups = "VPI24"; 1773 }; 1774 1775 pinctrl_vpo_default: vpo_default { 1776 function = "VPO"; 1777 groups = "VPO"; 1778 }; 1779 1780 pinctrl_wdtrst1_default: wdtrst1_default { 1781 function = "WDTRST1"; 1782 groups = "WDTRST1"; 1783 }; 1784 1785 pinctrl_wdtrst2_default: wdtrst2_default { 1786 function = "WDTRST2"; 1787 groups = "WDTRST2"; 1788 }; 1789}; 1790