xref: /openbmc/u-boot/drivers/ram/aspeed/sdram_ast2600.c (revision 84ee0840e4cd9046c7b9cd66903acec6fb757f2e)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012-2020  ASPEED Technology Inc.
4  *
5  * Copyright 2016 Google, Inc
6  */
7 
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <reset.h>
15 #include <asm/io.h>
16 #include <asm/arch/scu_ast2600.h>
17 #include <asm/arch/sdram_ast2600.h>
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <dt-bindings/clock/ast2600-clock.h>
21 #include "sdram_phy_ast2600.h"
22 
23 /* in order to speed up DRAM init time, write pre-defined values to registers
24  * directly */
25 #define AST2600_SDRAMMC_MANUAL_CLK
26 
27 /* register offset */
28 #define AST_SCU_FPGA_STATUS	0x004
29 #define AST_SCU_HANDSHAKE	0x100
30 #define AST_SCU_MPLL		0x220
31 #define AST_SCU_MPLL_EXT	0x224
32 #define AST_SCU_FPGA_PLL	0x400
33 #define AST_SCU_HW_STRAP	0x500
34 
35 
36 /* bit-field of AST_SCU_HW_STRAP */
37 #define SCU_HWSTRAP_VGAMEM_SHIFT	2
38 #define SCU_HWSTRAP_VGAMEM_MASK		(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
39 #define SCU_HWSTRAP_DDR3		(1 << 25)
40 
41 
42 /* bit-field of AST_SCU_HANDSHAKE */
43 #define SCU_SDRAM_INIT_READY_MASK	BIT(6)
44 #define SCU_SDRAM_INIT_BY_SOC_MASK	BIT(7)
45 
46 /* bit-field of AST_SCU_MPLL */
47 #define SCU_MPLL_RESET			BIT(25)
48 #define SCU_MPLL_BYPASS			BIT(24)
49 #define SCU_MPLL_TURN_OFF		BIT(23)
50 #define SCU_MPLL_FREQ_MASK		GENMASK(22, 0)
51 
52 #define SCU_MPLL_FREQ_400M		0x0008405F
53 #define SCU_MPLL_EXT_400M		0x00000031
54 //#define SCU_MPLL_FREQ_400M		0x0038007F
55 //#define SCU_MPLL_EXT_400M		0x0000003F
56 #define SCU_MPLL_FREQ_200M		0x0078007F
57 #define SCU_MPLL_EXT_200M		0x0000003F
58 
59 /* MPLL configuration */
60 #if defined(CONFIG_ASPEED_DDR4_800)
61 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_200M
62 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_200M
63 #elif defined(CONFIG_ASPEED_DDR4_1600)
64 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_400M
65 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_400M
66 #else
67 #error "undefined DDR4 target rate\n"
68 #endif
69 
70 /* AC timing and SDRAM mode registers */
71 #ifdef CONFIG_FPGA_ASPEED
72 /* mode register settings for FPGA are fixed */
73 #define DDR4_MR01_MODE		0x03010100
74 #define DDR4_MR23_MODE		0x00000000
75 #define DDR4_MR45_MODE		0x04C00000
76 #define DDR4_MR6_MODE		0x00000050
77 #define DDR4_TRFC_FPGA		0x17263434
78 
79 /* FPGA need for an additional initialization procedure: search read window */
80 #define SEARCH_RDWIN_ANCHOR_0   (CONFIG_SYS_SDRAM_BASE + 0x0000)
81 #define SEARCH_RDWIN_ANCHOR_1   (CONFIG_SYS_SDRAM_BASE + 0x0004)
82 #define SEARCH_RDWIN_PTRN_0     0x12345678
83 #define SEARCH_RDWIN_PTRN_1     0xaabbccdd
84 #define SEARCH_RDWIN_PTRN_SUM   0xbcf02355
85 #else
86 /* mode register setting for real chip are derived from the model GDDR4-1600 */
87 #define DDR4_MR01_MODE		0x03010510
88 #define DDR4_MR23_MODE		0x00000000
89 #define DDR4_MR45_MODE		0x04000000
90 #define DDR4_MR6_MODE           0x00000400
91 #define DDR4_TRFC_1600		0x467299f1
92 #define DDR4_TRFC_800		0x23394c78
93 #endif  /* end of "#ifdef CONFIG_FPGA_ASPEED" */
94 
95 #if defined(CONFIG_FPGA_ASPEED)
96 #define DDR4_TRFC			DDR4_TRFC_FPGA
97 #else
98 /* real chip setting */
99 #if defined(CONFIG_ASPEED_DDR4_1600)
100 #define DDR4_TRFC			DDR4_TRFC_1600
101 #define DDR4_PHY_TRAIN_TRFC		0xc30
102 #elif defined(CONFIG_ASPEED_DDR4_800)
103 #define DDR4_TRFC			DDR4_TRFC_800
104 #define DDR4_PHY_TRAIN_TRFC		0x618
105 #else
106 #error "undefined tRFC setting"
107 #endif	/* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
108 #endif	/* end of "#if defined(CONFIG_FPGA_ASPEED)" */
109 
110 /* supported SDRAM size */
111 #define SDRAM_SIZE_1KB		(1024U)
112 #define SDRAM_SIZE_1MB		(SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
113 #define SDRAM_MIN_SIZE		(256 * SDRAM_SIZE_1MB)
114 #define SDRAM_MAX_SIZE		(2048 * SDRAM_SIZE_1MB)
115 
116 
117 DECLARE_GLOBAL_DATA_PTR;
118 
119 /*
120  * Bandwidth configuration parameters for different SDRAM requests.
121  * These are hardcoded settings taken from Aspeed SDK.
122  */
123 #ifdef CONFIG_FPGA_ASPEED
124 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200,
125                                       0x00000140};
126 
127 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888,
128                                             0x88888888};
129 #else
130 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304,
131                                       0x00001240};
132 
133 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444,
134                                             0x44444444};
135 #endif
136 
137 struct dram_info {
138 	struct ram_info info;
139 	struct clk ddr_clk;
140 	struct ast2600_sdrammc_regs *regs;
141 	void __iomem *scu;
142 	struct ast2600_ddr_phy *phy;
143 	void __iomem *phy_setting;
144 	void __iomem *phy_status;
145 	ulong clock_rate;
146 };
147 
148 static void ast2600_sdramphy_kick_training(struct dram_info *info)
149 {
150 #ifndef CONFIG_FPGA_ASPEED
151         struct ast2600_sdrammc_regs *regs = info->regs;
152         u32 mask = SDRAM_PHYCTRL0_INIT | SDRAM_PHYCTRL0_PLL_LOCKED;
153         u32 data;
154 
155 	writel(0, &regs->phy_ctrl[0]);
156 	udelay(5000);
157         writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
158 	udelay(1000);
159         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
160 	udelay(1000);
161         /* wait for (PLL_LOCKED == 1) and (INIT == 0) */
162 	debug("%s: wait for PHY PLL lock\n", __func__);
163 	while (1) {
164 		data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_PLL_LOCKED;
165 		if (data) {
166 			break;
167 		}
168 	}
169 
170 	debug("%s: wait for PHY init done\n", __func__);
171 	while (1) {
172 		data = readl(&regs->phy_ctrl[0]) | SDRAM_PHYCTRL0_INIT;
173 		if (~data) {
174 			break;
175 		}
176 	}
177 
178 #ifdef CONFIG_ASPEED_DDR4_800
179 	do {
180 		data = readl(0x1e6e0400);
181 	} while((data & 0x7) != 0x7);
182 #endif
183 #endif
184 }
185 
186 /**
187  * @brief	load DDR-PHY configurations table to the PHY registers
188  * @param[in]	p_tbl - pointer to the configuration table
189  * @param[in]	info - pointer to the DRAM info struct
190  *
191  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
192  * system: one is in the SDRAM MC (memory controller) which is used in run
193  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
194  * training.  To make these two configurations align, we overwrite the DDR-PHY
195  * setting by the MC setting before DDR-PHY training.
196 */
197 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
198 {
199 #ifndef CONFIG_FPGA_ASPEED
200 	u32 reg_base = (u32)info->phy_setting;
201 	u32 addr = p_tbl[0];
202         u32 data;
203         int i = 1;
204 
205         debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base,
206                addr);
207 
208         /* load PHY configuration table into PHY-setting registers */
209         while (1) {
210                 if (addr < reg_base) {
211                         debug("invalid DDR-PHY addr: 0x%08x\n", addr);
212                         break;
213                 }
214                 data = p_tbl[i++];
215 
216                 if (DDR_PHY_TBL_END == data) {
217                         break;
218                 } else if (DDR_PHY_TBL_CHG_ADDR == data) {
219                         addr = p_tbl[i++];
220                 } else {
221                         writel(data, addr);
222                         addr += 4;
223                 }
224         }
225 
226 	data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
227 	data |= DDR4_PHY_TRAIN_TRFC;
228 	writel(data, info->phy_setting + 0x84);
229 
230 #ifdef CONFIG_ASPEED_DDR4_800
231 
232 	debug("Overwrite DDR-PHY MRS by MCR config\n");
233 	/* MR0 and MR1 */
234 	data = readl(&info->regs->mr01_mode_setting);
235 	data =
236 	    ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16);
237 	writel(data, reg_base + 0x58);
238 	debug("[%08x] 0x%08x\n", reg_base + 0x58, data);
239 
240 	/* MR2 and MR3 */
241 	data = readl(&info->regs->mr23_mode_setting);
242 	writel(data, reg_base + 0x54);
243 	debug("[%08x] 0x%08x\n", reg_base + 0x54, data);
244 
245 	/* MR4 and MR5 */
246 	data = readl(&info->regs->mr45_mode_setting);
247 	writel(data, reg_base + 0x5c);
248 	debug("[%08x] 0x%08x\n", reg_base + 0x5c, data);
249 
250 	/* MR6 */
251 	data = readl(&info->regs->mr6_mode_setting);
252 	writel(data, reg_base + 0x60);
253 	debug("[%08x] 0x%08x\n", reg_base + 0x60, data);
254 #endif
255 #endif
256 }
257 
258 static void ast2600_sdramphy_show_status(struct dram_info *info)
259 {
260 #ifndef CONFIG_FPGA_ASPEED
261         u32 value, tmp;
262         u32 reg_base = (u32)info->phy_status;
263 
264 	printf("\n");
265 	/* training status */
266         value = readl(reg_base + 0x00);
267 	printf("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
268         if (value & BIT(3)) {
269                 debug("\tinitial PVT calibration fail\n");
270         }
271         if (value & BIT(5)) {
272                 debug("\truntime calibration fail\n");
273         }
274 
275 	/* PU & PD */
276 	value = readl(reg_base + 0x30);
277 	printf("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
278         printf("  PU = 0x%02x\n", value & 0xff);
279         printf("  PD = 0x%02x\n", (value >> 16) & 0xff);
280 
281 	/* read eye window */
282         value = readl(reg_base + 0x68);
283 	printf("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
284 	printf("  rising edge of read data eye training pass window\n");
285 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
286 	printf("    B0:%d\%\n", tmp);
287 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
288         printf("    B1:%d\%\n", tmp);
289 
290 	value = readl(reg_base + 0xC8);
291 	printf("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
292 	printf("  falling edge of read data eye training pass window\n");
293 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
294 	printf("    B0:%d\%\n", tmp);
295 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
296         printf("    B1:%d\%\n", tmp);
297 
298         /* write eye window */
299         value = readl(reg_base + 0x7c);
300 	printf("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
301 	printf("  rising edge of write data eye training pass window\n");
302 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
303 	printf("    B0:%d\%\n", tmp);
304 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
305         printf("    B1:%d\%\n", tmp);
306 
307 	/* read Vref training result */
308         value = readl(reg_base + 0x88);
309 	printf("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
310         printf("  read Vref training result\n");
311 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
312 	printf("    B0:%d\%\n", tmp);
313 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
314         printf("    B1:%d\%\n", tmp);
315 
316         /* write Vref training result */
317         value = readl(reg_base + 0x90);
318 	printf("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
319 	tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127;
320         printf("  write Vref training result = %d\%\n", tmp);
321 
322         /* gate train */
323 	value = readl(reg_base + 0x50);
324 	printf("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
325 	printf("  gate training pass window\n");
326 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
327 	printf("    module 0: %d.%03d\n", (value >> 8) & 0xff, tmp);
328         tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255;
329 	printf("    module 1: %d.%03d\n", (value >> 24) & 0xff, tmp);
330 #endif
331 }
332 
333 #define MC_TEST_PATTERN_N 8
334 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
335     0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
336     0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253};
337 
338 #define DRAM_MapAdr	81000000
339 #define TIMEOUT_DRAM	5000000
340 int MMCTestSingle1(unsigned int datagen)
341 {
342 	unsigned int data;
343 	unsigned int timeout = 0;
344 
345 	writel(0x00000000, 0x1E6E0070);
346 	writel((0x00000085 | (datagen << 3)), 0x1E6E0070);
347 
348 	do {
349 		data = readl(0x1E6E0070) & 0x3000;
350 
351 		if( data & 0x2000 )
352 			return(0);
353 
354 		if( ++timeout > TIMEOUT_DRAM ){
355 			printf("Timeout!!\n");
356 			writel(0x00000000, 0x1E6E0070);
357 
358 			return(0);
359 		}
360 	} while ( !data );
361 
362 	writel(0x00000000, 0x1E6E0070);
363 
364 	return(1);
365 }
366 int MMCTestBurst1(unsigned int datagen)
367 {
368 	unsigned int data;
369 	unsigned int timeout = 0;
370 
371 	writel(0x00000000, 0x1E6E0070);
372 	writel((0x000000C1 | (datagen << 3)), 0x1E6E0070);
373 
374 	do {
375 		data = readl(0x1E6E0070) & 0x3000;
376 
377 		if( data & 0x2000 )
378 			return(0);
379 
380 		if( ++timeout > TIMEOUT_DRAM ) {
381 			printf("Timeout!!\n");
382 			writel(0x00000000, 0x1E6E0070);
383 			return(0);
384 		}
385 	} while (!data);
386 
387 	writel(0x00000000, 0x1E6E0070);
388 
389 	return(1);
390 }
391 
392 int MMCTest1(void)
393 {
394 	writel((DRAM_MapAdr | 0x7fffff), 0x1E6E0074);
395 
396   	if(!MMCTestSingle1(0))   return(0);
397 	if(!MMCTestSingle1(1))   return(0);
398 	if(!MMCTestSingle1(2))   return(0);
399 	if(!MMCTestSingle1(3))   return(0);
400 	if(!MMCTestSingle1(4))   return(0);
401 	if(!MMCTestSingle1(5))   return(0);
402 	if(!MMCTestSingle1(6))   return(0);
403 	if(!MMCTestSingle1(7))   return(0);
404 	if(!MMCTestBurst1(0))    return(0);
405 	if(!MMCTestBurst1(1))    return(0);
406 	if(!MMCTestBurst1(2))    return(0);
407 	if(!MMCTestBurst1(3))    return(0);
408 	if(!MMCTestBurst1(4))    return(0);
409 	if(!MMCTestBurst1(5))    return(0);
410 	if(!MMCTestBurst1(6))    return(0);
411 	if(!MMCTestBurst1(7))    return(0);
412 
413 
414 	return(1);
415 }
416 
417 static int ast2600_sdrammc_test(void)
418 {
419 	u32 pass_cnt = 0;
420 	u32 fail_cnt = 0;
421 	u32 target_cnt = 2;
422 	u32 test_cnt = 0;
423 	u32 pattern;
424 	u32 i = 0;
425 	bool finish = false;
426 
427 	while (finish == false) {
428 		pattern = as2600_sdrammc_test_pattern[i++];
429 		i = i % MC_TEST_PATTERN_N;
430 		printf("Pattern = %08X : ",pattern);
431 		writel(pattern, 0x1E6E007C);
432 
433 		if (!MMCTest1()) {
434 			fail_cnt++;
435 		} else {
436 			pass_cnt++;
437 		}
438 
439 		if (++test_cnt == target_cnt) {
440 			finish = true;
441 		}
442 		printf("pass/fail/total %d/%d/%d\n", pass_cnt, fail_cnt,
443 		       target_cnt);
444 	}
445 
446 	return fail_cnt;
447 }
448 
449 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
450 {
451         u32 vga_hwconf;
452         size_t vga_mem_size_base = 8 * 1024 * 1024;
453 
454         vga_hwconf = readl(info->scu + AST_SCU_HW_STRAP) &
455                      SCU_HWSTRAP_VGAMEM_MASK >> SCU_HWSTRAP_VGAMEM_SHIFT;
456 
457         return vga_mem_size_base << vga_hwconf;
458 }
459 #ifdef CONFIG_FPGA_ASPEED
460 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
461 {
462         u32 data;
463         u32 scu_base = (u32)info->scu;
464 
465         writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
466 
467         do {
468                 data = readl(scu_base + AST_SCU_FPGA_STATUS);
469         } while (!(data & 0x100));
470 
471         writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
472 }
473 
474 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
475 {
476         u32 pll, pll_min, pll_max, dat1, offset;
477         u32 win = 0x03, gwin = 0, gwinsize = 0;
478         u32 phy_setting = (u32)info->phy_setting;
479 
480         writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
481         writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
482 
483         while (gwin == 0) {
484                 while (!(win & 0x80)) {
485                         debug("Window = 0x%X\n", win);
486                         writel(win, phy_setting + 0x0000);
487 
488                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
489                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
490                         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
491                                 ast2600_sdrammc_fpga_set_pll(info);
492                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
493                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
494                         }
495 
496                         pll_min = 0xfff;
497                         pll_max = 0x0;
498                         pll = 0;
499                         while (pll_max > 0 || pll < 256) {
500                                 ast2600_sdrammc_fpga_set_pll(info);
501                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
502                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
503                                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
504                                         if (pll_min > pll) {
505                                                 pll_min = pll;
506                                         }
507                                         if (pll_max < pll) {
508                                                 pll_max = pll;
509                                         }
510                                         debug("%3d_(%3d:%3d)\n", pll, pll_min,
511                                                pll_max);
512                                 } else if (pll_max > 0) {
513                                         pll_min = pll_max - pll_min;
514                                         if (gwinsize < pll_min) {
515                                                 gwin = win;
516                                                 gwinsize = pll_min;
517                                         }
518                                         break;
519                                 }
520                                 pll += 1;
521                         }
522 
523                         if (gwin != 0 && pll_max == 0) {
524                                 break;
525                         }
526                         win = win << 1;
527                 }
528                 if (gwin == 0) {
529                         win = 0x7;
530                 }
531         }
532         debug("Set PLL Read Gating Window = %x\n", gwin);
533         writel(gwin, phy_setting + 0x0000);
534 
535         debug("PLL Read Window training\n");
536         pll_min = 0xfff;
537         pll_max = 0x0;
538 
539         debug("Search Window Start\n");
540         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
541         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
542         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
543                 ast2600_sdrammc_fpga_set_pll(info);
544                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
545                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
546         }
547 
548         debug("Search Window Margin\n");
549         pll = 0;
550         while (pll_max > 0 || pll < 256) {
551                 ast2600_sdrammc_fpga_set_pll(info);
552                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
553                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
554                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
555                         if (pll_min > pll) {
556                                 pll_min = pll;
557                         }
558                         if (pll_max < pll) {
559                                 pll_max = pll;
560                         }
561                         debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
562                 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
563                         break;
564                 } else if (pll_max > 0) {
565                         pll_min = 0xfff;
566                         pll_max = 0x0;
567                 }
568                 pll += 1;
569         }
570         if (pll_min < pll_max) {
571                 debug("PLL Read window = %d\n", (pll_max - pll_min));
572                 offset = (pll_max - pll_min) >> 1;
573                 pll_min = 0xfff;
574                 pll = 0;
575                 while (pll < (pll_min + offset)) {
576                         ast2600_sdrammc_fpga_set_pll(info);
577                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
578                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
579                         if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
580                                 if (pll_min > pll) {
581                                         pll_min = pll;
582                                 }
583                                 debug("%d\n", pll);
584                         } else {
585                                 pll_min = 0xfff;
586                                 pll_max = 0x0;
587                         }
588                         pll += 1;
589                 }
590                 return (1);
591         } else {
592                 debug("PLL Read window training fail\n");
593                 return (0);
594         }
595 }
596 #endif  /* end of "#ifdef CONFIG_FPGA_ASPEED" */
597 
598 /*
599  * Find out RAM size and save it in dram_info
600  *
601  * The procedure is taken from Aspeed SDK
602  */
603 static void ast2600_sdrammc_calc_size(struct dram_info *info)
604 {
605 	/* The controller supports 256/512/1024/2048 MB ram */
606 	size_t ram_size = SDRAM_MIN_SIZE;
607 	const int write_test_offset = 0x100000;
608 	u32 test_pattern = 0xdeadbeef;
609 	u32 cap_param = SDRAM_CONF_CAP_2048M;
610 	u32 refresh_timing_param = DDR4_TRFC;
611 	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
612 
613 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
614 	     ram_size >>= 1) {
615 		writel(test_pattern, write_addr_base + (ram_size >> 1));
616 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
617 	}
618 
619 	/* One last write to overwrite all wrapped values */
620 	writel(test_pattern, write_addr_base);
621 
622 	/* Reset the pattern and see which value was really written */
623 	test_pattern = 0xdeadbeef;
624 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
625 	     ram_size >>= 1) {
626 		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
627 			break;
628 
629 		--cap_param;
630 		refresh_timing_param >>= 8;
631 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
632 	}
633 
634 	clrsetbits_le32(&info->regs->ac_timing[1],
635 			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
636 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
637 			 << SDRAM_AC_TRFC_SHIFT));
638 
639 	info->info.base = CONFIG_SYS_SDRAM_BASE;
640 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
641 	clrsetbits_le32(&info->regs->config,
642 			(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
643 			((cap_param & SDRAM_CONF_CAP_MASK)
644 			 << SDRAM_CONF_CAP_SHIFT));
645 }
646 
647 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
648 {
649         const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
650                                MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
651                                MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
652                                (0x1 << MCR34_ODT_EXT_SHIFT);
653 
654 #ifdef CONFIG_ASPEED_DDR4_DUALX8
655 	setbits_le32(&info->regs->config, SDRAM_CONF_DDR4 | SDRAM_CONF_DUALX8);
656 #else
657 	setbits_le32(&info->regs->config, SDRAM_CONF_DDR4);
658 #endif
659 
660         /* init SDRAM-PHY only on real chip */
661 	ast2600_sdramphy_init(ast2600_sdramphy_config, info);
662 	ast2600_sdramphy_kick_training(info);
663         writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
664                &info->regs->power_ctrl);
665 	udelay(500);
666         writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
667 
668         writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
669         writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
670         writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
671         writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
672         writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
673         writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
674         writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
675                &info->regs->mode_setting_control);
676 
677 #ifdef CONFIG_FPGA_ASPEED
678         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
679                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT),
680                &info->regs->refresh_timing);
681 #else
682         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
683                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
684                &info->regs->refresh_timing);
685 #endif
686 
687         /* wait self-refresh idle */
688         while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
689                 ;
690 
691 #ifdef CONFIG_FPGA_ASPEED
692         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
693                    SDRAM_REFRESH_ZQCS_EN |
694                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) |
695                    (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
696                &info->regs->refresh_timing);
697 #else
698         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
699                    SDRAM_REFRESH_ZQCS_EN |
700                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
701                    (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
702                &info->regs->refresh_timing);
703 #endif
704 
705         writel(power_ctrl, &info->regs->power_ctrl);
706 	udelay(500);
707 
708 #ifdef CONFIG_FPGA_ASPEED
709         /* toggle Vref training */
710         setbits_le32(&info->regs->mr6_mode_setting, 0x80);
711         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
712                &info->regs->mode_setting_control);
713         clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
714         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
715                &info->regs->mode_setting_control);
716 #endif
717 	return 0;
718 }
719 
720 static void ast2600_sdrammc_unlock(struct dram_info *info)
721 {
722 	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
723 	while (!readl(&info->regs->protection_key))
724 		;
725 }
726 
727 static void ast2600_sdrammc_lock(struct dram_info *info)
728 {
729 	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
730 	while (readl(&info->regs->protection_key))
731 		;
732 }
733 
734 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
735 {
736 	int i;
737 
738         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
739         writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
740         writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
741                &regs->arbitration_ctrl);
742         writel(0xFFFFFFFF, &regs->req_limit_mask);
743 
744         for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
745                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
746 
747         writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
748 
749         /* FIXME: the sample code does NOT match the datasheet */
750         writel(0x7FFFFFF, &regs->ecc_range_ctrl);
751 
752         writel(0, &regs->ecc_test_ctrl);
753         writel(0, &regs->test_addr);
754         writel(0, &regs->test_fail_dq_bit);
755         writel(0, &regs->test_init_val);
756 
757         writel(0xFFFFFFFF, &regs->req_input_ctrl);
758         writel(0, &regs->req_high_pri_ctrl);
759 
760         udelay(500);
761 
762 	/* set capacity to the max size */
763         clrsetbits_le32(&regs->config, SDRAM_CONF_CAP_MASK,
764                         SDRAM_CONF_CAP_2048M);
765 
766 	/* load controller setting */
767 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
768 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
769 
770 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
771 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
772 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
773 	writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
774 }
775 
776 static int ast2600_sdrammc_probe(struct udevice *dev)
777 {
778 	struct reset_ctl reset_ctl;
779 	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
780 	struct ast2600_sdrammc_regs *regs = priv->regs;
781 	struct udevice *clk_dev;
782 	int ret;
783 	uint32_t reg;
784 
785 	/* find SCU base address from clock device */
786 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
787                                           &clk_dev);
788 	if (ret) {
789 		debug("clock device not defined\n");
790 		return ret;
791 	}
792 
793 	priv->scu = devfdt_get_addr_ptr(clk_dev);
794 	if (IS_ERR(priv->scu)) {
795 		debug("%s(): can't get SCU\n", __func__);
796 		return PTR_ERR(priv->scu);
797 	}
798 
799 	if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) {
800 		debug("%s(): DDR SDRAM had been initialized\n", __func__);
801 		ast2600_sdrammc_calc_size(priv);
802 		return 0;
803 	}
804 
805 #ifdef AST2600_SDRAMMC_MANUAL_CLK
806 	reg = readl(priv->scu + AST_SCU_MPLL);
807 	reg &= ~(BIT(24) | GENMASK(22, 0));
808 	reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG);
809 	writel(reg, priv->scu + AST_SCU_MPLL);
810         writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
811 	udelay(100);
812 	reg &= ~(BIT(25) | BIT(23));
813 	writel(reg, priv->scu + AST_SCU_MPLL);
814 	while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)));
815 #else
816 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
817 	if (ret) {
818 		debug("DDR:No CLK\n");
819 		return ret;
820 	}
821 	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
822 #endif
823 
824 #if 0
825 	/* FIXME: enable the following code if reset-driver is ready */
826 	ret = reset_get_by_index(dev, 0, &reset_ctl);
827 	if (ret) {
828 		debug("%s(): Failed to get reset signal\n", __func__);
829 		return ret;
830 	}
831 
832 	ret = reset_assert(&reset_ctl);
833 	if (ret) {
834 		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
835 		return ret;
836 	}
837 #endif
838 
839 	ast2600_sdrammc_unlock(priv);
840 	ast2600_sdrammc_common_init(regs);
841 
842 	if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) {
843 		debug("Unsupported SDRAM type: DDR3\n");
844 		return -EINVAL;
845 	} else {
846 		ast2600_sdrammc_init_ddr4(priv);
847 	}
848 
849 #ifdef CONFIG_FPGA_ASPEED
850         ast2600_sdrammc_search_read_window(priv);
851 #endif
852 
853 	ast2600_sdramphy_show_status(priv);
854 	ast2600_sdrammc_calc_size(priv);
855 
856 	if (0 != ast2600_sdrammc_test()) {
857 		printf("%s: DDR4 init fail\n", __func__);
858 		return -EINVAL;
859 	}
860 
861 	writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK,
862 	       priv->scu + AST_SCU_HANDSHAKE);
863 
864 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
865 	ast2600_sdrammc_lock(priv);
866 	return 0;
867 }
868 
869 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
870 {
871 	struct dram_info *priv = dev_get_priv(dev);
872 	int ret;
873 
874 	priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
875 	priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
876 	priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
877 
878 	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
879 					  "clock-frequency", 0);
880 	if (!priv->clock_rate) {
881 		debug("DDR Clock Rate not defined\n");
882 		return -EINVAL;
883 	}
884 
885 	return 0;
886 }
887 
888 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
889 {
890 	struct dram_info *priv = dev_get_priv(dev);
891 
892 	*info = priv->info;
893 
894 	return 0;
895 }
896 
897 static struct ram_ops ast2600_sdrammc_ops = {
898 	.get_info = ast2600_sdrammc_get_info,
899 };
900 
901 static const struct udevice_id ast2600_sdrammc_ids[] = {
902 	{ .compatible = "aspeed,ast2600-sdrammc" },
903 	{ }
904 };
905 
906 U_BOOT_DRIVER(sdrammc_ast2600) = {
907 	.name = "aspeed_ast2600_sdrammc",
908 	.id = UCLASS_RAM,
909 	.of_match = ast2600_sdrammc_ids,
910 	.ops = &ast2600_sdrammc_ops,
911 	.ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
912 	.probe = ast2600_sdrammc_probe,
913 	.priv_auto_alloc_size = sizeof(struct dram_info),
914 };
915