1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * 17 * Version : 2 18 * Release date: 2019.02.19 19 * 20 * Priority of fix item: 21 * [P1] = critical 22 * [P2] = nice to have 23 * [P3] = minor 24 * 25 * Change List : 26 * V0 |2018.03.28 : 1.[P1] Initial release for simulation 27 * 28 * Optional define variable 29 * 30 ****************************************************************************** 31 */ 32 33#include <config.h> 34#include <version.h> 35#include <asm/secure.h> 36#include <asm/armv7.h> 37#include <linux/linkage.h> 38 39/* 40 * SMP mailbox 41 * +----------------------+ 42 * | | 43 * | mailbox insn. for | 44 * | cpuN polling SMP go | 45 * | | 46 * +----------------------+ 0xC 47 * | mailbox ready signal | 48 * +----------------------+ 0x8 49 * | cpuN GO signal | 50 * +----------------------+ 0x4 51 * | cpuN entrypoint | 52 * +----------------------+ AST_SMP_MAILBOX_BASE 53 */ 54 55#define AST_SMP_MAILBOX_BASE 0x1E6E2180 56#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 57#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 58#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 59#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 60 61/* AST2600 HW registers */ 62#define AST_SCU_BASE 0x1E6E2000 63#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) 64#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) 65#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) 66#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) 67 68#define AST_FMC_BASE 0x1E620000 69#define AST_FMC_WDT1_CTRL_MODE (AST_FMC_BASE + 0x060) 70#define AST_FMC_WDT2_CTRL_MODE (AST_FMC_BASE + 0x064) 71 72#define AST_UART_BASE 0x1E784000 73 74/* Revision ID */ 75#define REV_ID_AST2600A0 0x05000303 76 77ENTRY(ast_bootmode) 78 ldr r1, =AST_SCU_HW_STRAP1 79 ldr r0, [r1] 80 tst r0, #0x4 81 moveq r0, #0x0 @; AST_BOOTMODE_SPI 82 movne r0, #0x1 @; AST_BOOTMODE_EMMC 83 mov pc, lr 84ENDPROC(ast_bootmode) 85 86.macro timer_init 87#ifdef CONFIG_FPGA_ASPEED 88 movw r0, #0x0 89 movt r0, #0x2500 90#else 91 ldr r0, =AST_SCU_REV_ID 92 ldr r0, [r0] 93 94 ldr r1, =REV_ID_AST2600A0 95 cmp r0, r1 96 97 movweq r0, #0x0800 98 movteq r0, #0x2FAF @; 800MHz for A0 99 movwne r0, #0x8C00 100 movtne r0, #0x4786 @; 1.2GHz for A1 101#endif 102 /* write CNTFRQ */ 103 mcr p15, 0, r0, c14, c0, 0 104.endm 105 106 107.globl lowlevel_init 108 109lowlevel_init: 110#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 111 mov pc, lr 112#else 113 /* setup timer frequency for ARM generic timer */ 114 timer_init 115 116 /* 117 * we treat cpu0 as the primary core and 118 * put secondary core (cpuN) to sleep 119 */ 120 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 121 ands r0, r0, #0x03 @; Mask off, leaving the CPU ID field 122 123 beq do_primary_core_setup 124 125 /* hold cpuN until mailbox is ready */ 126poll_mailbox_ready: 127 wfe 128 ldr r0, =AST_SMP_MBOX_FIELD_READY 129 ldr r1, =0xBABECAFE 130 ldr r2, [r0] 131 cmp r1, r2 132 bne poll_mailbox_ready 133 134 /* parameters for relocated SMP go polling insn. */ 135 ldr r0, =AST_SMP_MBOX_FIELD_GOSIGN 136 ldr r1, =AST_SMP_MBOX_FIELD_ENTRY 137 ldr r2, =0xABBAADDA 138 ldr r3, =AST_UART_BASE 139 140 /* no return */ 141 ldr pc, =AST_SMP_MBOX_FIELD_POLLINSN 142 143do_primary_core_setup: 144 /* unlock SCU */ 145 ldr r0, =0x1688A8A8 @; magic key to unlock SCU 146 ldr r1, =AST_SCU_PROT_KEY1 147 str r0, [r1] 148 ldr r1, =AST_SCU_PROT_KEY2 149 str r0, [r1] 150 151 /* disable FMC WDT for SPI address mode detection */ 152 mov r0, #0 153 ldr r1, =AST_FMC_WDT1_CTRL_MODE 154 str r0, [r1] 155 ldr r1, =AST_FMC_WDT2_CTRL_MODE 156 str r0, [r1] 157 158 /* relocate mailbox insn. for cpuN polling SMP go signal */ 159 adrl r0, mailbox_insn 160 adrl r1, mailbox_insn_end 161 162 ldr r2, =#AST_SMP_MBOX_FIELD_POLLINSN 163 164relocate_mailbox_insn: 165 ldr r3, [r0], #0x4 166 str r3, [r2], #0x4 167 cmp r0, r1 168 bne relocate_mailbox_insn 169 170 /* notify cpuN mailbox is ready */ 171 ldr r0, =AST_SMP_MBOX_FIELD_READY 172 ldr r1, =0xBABECAFE 173 str r1, [r0] 174 sev 175 176 /* back to arch calling code */ 177 mov pc, lr 178 179/* 180 * insn. inside mailbox to poll SMP go signal. 181 * 182 * Note that as this code will be relocated, any 183 * pc-relative assembly should NOT be used. 184 */ 185mailbox_insn: 186 /* 187 * r0 ~ r3 are parameters: 188 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 189 * r1 = AST_SMP_MBOX_FIELD_ENTRY 190 * r2 = 0xABBAADDA 191 * r3 = AST_UART_BASE (for debug purpose) 192 */ 193poll_mailbox_smp_go: 194 wfe 195 ldr r4, [r0] 196 cmp r2, r4 197 bne poll_mailbox_smp_go 198 199 /* debug message */ 200 mov r4, #'C' 201 str r4, [r3] 202 mov r4, #'P' 203 str r4, [r3] 204 mov r4, #'U' 205 str r4, [r3] 206 mov r4, #'1' 207 str r4, [r3] 208 mov r4, #'\r' 209 str r4, [r3] 210 mov r4, #'\n' 211 str r4, [r3] 212 213 /* SMP GO signal confirmed, release cpuN */ 214 ldr pc, [r1] 215 216mailbox_insn_end: 217 /* should never reach */ 218 b . 219 220#endif 221