xref: /openbmc/u-boot/drivers/ram/aspeed/sdram_ast2600.c (revision d8ebf49e584e4e134bd8d1c445ef2da276a00e1a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  *
5  */
6 
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <ram.h>
12 #include <regmap.h>
13 #include <reset.h>
14 #include <asm/io.h>
15 #include <asm/arch/scu_ast2600.h>
16 #include <asm/arch/sdram_ast2600.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <dt-bindings/clock/ast2600-clock.h>
20 #include "sdram_phy_ast2600.h"
21 
22 /* in order to speed up DRAM init time, write pre-defined values to registers
23  * directly */
24 #define AST2600_SDRAMMC_MANUAL_CLK
25 
26 /* register offset */
27 #define AST_SCU_FPGA_STATUS	0x004
28 #define AST_SCU_HANDSHAKE	0x100
29 #define AST_SCU_MPLL		0x220
30 #define AST_SCU_MPLL_EXT	0x224
31 #define AST_SCU_FPGA_PLL	0x400
32 #define AST_SCU_HW_STRAP	0x500
33 
34 
35 /* bit-field of AST_SCU_HW_STRAP */
36 #define SCU_HWSTRAP_VGAMEM_SHIFT	13
37 #define SCU_HWSTRAP_VGAMEM_MASK		GENMASK(14, 13)
38 #define SCU_HWSTRAP_DDR3		BIT(25)
39 
40 
41 /* bit-field of AST_SCU_HANDSHAKE */
42 #define SCU_SDRAM_INIT_READY_MASK	BIT(6)
43 #define SCU_SDRAM_INIT_BY_SOC_MASK	BIT(7)
44 
45 /* bit-field of AST_SCU_MPLL */
46 #define SCU_MPLL_RESET			BIT(25)
47 #define SCU_MPLL_BYPASS			BIT(24)
48 #define SCU_MPLL_TURN_OFF		BIT(23)
49 #define SCU_MPLL_FREQ_MASK		GENMASK(22, 0)
50 
51 #define SCU_MPLL_FREQ_400M		0x0008405F
52 #define SCU_MPLL_EXT_400M		0x00000031
53 //#define SCU_MPLL_FREQ_400M		0x0038007F
54 //#define SCU_MPLL_EXT_400M		0x0000003F
55 #define SCU_MPLL_FREQ_200M		0x0078007F
56 #define SCU_MPLL_EXT_200M		0x0000003F
57 
58 /* MPLL configuration */
59 #if defined(CONFIG_ASPEED_DDR4_800)
60 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_200M
61 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_200M
62 #elif defined(CONFIG_ASPEED_DDR4_1600)
63 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_400M
64 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_400M
65 #else
66 #error "undefined DDR4 target rate\n"
67 #endif
68 
69 /* AC timing and SDRAM mode registers */
70 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
71 /* mode register settings for FPGA are fixed */
72 #define DDR4_MR01_MODE		0x03010100
73 #define DDR4_MR23_MODE		0x00000000
74 #define DDR4_MR45_MODE		0x04C00000
75 #define DDR4_MR6_MODE		0x00000050
76 #define DDR4_TRFC_FPGA		0x17263434
77 
78 /* FPGA need for an additional initialization procedure: search read window */
79 #define SEARCH_RDWIN_ANCHOR_0   (CONFIG_SYS_SDRAM_BASE + 0x0000)
80 #define SEARCH_RDWIN_ANCHOR_1   (CONFIG_SYS_SDRAM_BASE + 0x0004)
81 #define SEARCH_RDWIN_PTRN_0     0x12345678
82 #define SEARCH_RDWIN_PTRN_1     0xaabbccdd
83 #define SEARCH_RDWIN_PTRN_SUM   0xbcf02355
84 #else
85 /* mode register setting for real chip are derived from the model GDDR4-1600 */
86 #define DDR4_MR01_MODE		0x03010510
87 #define DDR4_MR23_MODE		0x00000000
88 #define DDR4_MR45_MODE		0x04000000
89 #define DDR4_MR6_MODE           0x00000400
90 #define DDR4_TRFC_1600		0x467299f1
91 #define DDR4_TRFC_800		0x23394c78
92 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                           \
93 	  defined(CONFIG_ASPEED_PALLADIUM)" */
94 
95 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
96 #define DDR4_TRFC			DDR4_TRFC_FPGA
97 #else
98 /* real chip setting */
99 #if defined(CONFIG_ASPEED_DDR4_1600)
100 #define DDR4_TRFC			DDR4_TRFC_1600
101 #define DDR4_PHY_TRAIN_TRFC		0xc30
102 #elif defined(CONFIG_ASPEED_DDR4_800)
103 #define DDR4_TRFC			DDR4_TRFC_800
104 #define DDR4_PHY_TRAIN_TRFC		0x618
105 #else
106 #error "undefined tRFC setting"
107 #endif	/* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
108 #endif  /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                          \
109 	   defined(CONFIG_ASPEED_PALLADIUM)" */
110 
111 /* supported SDRAM size */
112 #define SDRAM_SIZE_1KB		(1024U)
113 #define SDRAM_SIZE_1MB		(SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
114 #define SDRAM_MIN_SIZE		(256 * SDRAM_SIZE_1MB)
115 #define SDRAM_MAX_SIZE		(2048 * SDRAM_SIZE_1MB)
116 
117 
118 DECLARE_GLOBAL_DATA_PTR;
119 
120 /*
121  * Bandwidth configuration parameters for different SDRAM requests.
122  * These are hardcoded settings taken from Aspeed SDK.
123  */
124 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
125 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200,
126                                       0x00000140};
127 
128 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888,
129                                             0x88888888};
130 #else
131 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304,
132                                       0x00001240};
133 
134 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444,
135                                             0x44444444};
136 #endif
137 
138 struct dram_info {
139 	struct ram_info info;
140 	struct clk ddr_clk;
141 	struct ast2600_sdrammc_regs *regs;
142 	void __iomem *scu;
143 	struct ast2600_ddr_phy *phy;
144 	void __iomem *phy_setting;
145 	void __iomem *phy_status;
146 	ulong clock_rate;
147 };
148 
149 static void ast2600_sdramphy_kick_training(struct dram_info *info)
150 {
151 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
152         struct ast2600_sdrammc_regs *regs = info->regs;
153         u32 volatile data;
154 
155         writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
156 	udelay(5);
157         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
158 	udelay(1000);
159 
160 	while (1) {
161 		data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
162 		if (~data) {
163 			break;
164 		}
165 	}
166 
167 #if 0
168 	while (1) {
169 		data = readl(0x1e6e0400) & BIT(1);
170 		if (data) {
171 			break;
172 		}
173 	}
174 #endif
175 #endif
176 }
177 
178 /**
179  * @brief	load DDR-PHY configurations table to the PHY registers
180  * @param[in]	p_tbl - pointer to the configuration table
181  * @param[in]	info - pointer to the DRAM info struct
182  *
183  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
184  * system: one is in the SDRAM MC (memory controller) which is used in run
185  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
186  * training.  To make these two configurations align, we overwrite the DDR-PHY
187  * setting by the MC setting before DDR-PHY training.
188 */
189 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
190 {
191 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
192 	u32 reg_base = (u32)info->phy_setting;
193 	u32 addr = p_tbl[0];
194         u32 data;
195         int i = 1;
196 
197         debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base,
198                addr);
199 
200         /* load PHY configuration table into PHY-setting registers */
201         while (1) {
202                 if (addr < reg_base) {
203                         debug("invalid DDR-PHY addr: 0x%08x\n", addr);
204                         break;
205                 }
206                 data = p_tbl[i++];
207 
208                 if (DDR_PHY_TBL_END == data) {
209                         break;
210                 } else if (DDR_PHY_TBL_CHG_ADDR == data) {
211                         addr = p_tbl[i++];
212                 } else {
213                         writel(data, addr);
214                         addr += 4;
215                 }
216         }
217 
218 	data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
219 	data |= DDR4_PHY_TRAIN_TRFC;
220 	writel(data, info->phy_setting + 0x84);
221 
222 #ifdef CONFIG_ASPEED_DDR4_800
223 
224 	debug("Overwrite DDR-PHY MRS by MCR config\n");
225 	/* MR0 and MR1 */
226 	data = readl(&info->regs->mr01_mode_setting);
227 	data =
228 	    ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16);
229 	writel(data, reg_base + 0x58);
230 	debug("[%08x] 0x%08x\n", reg_base + 0x58, data);
231 
232 	/* MR2 and MR3 */
233 	data = readl(&info->regs->mr23_mode_setting);
234 	writel(data, reg_base + 0x54);
235 	debug("[%08x] 0x%08x\n", reg_base + 0x54, data);
236 
237 	/* MR4 and MR5 */
238 	data = readl(&info->regs->mr45_mode_setting);
239 	writel(data, reg_base + 0x5c);
240 	debug("[%08x] 0x%08x\n", reg_base + 0x5c, data);
241 
242 	/* MR6 */
243 	data = readl(&info->regs->mr6_mode_setting);
244 	writel(data, reg_base + 0x60);
245 	debug("[%08x] 0x%08x\n", reg_base + 0x60, data);
246 #endif
247 #endif
248 }
249 
250 static void ast2600_sdramphy_show_status(struct dram_info *info)
251 {
252 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
253         u32 value, tmp;
254         u32 reg_base = (u32)info->phy_status;
255 
256 	debug("\nSDRAM PHY training report:\n");
257 	/* training status */
258         value = readl(reg_base + 0x00);
259 	debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
260         if (value & BIT(3)) {
261                 debug("\tinitial PVT calibration fail\n");
262         }
263         if (value & BIT(5)) {
264                 debug("\truntime calibration fail\n");
265         }
266 
267 	/* PU & PD */
268 	value = readl(reg_base + 0x30);
269 	debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
270         debug("  PU = 0x%02x\n", value & 0xff);
271         debug("  PD = 0x%02x\n", (value >> 16) & 0xff);
272 
273 	/* read eye window */
274         value = readl(reg_base + 0x68);
275 	debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
276 	debug("  rising edge of read data eye training pass window\n");
277 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
278 	debug("    B0:%d%%\n", tmp);
279 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
280         debug("    B1:%d%%\n", tmp);
281 
282 	value = readl(reg_base + 0xC8);
283 	debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
284 	debug("  falling edge of read data eye training pass window\n");
285 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
286 	debug("    B0:%d%%\n", tmp);
287 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
288         debug("    B1:%d%%\n", tmp);
289 
290         /* write eye window */
291         value = readl(reg_base + 0x7c);
292 	debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
293 	debug("  rising edge of write data eye training pass window\n");
294 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
295 	debug("    B0:%d%%\n", tmp);
296 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
297         debug("    B1:%d%%\n", tmp);
298 
299 	/* read Vref training result */
300         value = readl(reg_base + 0x88);
301 	debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
302         debug("  read Vref training result\n");
303 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
304 	debug("    B0:%d%%\n", tmp);
305 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
306         debug("    B1:%d%%\n", tmp);
307 
308         /* write Vref training result */
309         value = readl(reg_base + 0x90);
310 	debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
311 	tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127;
312         debug("  write Vref training result = %d%%\n", tmp);
313 
314         /* gate train */
315 	value = readl(reg_base + 0x50);
316 	debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
317 	debug("  gate training pass window\n");
318 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
319 	debug("    module 0: %d.%03d\n", (value >> 8) & 0xff, tmp);
320         tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255;
321 	debug("    module 1: %d.%03d\n", (value >> 24) & 0xff, tmp);
322 #endif
323 }
324 
325 #define MC_TEST_PATTERN_N 8
326 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
327     0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
328     0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253};
329 
330 #define DRAM_MapAdr	81000000
331 #define TIMEOUT_DRAM	5000000
332 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
333 {
334 	unsigned int data;
335 	unsigned int timeout = 0;
336 	struct ast2600_sdrammc_regs *regs = info->regs;
337 
338 	writel(0, &regs->ecc_test_ctrl);
339 	if (mode == 0) {
340 		writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl);
341 	} else {
342 		writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl);
343 	}
344 
345 	do {
346 		data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12);
347 
348 		if (data & BIT(13))
349 			return (0);
350 
351 		if (++timeout > TIMEOUT_DRAM) {
352 			printf("Timeout!!\n");
353 			writel(0, &regs->ecc_test_ctrl);
354 
355 			return (0);
356 		}
357 	} while (!data);
358 
359 	writel(0, &regs->ecc_test_ctrl);
360 
361 	return (1);
362 }
363 
364 int ast2600_sdrammc_cbr_test(struct dram_info *info)
365 {
366 	struct ast2600_sdrammc_regs *regs = info->regs;
367 	u32 i;
368 
369 	writel((DRAM_MapAdr | 0x7fffff), &regs->test_addr);
370 
371 	/* single */
372 	for (i=0; i<8; i++) {
373   		if(!ast2600_sdrammc_dg_test(info, i, 0))   return(0);
374 	}
375 
376 	/* burst */
377 	for (i=0; i<8; i++) {
378   		if(!ast2600_sdrammc_dg_test(info, i, i))   return(0);
379 	}
380 
381 	return(1);
382 }
383 
384 static int ast2600_sdrammc_test(struct dram_info *info)
385 {
386 	struct ast2600_sdrammc_regs *regs = info->regs;
387 
388 	u32 pass_cnt = 0;
389 	u32 fail_cnt = 0;
390 	u32 target_cnt = 2;
391 	u32 test_cnt = 0;
392 	u32 pattern;
393 	u32 i = 0;
394 	bool finish = false;
395 
396 	debug("sdram mc test:\n");
397 	while (finish == false) {
398 		pattern = as2600_sdrammc_test_pattern[i++];
399 		i = i % MC_TEST_PATTERN_N;
400 		debug("  pattern = %08X : ",pattern);
401 		writel(pattern, regs->test_init_val);
402 
403 		if (!ast2600_sdrammc_cbr_test(info)) {
404 			debug("fail\n");
405 			fail_cnt++;
406 		} else {
407 			debug("pass\n");
408 			pass_cnt++;
409 		}
410 
411 		if (++test_cnt == target_cnt) {
412 			finish = true;
413 		}
414 	}
415 	debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt,
416 	       target_cnt);
417 	return fail_cnt;
418 }
419 
420 /**
421  * scu500[14:13]
422  * 	2b'00: VGA memory size = 8MB * 2^((0+1) & 0x3) = 16MB
423  * 	2b'01: VGA memory size = 8MB * 2^((1+1) & 0x3) = 32MB
424  * 	2b'10: VGA memory size = 8MB * 2^((2+1) & 0x3) = 64MB
425  * 	2b'11: VGA memory size = 8MB * 2^((3+1) & 0x3) = 8MB
426  *
427  * mcr04[3:2]
428  * 	2b'00: VGA memory size = 8MB
429  * 	2b'01: VGA memory size = 16MB
430  * 	2b'10: VGA memory size = 32MB
431  * 	2b'11: VGA memory size = 64MB
432 */
433 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
434 {
435         u32 vga_hwconf;
436         size_t vga_mem_size_base = 8 * 1024 * 1024;
437 
438 	vga_hwconf =
439 	    (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >>
440 	    SCU_HWSTRAP_VGAMEM_SHIFT;
441 
442 	vga_hwconf = (vga_hwconf + 1) & 0x3;
443 
444 	clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK,
445 			((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) &
446 			 SDRAM_CONF_VGA_SIZE_MASK));
447 
448 	return vga_mem_size_base << vga_hwconf;
449 }
450 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
451 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
452 {
453         u32 data;
454         u32 scu_base = (u32)info->scu;
455 
456         writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
457 
458         do {
459                 data = readl(scu_base + AST_SCU_FPGA_STATUS);
460         } while (!(data & 0x100));
461 
462         writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
463 }
464 
465 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
466 {
467         u32 pll, pll_min, pll_max, dat1, offset;
468         u32 win = 0x03, gwin = 0, gwinsize = 0;
469         u32 phy_setting = (u32)info->phy_setting;
470 
471 #ifdef CONFIG_ASPEED_PALLADIUM
472 	writel(0xc, phy_setting + 0x0000);
473 	return (1);
474 #endif
475         writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
476         writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
477 
478         while (gwin == 0) {
479                 while (!(win & 0x80)) {
480                         debug("Window = 0x%X\n", win);
481                         writel(win, phy_setting + 0x0000);
482 
483                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
484                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
485                         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
486                                 ast2600_sdrammc_fpga_set_pll(info);
487                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
488                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
489                         }
490 
491                         pll_min = 0xfff;
492                         pll_max = 0x0;
493                         pll = 0;
494                         while (pll_max > 0 || pll < 256) {
495                                 ast2600_sdrammc_fpga_set_pll(info);
496                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
497                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
498                                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
499                                         if (pll_min > pll) {
500                                                 pll_min = pll;
501                                         }
502                                         if (pll_max < pll) {
503                                                 pll_max = pll;
504                                         }
505                                         debug("%3d_(%3d:%3d)\n", pll, pll_min,
506                                                pll_max);
507                                 } else if (pll_max > 0) {
508                                         pll_min = pll_max - pll_min;
509                                         if (gwinsize < pll_min) {
510                                                 gwin = win;
511                                                 gwinsize = pll_min;
512                                         }
513                                         break;
514                                 }
515                                 pll += 1;
516                         }
517 
518                         if (gwin != 0 && pll_max == 0) {
519                                 break;
520                         }
521                         win = win << 1;
522                 }
523                 if (gwin == 0) {
524                         win = 0x7;
525                 }
526         }
527         debug("Set PLL Read Gating Window = %x\n", gwin);
528         writel(gwin, phy_setting + 0x0000);
529 
530         debug("PLL Read Window training\n");
531         pll_min = 0xfff;
532         pll_max = 0x0;
533 
534         debug("Search Window Start\n");
535         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
536         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
537         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
538                 ast2600_sdrammc_fpga_set_pll(info);
539                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
540                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
541         }
542 
543         debug("Search Window Margin\n");
544         pll = 0;
545         while (pll_max > 0 || pll < 256) {
546                 ast2600_sdrammc_fpga_set_pll(info);
547                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
548                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
549                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
550                         if (pll_min > pll) {
551                                 pll_min = pll;
552                         }
553                         if (pll_max < pll) {
554                                 pll_max = pll;
555                         }
556                         debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
557                 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
558                         break;
559                 } else if (pll_max > 0) {
560                         pll_min = 0xfff;
561                         pll_max = 0x0;
562                 }
563                 pll += 1;
564         }
565         if (pll_min < pll_max) {
566                 debug("PLL Read window = %d\n", (pll_max - pll_min));
567                 offset = (pll_max - pll_min) >> 1;
568                 pll_min = 0xfff;
569                 pll = 0;
570                 while (pll < (pll_min + offset)) {
571                         ast2600_sdrammc_fpga_set_pll(info);
572                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
573                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
574                         if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
575                                 if (pll_min > pll) {
576                                         pll_min = pll;
577                                 }
578                                 debug("%d\n", pll);
579                         } else {
580                                 pll_min = 0xfff;
581                                 pll_max = 0x0;
582                         }
583                         pll += 1;
584                 }
585                 return (1);
586         } else {
587                 debug("PLL Read window training fail\n");
588                 return (0);
589         }
590 }
591 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                           \
592 	  defined(CONFIG_ASPEED_PALLADIUM)" */
593 
594 /*
595  * Find out RAM size and save it in dram_info
596  *
597  * The procedure is taken from Aspeed SDK
598  */
599 static void ast2600_sdrammc_calc_size(struct dram_info *info)
600 {
601 	/* The controller supports 256/512/1024/2048 MB ram */
602 	size_t ram_size = SDRAM_MIN_SIZE;
603 	const int write_test_offset = 0x100000;
604 	u32 test_pattern = 0xdeadbeef;
605 	u32 cap_param = SDRAM_CONF_CAP_2048M;
606 	u32 refresh_timing_param = DDR4_TRFC;
607 	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
608 
609 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
610 	     ram_size >>= 1) {
611 		writel(test_pattern, write_addr_base + (ram_size >> 1));
612 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
613 	}
614 
615 	/* One last write to overwrite all wrapped values */
616 	writel(test_pattern, write_addr_base);
617 
618 	/* Reset the pattern and see which value was really written */
619 	test_pattern = 0xdeadbeef;
620 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
621 	     ram_size >>= 1) {
622 		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
623 			break;
624 
625 		--cap_param;
626 		refresh_timing_param >>= 8;
627 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
628 	}
629 
630 	clrsetbits_le32(&info->regs->ac_timing[1],
631 			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
632 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
633 			 << SDRAM_AC_TRFC_SHIFT));
634 
635 	info->info.base = CONFIG_SYS_SDRAM_BASE;
636 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
637 
638 	clrsetbits_le32(
639 	    &info->regs->config, SDRAM_CONF_CAP_MASK,
640 	    ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK));
641 }
642 
643 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
644 {
645         const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
646                                MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
647                                MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
648                                (0x1 << MCR34_ODT_EXT_SHIFT);
649 
650         /* init SDRAM-PHY only on real chip */
651 	ast2600_sdramphy_init(ast2600_sdramphy_config, info);
652         writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
653                &info->regs->power_ctrl);
654 	udelay(5);
655 	ast2600_sdramphy_kick_training(info);
656 	udelay(500);
657         writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
658 
659         writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
660         writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
661         writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
662         writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
663         writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
664         writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
665         writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
666                &info->regs->mode_setting_control);
667 
668 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
669 
670         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
671                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT),
672                &info->regs->refresh_timing);
673 #else
674         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
675                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
676                &info->regs->refresh_timing);
677 #endif
678 
679         /* wait self-refresh idle */
680         while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
681                 ;
682 
683 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
684         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
685                    SDRAM_REFRESH_ZQCS_EN |
686                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) |
687                    (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
688                &info->regs->refresh_timing);
689 #else
690         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
691                    SDRAM_REFRESH_ZQCS_EN |
692                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
693                    (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
694                &info->regs->refresh_timing);
695 #endif
696 
697         writel(power_ctrl, &info->regs->power_ctrl);
698 	udelay(500);
699 
700 #if defined(CONFIG_FPGA_ASPEED)
701         /* toggle Vref training */
702         setbits_le32(&info->regs->mr6_mode_setting, 0x80);
703         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
704                &info->regs->mode_setting_control);
705         clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
706         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
707                &info->regs->mode_setting_control);
708 #endif
709 	return 0;
710 }
711 
712 static void ast2600_sdrammc_unlock(struct dram_info *info)
713 {
714 	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
715 	while (!readl(&info->regs->protection_key))
716 		;
717 }
718 
719 static void ast2600_sdrammc_lock(struct dram_info *info)
720 {
721 	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
722 	while (readl(&info->regs->protection_key))
723 		;
724 }
725 
726 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
727 {
728 	int i;
729 
730         writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
731         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
732         writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
733                &regs->arbitration_ctrl);
734         writel(0xFFBBFFF4, &regs->req_limit_mask);
735 
736 	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
737                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
738 
739         writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
740 
741         /* FIXME: the sample code does NOT match the datasheet */
742         writel(0x07FFFFFF, &regs->ecc_range_ctrl);
743 
744         writel(0, &regs->ecc_test_ctrl);
745         writel(0, &regs->test_addr);
746         writel(0, &regs->test_fail_dq_bit);
747         writel(0, &regs->test_init_val);
748 
749         writel(0xFFFFFFFF, &regs->req_input_ctrl);
750         writel(0, &regs->req_high_pri_ctrl);
751 
752         udelay(600);
753 
754 #ifdef CONFIG_ASPEED_DDR4_DUALX8
755 	writel(0x37, &regs->config);
756 #else
757 	writel(0x17, &regs->config);
758 #endif
759 
760 	/* load controller setting */
761 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
762 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
763 
764 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
765 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
766 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
767 	writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
768 }
769 
770 static int ast2600_sdrammc_probe(struct udevice *dev)
771 {
772 	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
773 	struct ast2600_sdrammc_regs *regs = priv->regs;
774 	struct udevice *clk_dev;
775 	int ret;
776 	volatile uint32_t reg;
777 
778 	/* find SCU base address from clock device */
779 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
780                                           &clk_dev);
781 	if (ret) {
782 		debug("clock device not defined\n");
783 		return ret;
784 	}
785 
786 	priv->scu = devfdt_get_addr_ptr(clk_dev);
787 	if (IS_ERR(priv->scu)) {
788 		debug("%s(): can't get SCU\n", __func__);
789 		return PTR_ERR(priv->scu);
790 	}
791 
792 	if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) {
793 		debug("%s(): DDR SDRAM had been initialized\n", __func__);
794 		ast2600_sdrammc_calc_size(priv);
795 		return 0;
796 	}
797 
798 #ifdef AST2600_SDRAMMC_MANUAL_CLK
799 	reg = readl(priv->scu + AST_SCU_MPLL);
800 	reg &= ~(BIT(24) | GENMASK(22, 0));
801 	reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG);
802 	writel(reg, priv->scu + AST_SCU_MPLL);
803         writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
804 	udelay(100);
805 	reg &= ~(BIT(25) | BIT(23));
806 	writel(reg, priv->scu + AST_SCU_MPLL);
807 	while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)));
808 #else
809 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
810 	if (ret) {
811 		debug("DDR:No CLK\n");
812 		return ret;
813 	}
814 	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
815 #endif
816 
817 #if 0
818 	/* FIXME: enable the following code if reset-driver is ready */
819 	struct reset_ctl reset_ctl;
820 	ret = reset_get_by_index(dev, 0, &reset_ctl);
821 	if (ret) {
822 		debug("%s(): Failed to get reset signal\n", __func__);
823 		return ret;
824 	}
825 
826 	ret = reset_assert(&reset_ctl);
827 	if (ret) {
828 		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
829 		return ret;
830 	}
831 #endif
832 
833 	ast2600_sdrammc_unlock(priv);
834 	ast2600_sdrammc_common_init(regs);
835 
836 	if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) {
837 		debug("Unsupported SDRAM type: DDR3\n");
838 		return -EINVAL;
839 	} else {
840 		ast2600_sdrammc_init_ddr4(priv);
841 	}
842 
843 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
844         ast2600_sdrammc_search_read_window(priv);
845 #else
846 	/* make sure DDR-PHY is ready before access */
847 	do {
848 		reg = readl(priv->phy_status) & BIT(1);
849 	} while(reg == 0);
850 #endif
851 
852 	ast2600_sdramphy_show_status(priv);
853 	ast2600_sdrammc_calc_size(priv);
854 
855         if (0 != ast2600_sdrammc_test(priv)) {
856 		printf("%s: DDR4 init fail\n", __func__);
857 		return -EINVAL;
858 	}
859 
860 	writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK,
861 	       priv->scu + AST_SCU_HANDSHAKE);
862 
863 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
864 	ast2600_sdrammc_lock(priv);
865 	return 0;
866 }
867 
868 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
869 {
870 	struct dram_info *priv = dev_get_priv(dev);
871 
872 	priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
873 	priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
874 	priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
875 
876 	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
877 					  "clock-frequency", 0);
878 	if (!priv->clock_rate) {
879 		debug("DDR Clock Rate not defined\n");
880 		return -EINVAL;
881 	}
882 
883 	return 0;
884 }
885 
886 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
887 {
888 	struct dram_info *priv = dev_get_priv(dev);
889 
890 	*info = priv->info;
891 
892 	return 0;
893 }
894 
895 static struct ram_ops ast2600_sdrammc_ops = {
896 	.get_info = ast2600_sdrammc_get_info,
897 };
898 
899 static const struct udevice_id ast2600_sdrammc_ids[] = {
900 	{ .compatible = "aspeed,ast2600-sdrammc" },
901 	{ }
902 };
903 
904 U_BOOT_DRIVER(sdrammc_ast2600) = {
905 	.name = "aspeed_ast2600_sdrammc",
906 	.id = UCLASS_RAM,
907 	.of_match = ast2600_sdrammc_ids,
908 	.ops = &ast2600_sdrammc_ops,
909 	.ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
910 	.probe = ast2600_sdrammc_probe,
911 	.priv_auto_alloc_size = sizeof(struct dram_info),
912 };
913