xref: /openbmc/u-boot/arch/arm/mach-aspeed/ast2600/platform.S (revision 001f2e2f1d22848639577834c39e070dfdff0152)
1/*
2 *  This program is distributed in the hope that it will be useful,
3 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
4 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5 *  GNU General Public License for more details.
6 *
7 *  You should have received a copy of the GNU General Public License
8 *  along with this program; if not, write to the Free Software
9 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
10 */
11/*
12 * Board specific setup info
13 *
14 ******************************************************************************
15 * ASPEED Technology Inc.
16 *
17 * Version     : 2
18 * Release date: 2019.02.19
19 *
20 * Priority of fix item:
21 * [P1] = critical
22 * [P2] = nice to have
23 * [P3] = minor
24 *
25 * Change List :
26 * V0 |2018.03.28 : 1.[P1] Initial release for simulation
27 *
28 * Optional define variable
29 *
30 ******************************************************************************
31 */
32
33#include <config.h>
34#include <version.h>
35#include <asm/secure.h>
36#include <asm/armv7.h>
37#include <linux/linkage.h>
38
39/*
40 *       SMP mailbox
41 * +----------------------+
42 * |                      |
43 * | mailbox insn. for    |
44 * | cpuN polling SMP go  |
45 * |                      |
46 * +----------------------+ 0xC
47 * | mailbox ready signal |
48 * +----------------------+ 0x8
49 * | cpuN GO signal       |
50 * +----------------------+ 0x4
51 * | cpuN entrypoint      |
52 * +----------------------+ AST_SMP_MAILBOX_BASE
53 */
54
55#define AST_SMP_MAILBOX_BASE            0x1E6E2180
56#define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
57#define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
58#define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
59#define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
60
61/* AST2600 HW registers */
62#define AST_SCU_BASE            0x1E6E2000
63#define AST_SCU_PROT_KEY1       (AST_SCU_BASE)
64#define AST_SCU_PROT_KEY2       (AST_SCU_BASE + 0x010)
65#define AST_SCU_REV_ID          (AST_SCU_BASE + 0x014)
66#define AST_SCU_HW_STRAP1       (AST_SCU_BASE + 0x500)
67
68#define AST_FMC_BASE            0x1E620000
69#define AST_FMC_WDT1_CTRL_MODE  (AST_FMC_BASE + 0x060)
70#define AST_FMC_WDT2_CTRL_MODE  (AST_FMC_BASE + 0x064)
71
72/* Revision ID */
73#define REV_ID_AST2600A0    0x05000303
74
75ENTRY(ast_bootmode)
76    ldr     r1, =AST_SCU_HW_STRAP1
77    ldr     r0, [r1]
78    tst     r0, #0x4
79    moveq   r0, #0x0            @; AST_BOOTMODE_SPI
80    movne   r0, #0x1            @; AST_BOOTMODE_EMMC
81    mov     pc, lr
82ENDPROC(ast_bootmode)
83
84.macro timer_init
85#ifdef CONFIG_FPGA_ASPEED
86    movw    r0, #0x7840
87    movt    r0, #0x17D
88#else
89    ldr     r0, =AST_SCU_REV_ID
90    ldr     r0, [r0]
91
92    ldr     r1, =REV_ID_AST2600A0
93    cmp     r0, r1
94
95    movweq  r0, #0x0800
96    movteq  r0, #0x2FAF         @; 800MHz for A0
97    movwne  r0, #0x8C00
98    movtne  r0, #0x4786         @; 1.2GHz for A1
99#endif
100    /* write CNTFRQ */
101    mcr     p15, 0, r0, c14, c0, 0
102.endm
103
104
105.globl lowlevel_init
106
107lowlevel_init:
108#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
109    mov   pc, lr
110#else
111    /* setup timer frequency for ARM generic timer */
112    timer_init
113
114    /* set ACTLR.SMP to enable cache use */
115    mrc   p15, 0, r0, c1, c0, 1
116    orr   r0, r0, #0x40
117    mcr   p15, 0, r0, c1, c0, 1
118
119    /*
120     * we treat cpu0 as the primary core and
121     * put secondary core (cpuN) to sleep
122     */
123    mrc   p15, 0, r0, c0, c0, 5             @; Read CPU ID register
124    ands  r0, r0, #0xFF                     @; Mask off, leaving the CPU ID field
125    ldr   r2, =0xABBAAB00
126    orr   r2, r2, r0
127
128    beq   do_primary_core_setup
129
130    /* hold cpuN until mailbox is ready */
131poll_mailbox_ready:
132    wfe
133    ldr   r0, =AST_SMP_MBOX_FIELD_READY
134    ldr   r0, [r0]
135    ldr   r1, =0xBABECAFE
136    cmp   r1, r0
137    bne   poll_mailbox_ready
138
139    /* parameters for relocated SMP go polling insn. */
140    ldr   r0, =AST_SMP_MBOX_FIELD_GOSIGN
141    ldr   r1, =AST_SMP_MBOX_FIELD_ENTRY
142
143    /* no return */
144    ldr   pc, =AST_SMP_MBOX_FIELD_POLLINSN
145
146do_primary_core_setup:
147    /* unlock SCU */
148    ldr   r0, =0x1688A8A8                   @; magic key to unlock SCU
149    ldr   r1, =AST_SCU_PROT_KEY1
150    str   r0, [r1]
151    ldr   r1, =AST_SCU_PROT_KEY2
152    str   r0, [r1]
153
154    /* disable FMC WDT for SPI address mode detection */
155    mov   r0, #0
156    ldr   r1, =AST_FMC_WDT1_CTRL_MODE
157    str   r0, [r1]
158    ldr   r1, =AST_FMC_WDT2_CTRL_MODE
159    str   r0, [r1]
160
161    /* relocate mailbox insn. for cpuN polling SMP go signal */
162    adrl  r0, mailbox_insn
163    adrl  r1, mailbox_insn_end
164
165    ldr   r2, =#AST_SMP_MBOX_FIELD_POLLINSN
166
167relocate_mailbox_insn:
168    ldr   r3, [r0], #0x4
169    str   r3, [r2], #0x4
170    cmp   r0, r1
171    bne   relocate_mailbox_insn
172
173    /* notify cpuN mailbox is ready */
174    ldr   r0, =AST_SMP_MBOX_FIELD_READY
175    ldr   r1, =0xBABECAFE
176    str   r1, [r0]
177    sev
178
179    /* back to arch calling code */
180    mov   pc, lr
181
182/*
183 * insn. inside mailbox to poll SMP go signal.
184 *
185 * Note that as this code will be relocated, any
186 * pc-relative assembly should NOT be used.
187 */
188mailbox_insn:
189    /*
190     * r0 ~ r3 are parameters:
191     *   r0 = AST_SMP_MBOX_FIELD_GOSIGN
192     *   r1 = AST_SMP_MBOX_FIELD_ENTRY
193     *   r2 = per-cpu go sign value
194     *   r3 = no used now
195     */
196poll_mailbox_smp_go:
197    wfe
198    ldr   r4, [r0]
199    cmp   r2, r4
200    bne   poll_mailbox_smp_go
201
202    /* SMP GO signal confirmed, release cpuN */
203    ldr   pc, [r1]
204
205mailbox_insn_end:
206    /* should never reach */
207    b .
208
209#endif
210