xref: /openbmc/u-boot/drivers/ram/aspeed/sdram_ast2600.c (revision 001f2e2f1d22848639577834c39e070dfdff0152)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  *
5  */
6 
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <ram.h>
12 #include <regmap.h>
13 #include <reset.h>
14 #include <asm/io.h>
15 #include <asm/arch/scu_ast2600.h>
16 #include <asm/arch/sdram_ast2600.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <dt-bindings/clock/ast2600-clock.h>
20 #include "sdram_phy_ast2600.h"
21 
22 /* in order to speed up DRAM init time, write pre-defined values to registers
23  * directly */
24 #define AST2600_SDRAMMC_MANUAL_CLK
25 
26 /* register offset */
27 #define AST_SCU_FPGA_STATUS	0x004
28 #define AST_SCU_HANDSHAKE	0x100
29 #define AST_SCU_MPLL		0x220
30 #define AST_SCU_MPLL_EXT	0x224
31 #define AST_SCU_FPGA_PLL	0x400
32 #define AST_SCU_HW_STRAP	0x500
33 
34 
35 /* bit-field of AST_SCU_HW_STRAP */
36 #define SCU_HWSTRAP_VGAMEM_SHIFT	13
37 #define SCU_HWSTRAP_VGAMEM_MASK		GENMASK(14, 13)
38 #define SCU_HWSTRAP_DDR3		BIT(25)
39 
40 
41 /* bit-field of AST_SCU_HANDSHAKE */
42 #define SCU_SDRAM_INIT_READY_MASK	BIT(6)
43 #define SCU_SDRAM_INIT_BY_SOC_MASK	BIT(7)
44 
45 /* bit-field of AST_SCU_MPLL */
46 #define SCU_MPLL_RESET			BIT(25)
47 #define SCU_MPLL_BYPASS			BIT(24)
48 #define SCU_MPLL_TURN_OFF		BIT(23)
49 #define SCU_MPLL_FREQ_MASK		GENMASK(22, 0)
50 
51 #define SCU_MPLL_FREQ_400M		0x0008405F
52 #define SCU_MPLL_EXT_400M		0x00000031
53 //#define SCU_MPLL_FREQ_400M		0x0038007F
54 //#define SCU_MPLL_EXT_400M		0x0000003F
55 #define SCU_MPLL_FREQ_200M		0x0078007F
56 #define SCU_MPLL_EXT_200M		0x0000003F
57 
58 /* MPLL configuration */
59 #if defined(CONFIG_ASPEED_DDR4_800)
60 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_200M
61 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_200M
62 #elif defined(CONFIG_ASPEED_DDR4_1600)
63 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_400M
64 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_400M
65 #else
66 #error "undefined DDR4 target rate\n"
67 #endif
68 
69 /* AC timing and SDRAM mode registers */
70 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
71 /* mode register settings for FPGA are fixed */
72 #define DDR4_MR01_MODE		0x03010100
73 #define DDR4_MR23_MODE		0x00000000
74 #define DDR4_MR45_MODE		0x04C00000
75 #define DDR4_MR6_MODE		0x00000050
76 #define DDR4_TRFC_FPGA		0x17263434
77 
78 /* FPGA need for an additional initialization procedure: search read window */
79 #define SEARCH_RDWIN_ANCHOR_0   (CONFIG_SYS_SDRAM_BASE + 0x0000)
80 #define SEARCH_RDWIN_ANCHOR_1   (CONFIG_SYS_SDRAM_BASE + 0x0004)
81 #define SEARCH_RDWIN_PTRN_0     0x12345678
82 #define SEARCH_RDWIN_PTRN_1     0xaabbccdd
83 #define SEARCH_RDWIN_PTRN_SUM   0xbcf02355
84 #else
85 /* mode register setting for real chip are derived from the model GDDR4-1600 */
86 #define DDR4_MR01_MODE		0x03010510
87 #define DDR4_MR23_MODE		0x00000000
88 #define DDR4_MR45_MODE		0x04000000
89 #define DDR4_MR6_MODE           0x00000400
90 #define DDR4_TRFC_1600		0x467299f1
91 #define DDR4_TRFC_800		0x23394c78
92 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                           \
93 	  defined(CONFIG_ASPEED_PALLADIUM)" */
94 
95 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
96 #define DDR4_TRFC			DDR4_TRFC_FPGA
97 #else
98 /* real chip setting */
99 #if defined(CONFIG_ASPEED_DDR4_1600)
100 #define DDR4_TRFC			DDR4_TRFC_1600
101 #define DDR4_PHY_TRAIN_TRFC		0xc30
102 #elif defined(CONFIG_ASPEED_DDR4_800)
103 #define DDR4_TRFC			DDR4_TRFC_800
104 #define DDR4_PHY_TRAIN_TRFC		0x618
105 #else
106 #error "undefined tRFC setting"
107 #endif	/* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
108 #endif  /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                          \
109 	   defined(CONFIG_ASPEED_PALLADIUM)" */
110 
111 /* supported SDRAM size */
112 #define SDRAM_SIZE_1KB		(1024U)
113 #define SDRAM_SIZE_1MB		(SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
114 #define SDRAM_MIN_SIZE		(256 * SDRAM_SIZE_1MB)
115 #define SDRAM_MAX_SIZE		(2048 * SDRAM_SIZE_1MB)
116 
117 
118 DECLARE_GLOBAL_DATA_PTR;
119 
120 /*
121  * Bandwidth configuration parameters for different SDRAM requests.
122  * These are hardcoded settings taken from Aspeed SDK.
123  */
124 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
125 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200,
126                                       0x00000140};
127 
128 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888,
129                                             0x88888888};
130 #else
131 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304,
132                                       0x00001240};
133 
134 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444,
135                                             0x44444444};
136 #endif
137 
138 struct dram_info {
139 	struct ram_info info;
140 	struct clk ddr_clk;
141 	struct ast2600_sdrammc_regs *regs;
142 	void __iomem *scu;
143 	struct ast2600_ddr_phy *phy;
144 	void __iomem *phy_setting;
145 	void __iomem *phy_status;
146 	ulong clock_rate;
147 };
148 
149 static void ast2600_sdramphy_kick_training(struct dram_info *info)
150 {
151 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
152         struct ast2600_sdrammc_regs *regs = info->regs;
153         u32 volatile data;
154 
155         writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
156 	udelay(5);
157         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
158 	udelay(1000);
159 
160 	while (1) {
161 		data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
162 		if (~data) {
163 			break;
164 		}
165 	}
166 
167 #if 0
168 	while (1) {
169 		data = readl(0x1e6e0400) & BIT(1);
170 		if (data) {
171 			break;
172 		}
173 	}
174 #endif
175 #endif
176 }
177 
178 /**
179  * @brief	load DDR-PHY configurations table to the PHY registers
180  * @param[in]	p_tbl - pointer to the configuration table
181  * @param[in]	info - pointer to the DRAM info struct
182  *
183  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
184  * system: one is in the SDRAM MC (memory controller) which is used in run
185  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
186  * training.  To make these two configurations align, we overwrite the DDR-PHY
187  * setting by the MC setting before DDR-PHY training.
188 */
189 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
190 {
191 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
192 	u32 reg_base = (u32)info->phy_setting;
193 	u32 addr = p_tbl[0];
194         u32 data;
195         int i = 1;
196 
197         debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base,
198                addr);
199 
200         /* load PHY configuration table into PHY-setting registers */
201         while (1) {
202                 if (addr < reg_base) {
203                         debug("invalid DDR-PHY addr: 0x%08x\n", addr);
204                         break;
205                 }
206                 data = p_tbl[i++];
207 
208                 if (DDR_PHY_TBL_END == data) {
209                         break;
210                 } else if (DDR_PHY_TBL_CHG_ADDR == data) {
211                         addr = p_tbl[i++];
212                 } else {
213                         writel(data, addr);
214                         addr += 4;
215                 }
216         }
217 
218 	data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
219 	data |= DDR4_PHY_TRAIN_TRFC;
220 	writel(data, info->phy_setting + 0x84);
221 
222 #ifdef CONFIG_ASPEED_DDR4_800
223 
224 	debug("Overwrite DDR-PHY MRS by MCR config\n");
225 	/* MR0 and MR1 */
226 	data = readl(&info->regs->mr01_mode_setting);
227 	data =
228 	    ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16);
229 	writel(data, reg_base + 0x58);
230 	debug("[%08x] 0x%08x\n", reg_base + 0x58, data);
231 
232 	/* MR2 and MR3 */
233 	data = readl(&info->regs->mr23_mode_setting);
234 	writel(data, reg_base + 0x54);
235 	debug("[%08x] 0x%08x\n", reg_base + 0x54, data);
236 
237 	/* MR4 and MR5 */
238 	data = readl(&info->regs->mr45_mode_setting);
239 	writel(data, reg_base + 0x5c);
240 	debug("[%08x] 0x%08x\n", reg_base + 0x5c, data);
241 
242 	/* MR6 */
243 	data = readl(&info->regs->mr6_mode_setting);
244 	writel(data, reg_base + 0x60);
245 	debug("[%08x] 0x%08x\n", reg_base + 0x60, data);
246 #endif
247 #endif
248 }
249 
250 static void ast2600_sdramphy_show_status(struct dram_info *info)
251 {
252 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
253         u32 value, tmp;
254         u32 reg_base = (u32)info->phy_status;
255 
256 	debug("\nSDRAM PHY training report:\n");
257 	/* training status */
258         value = readl(reg_base + 0x00);
259 	debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
260         if (value & BIT(3)) {
261                 debug("\tinitial PVT calibration fail\n");
262         }
263         if (value & BIT(5)) {
264                 debug("\truntime calibration fail\n");
265         }
266 
267 	/* PU & PD */
268 	value = readl(reg_base + 0x30);
269 	debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
270         debug("  PU = 0x%02x\n", value & 0xff);
271         debug("  PD = 0x%02x\n", (value >> 16) & 0xff);
272 
273 	/* read eye window */
274         value = readl(reg_base + 0x68);
275 	debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
276 	debug("  rising edge of read data eye training pass window\n");
277 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
278 	debug("    B0:%d%%\n", tmp);
279 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
280         debug("    B1:%d%%\n", tmp);
281 
282 	value = readl(reg_base + 0xC8);
283 	debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
284 	debug("  falling edge of read data eye training pass window\n");
285 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
286 	debug("    B0:%d%%\n", tmp);
287 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
288         debug("    B1:%d%%\n", tmp);
289 
290         /* write eye window */
291         value = readl(reg_base + 0x7c);
292 	debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
293 	debug("  rising edge of write data eye training pass window\n");
294 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
295 	debug("    B0:%d%%\n", tmp);
296 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
297         debug("    B1:%d%%\n", tmp);
298 
299 	/* read Vref training result */
300         value = readl(reg_base + 0x88);
301 	debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
302         debug("  read Vref training result\n");
303 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
304 	debug("    B0:%d%%\n", tmp);
305 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
306         debug("    B1:%d%%\n", tmp);
307 
308         /* write Vref training result */
309         value = readl(reg_base + 0x90);
310 	debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
311 	tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127;
312         debug("  write Vref training result = %d%%\n", tmp);
313 
314         /* gate train */
315 	value = readl(reg_base + 0x50);
316 	debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
317 	debug("  gate training pass window\n");
318 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
319 	debug("    module 0: %d.%03d\n", (value >> 8) & 0xff, tmp);
320         tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255;
321 	debug("    module 1: %d.%03d\n", (value >> 24) & 0xff, tmp);
322 #endif
323 }
324 
325 #define MC_TEST_PATTERN_N 8
326 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
327     0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
328     0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253};
329 
330 #define DRAM_MapAdr	81000000
331 #define TIMEOUT_DRAM	5000000
332 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
333 {
334 	unsigned int data;
335 	unsigned int timeout = 0;
336 	struct ast2600_sdrammc_regs *regs = info->regs;
337 
338 	writel(0, &regs->ecc_test_ctrl);
339 	if (mode == 0) {
340 		writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl);
341 	} else {
342 		writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl);
343 	}
344 
345 	do {
346 		data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12);
347 
348 		if (data & BIT(13))
349 			return (0);
350 
351 		if (++timeout > TIMEOUT_DRAM) {
352 			printf("Timeout!!\n");
353 			writel(0, &regs->ecc_test_ctrl);
354 
355 			return (0);
356 		}
357 	} while (!data);
358 
359 	writel(0, &regs->ecc_test_ctrl);
360 
361 	return (1);
362 }
363 
364 int ast2600_sdrammc_cbr_test(struct dram_info *info)
365 {
366 	struct ast2600_sdrammc_regs *regs = info->regs;
367 	u32 i;
368 
369 	writel((DRAM_MapAdr | 0x7fffff), &regs->test_addr);
370 
371 	/* single */
372 	for (i=0; i<8; i++) {
373   		if(!ast2600_sdrammc_dg_test(info, i, 0))   return(0);
374 	}
375 
376 	/* burst */
377 	for (i=0; i<8; i++) {
378   		if(!ast2600_sdrammc_dg_test(info, i, i))   return(0);
379 	}
380 
381 	return(1);
382 }
383 
384 static int ast2600_sdrammc_test(struct dram_info *info)
385 {
386 	struct ast2600_sdrammc_regs *regs = info->regs;
387 
388 	u32 pass_cnt = 0;
389 	u32 fail_cnt = 0;
390 	u32 target_cnt = 2;
391 	u32 test_cnt = 0;
392 	u32 pattern;
393 	u32 i = 0;
394 	bool finish = false;
395 
396 	debug("sdram mc test:\n");
397 	while (finish == false) {
398 		pattern = as2600_sdrammc_test_pattern[i++];
399 		i = i % MC_TEST_PATTERN_N;
400 		debug("  pattern = %08X : ",pattern);
401 		writel(pattern, regs->test_init_val);
402 
403 		if (!ast2600_sdrammc_cbr_test(info)) {
404 			debug("fail\n");
405 			fail_cnt++;
406 		} else {
407 			debug("pass\n");
408 			pass_cnt++;
409 		}
410 
411 		if (++test_cnt == target_cnt) {
412 			finish = true;
413 		}
414 	}
415 	debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt,
416 	       target_cnt);
417 	return fail_cnt;
418 }
419 
420 /**
421  * scu500[14:13]
422  * 	2b'00: VGA memory size = 8MB
423  * 	2b'01: VGA memory size = 16MB
424  * 	2b'10: VGA memory size = 32MB
425  * 	2b'11: VGA memory size = 64MB
426  *
427  * mcr04[3:2]
428  * 	2b'00: VGA memory size = 8MB
429  * 	2b'01: VGA memory size = 16MB
430  * 	2b'10: VGA memory size = 32MB
431  * 	2b'11: VGA memory size = 64MB
432 */
433 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
434 {
435         u32 vga_hwconf;
436         size_t vga_mem_size_base = 8 * 1024 * 1024;
437 
438 	vga_hwconf =
439 	    (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >>
440 	    SCU_HWSTRAP_VGAMEM_SHIFT;
441 
442 	clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK,
443 			((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) &
444 			 SDRAM_CONF_VGA_SIZE_MASK));
445 
446 	return vga_mem_size_base << vga_hwconf;
447 }
448 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
449 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
450 {
451         u32 data;
452         u32 scu_base = (u32)info->scu;
453 
454         writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
455 
456         do {
457                 data = readl(scu_base + AST_SCU_FPGA_STATUS);
458         } while (!(data & 0x100));
459 
460         writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
461 }
462 
463 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
464 {
465         u32 pll, pll_min, pll_max, dat1, offset;
466         u32 win = 0x03, gwin = 0, gwinsize = 0;
467         u32 phy_setting = (u32)info->phy_setting;
468 
469 #ifdef CONFIG_ASPEED_PALLADIUM
470 	writel(0xc, phy_setting + 0x0000);
471 	return (1);
472 #endif
473         writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
474         writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
475 
476         while (gwin == 0) {
477                 while (!(win & 0x80)) {
478                         debug("Window = 0x%X\n", win);
479                         writel(win, phy_setting + 0x0000);
480 
481                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
482                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
483                         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
484                                 ast2600_sdrammc_fpga_set_pll(info);
485                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
486                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
487                         }
488 
489                         pll_min = 0xfff;
490                         pll_max = 0x0;
491                         pll = 0;
492                         while (pll_max > 0 || pll < 256) {
493                                 ast2600_sdrammc_fpga_set_pll(info);
494                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
495                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
496                                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
497                                         if (pll_min > pll) {
498                                                 pll_min = pll;
499                                         }
500                                         if (pll_max < pll) {
501                                                 pll_max = pll;
502                                         }
503                                         debug("%3d_(%3d:%3d)\n", pll, pll_min,
504                                                pll_max);
505                                 } else if (pll_max > 0) {
506                                         pll_min = pll_max - pll_min;
507                                         if (gwinsize < pll_min) {
508                                                 gwin = win;
509                                                 gwinsize = pll_min;
510                                         }
511                                         break;
512                                 }
513                                 pll += 1;
514                         }
515 
516                         if (gwin != 0 && pll_max == 0) {
517                                 break;
518                         }
519                         win = win << 1;
520                 }
521                 if (gwin == 0) {
522                         win = 0x7;
523                 }
524         }
525         debug("Set PLL Read Gating Window = %x\n", gwin);
526         writel(gwin, phy_setting + 0x0000);
527 
528         debug("PLL Read Window training\n");
529         pll_min = 0xfff;
530         pll_max = 0x0;
531 
532         debug("Search Window Start\n");
533         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
534         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
535         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
536                 ast2600_sdrammc_fpga_set_pll(info);
537                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
538                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
539         }
540 
541         debug("Search Window Margin\n");
542         pll = 0;
543         while (pll_max > 0 || pll < 256) {
544                 ast2600_sdrammc_fpga_set_pll(info);
545                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
546                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
547                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
548                         if (pll_min > pll) {
549                                 pll_min = pll;
550                         }
551                         if (pll_max < pll) {
552                                 pll_max = pll;
553                         }
554                         debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
555                 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
556                         break;
557                 } else if (pll_max > 0) {
558                         pll_min = 0xfff;
559                         pll_max = 0x0;
560                 }
561                 pll += 1;
562         }
563         if (pll_min < pll_max) {
564                 debug("PLL Read window = %d\n", (pll_max - pll_min));
565                 offset = (pll_max - pll_min) >> 1;
566                 pll_min = 0xfff;
567                 pll = 0;
568                 while (pll < (pll_min + offset)) {
569                         ast2600_sdrammc_fpga_set_pll(info);
570                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
571                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
572                         if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
573                                 if (pll_min > pll) {
574                                         pll_min = pll;
575                                 }
576                                 debug("%d\n", pll);
577                         } else {
578                                 pll_min = 0xfff;
579                                 pll_max = 0x0;
580                         }
581                         pll += 1;
582                 }
583                 return (1);
584         } else {
585                 debug("PLL Read window training fail\n");
586                 return (0);
587         }
588 }
589 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                           \
590 	  defined(CONFIG_ASPEED_PALLADIUM)" */
591 
592 /*
593  * Find out RAM size and save it in dram_info
594  *
595  * The procedure is taken from Aspeed SDK
596  */
597 static void ast2600_sdrammc_calc_size(struct dram_info *info)
598 {
599 	/* The controller supports 256/512/1024/2048 MB ram */
600 	size_t ram_size = SDRAM_MIN_SIZE;
601 	const int write_test_offset = 0x100000;
602 	u32 test_pattern = 0xdeadbeef;
603 	u32 cap_param = SDRAM_CONF_CAP_2048M;
604 	u32 refresh_timing_param = DDR4_TRFC;
605 	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
606 
607 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
608 	     ram_size >>= 1) {
609 		writel(test_pattern, write_addr_base + (ram_size >> 1));
610 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
611 	}
612 
613 	/* One last write to overwrite all wrapped values */
614 	writel(test_pattern, write_addr_base);
615 
616 	/* Reset the pattern and see which value was really written */
617 	test_pattern = 0xdeadbeef;
618 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
619 	     ram_size >>= 1) {
620 		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
621 			break;
622 
623 		--cap_param;
624 		refresh_timing_param >>= 8;
625 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
626 	}
627 
628 	clrsetbits_le32(&info->regs->ac_timing[1],
629 			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
630 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
631 			 << SDRAM_AC_TRFC_SHIFT));
632 
633 	info->info.base = CONFIG_SYS_SDRAM_BASE;
634 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
635 
636 	clrsetbits_le32(
637 	    &info->regs->config, SDRAM_CONF_CAP_MASK,
638 	    ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK));
639 }
640 
641 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
642 {
643         const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
644                                MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
645                                MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
646                                (0x1 << MCR34_ODT_EXT_SHIFT);
647 
648         /* init SDRAM-PHY only on real chip */
649 	ast2600_sdramphy_init(ast2600_sdramphy_config, info);
650         writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
651                &info->regs->power_ctrl);
652 	udelay(5);
653 	ast2600_sdramphy_kick_training(info);
654 	udelay(500);
655         writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
656 
657         writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
658         writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
659         writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
660         writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
661         writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
662         writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
663         writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
664                &info->regs->mode_setting_control);
665 
666 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
667 
668         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
669                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT),
670                &info->regs->refresh_timing);
671 #else
672         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
673                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
674                &info->regs->refresh_timing);
675 #endif
676 
677         /* wait self-refresh idle */
678         while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
679                 ;
680 
681 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
682         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
683                    SDRAM_REFRESH_ZQCS_EN |
684                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) |
685                    (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
686                &info->regs->refresh_timing);
687 #else
688         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
689                    SDRAM_REFRESH_ZQCS_EN |
690                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
691                    (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
692                &info->regs->refresh_timing);
693 #endif
694 
695         writel(power_ctrl, &info->regs->power_ctrl);
696 	udelay(500);
697 
698 #if defined(CONFIG_FPGA_ASPEED)
699         /* toggle Vref training */
700         setbits_le32(&info->regs->mr6_mode_setting, 0x80);
701         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
702                &info->regs->mode_setting_control);
703         clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
704         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
705                &info->regs->mode_setting_control);
706 #endif
707 	return 0;
708 }
709 
710 static void ast2600_sdrammc_unlock(struct dram_info *info)
711 {
712 	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
713 	while (!readl(&info->regs->protection_key))
714 		;
715 }
716 
717 static void ast2600_sdrammc_lock(struct dram_info *info)
718 {
719 	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
720 	while (readl(&info->regs->protection_key))
721 		;
722 }
723 
724 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
725 {
726 	int i;
727 
728         writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
729         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
730         writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
731                &regs->arbitration_ctrl);
732         writel(0xFFBBFFF4, &regs->req_limit_mask);
733 
734 	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
735                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
736 
737         writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
738 
739         /* FIXME: the sample code does NOT match the datasheet */
740         writel(0x07FFFFFF, &regs->ecc_range_ctrl);
741 
742         writel(0, &regs->ecc_test_ctrl);
743         writel(0, &regs->test_addr);
744         writel(0, &regs->test_fail_dq_bit);
745         writel(0, &regs->test_init_val);
746 
747         writel(0xFFFFFFFF, &regs->req_input_ctrl);
748         writel(0, &regs->req_high_pri_ctrl);
749 
750         udelay(600);
751 
752 #ifdef CONFIG_ASPEED_DDR4_DUALX8
753 	writel(0x37, &regs->config);
754 #else
755 	writel(0x17, &regs->config);
756 #endif
757 
758 	/* load controller setting */
759 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
760 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
761 
762 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
763 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
764 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
765 	writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
766 }
767 
768 static int ast2600_sdrammc_probe(struct udevice *dev)
769 {
770 	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
771 	struct ast2600_sdrammc_regs *regs = priv->regs;
772 	struct udevice *clk_dev;
773 	int ret;
774 	volatile uint32_t reg;
775 
776 	/* find SCU base address from clock device */
777 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
778                                           &clk_dev);
779 	if (ret) {
780 		debug("clock device not defined\n");
781 		return ret;
782 	}
783 
784 	priv->scu = devfdt_get_addr_ptr(clk_dev);
785 	if (IS_ERR(priv->scu)) {
786 		debug("%s(): can't get SCU\n", __func__);
787 		return PTR_ERR(priv->scu);
788 	}
789 
790 	if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) {
791 		debug("%s(): DDR SDRAM had been initialized\n", __func__);
792 		ast2600_sdrammc_calc_size(priv);
793 		return 0;
794 	}
795 
796 #ifdef AST2600_SDRAMMC_MANUAL_CLK
797 	reg = readl(priv->scu + AST_SCU_MPLL);
798 	reg &= ~(BIT(24) | GENMASK(22, 0));
799 	reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG);
800 	writel(reg, priv->scu + AST_SCU_MPLL);
801         writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
802 	udelay(100);
803 	reg &= ~(BIT(25) | BIT(23));
804 	writel(reg, priv->scu + AST_SCU_MPLL);
805 	while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)));
806 #else
807 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
808 	if (ret) {
809 		debug("DDR:No CLK\n");
810 		return ret;
811 	}
812 	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
813 #endif
814 
815 #if 0
816 	/* FIXME: enable the following code if reset-driver is ready */
817 	struct reset_ctl reset_ctl;
818 	ret = reset_get_by_index(dev, 0, &reset_ctl);
819 	if (ret) {
820 		debug("%s(): Failed to get reset signal\n", __func__);
821 		return ret;
822 	}
823 
824 	ret = reset_assert(&reset_ctl);
825 	if (ret) {
826 		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
827 		return ret;
828 	}
829 #endif
830 
831 	ast2600_sdrammc_unlock(priv);
832 	ast2600_sdrammc_common_init(regs);
833 
834 	if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) {
835 		debug("Unsupported SDRAM type: DDR3\n");
836 		return -EINVAL;
837 	} else {
838 		ast2600_sdrammc_init_ddr4(priv);
839 	}
840 
841 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
842         ast2600_sdrammc_search_read_window(priv);
843 #else
844 	/* make sure DDR-PHY is ready before access */
845 	do {
846 		reg = readl(priv->phy_status) & BIT(1);
847 	} while(reg == 0);
848 #endif
849 
850 	ast2600_sdramphy_show_status(priv);
851 	ast2600_sdrammc_calc_size(priv);
852 
853         if (0 != ast2600_sdrammc_test(priv)) {
854 		printf("%s: DDR4 init fail\n", __func__);
855 		return -EINVAL;
856 	}
857 
858 	writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK,
859 	       priv->scu + AST_SCU_HANDSHAKE);
860 
861 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
862 	ast2600_sdrammc_lock(priv);
863 	return 0;
864 }
865 
866 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
867 {
868 	struct dram_info *priv = dev_get_priv(dev);
869 
870 	priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
871 	priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
872 	priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
873 
874 	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
875 					  "clock-frequency", 0);
876 	if (!priv->clock_rate) {
877 		debug("DDR Clock Rate not defined\n");
878 		return -EINVAL;
879 	}
880 
881 	return 0;
882 }
883 
884 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
885 {
886 	struct dram_info *priv = dev_get_priv(dev);
887 
888 	*info = priv->info;
889 
890 	return 0;
891 }
892 
893 static struct ram_ops ast2600_sdrammc_ops = {
894 	.get_info = ast2600_sdrammc_get_info,
895 };
896 
897 static const struct udevice_id ast2600_sdrammc_ids[] = {
898 	{ .compatible = "aspeed,ast2600-sdrammc" },
899 	{ }
900 };
901 
902 U_BOOT_DRIVER(sdrammc_ast2600) = {
903 	.name = "aspeed_ast2600_sdrammc",
904 	.id = UCLASS_RAM,
905 	.of_match = ast2600_sdrammc_ids,
906 	.ops = &ast2600_sdrammc_ops,
907 	.ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
908 	.probe = ast2600_sdrammc_probe,
909 	.priv_auto_alloc_size = sizeof(struct dram_info),
910 };
911