xref: /openbmc/u-boot/drivers/ram/aspeed/sdram_ast2600.c (revision 090431c0c7fb8662afcb9936ab64f0b61f825b08)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012-2020  ASPEED Technology Inc.
4  *
5  * Copyright 2016 Google, Inc
6  */
7 
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <reset.h>
15 #include <asm/io.h>
16 #include <asm/arch/scu_ast2600.h>
17 #include <asm/arch/sdram_ast2600.h>
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <dt-bindings/clock/ast2600-clock.h>
21 #include "sdram_phy_ast2600.h"
22 
23 /* in order to speed up DRAM init time, write pre-defined values to registers
24  * directly */
25 #define AST2600_SDRAMMC_MANUAL_CLK
26 
27 /* register offset */
28 #define AST_SCU_FPGA_STATUS	0x004
29 #define AST_SCU_HANDSHAKE	0x100
30 #define AST_SCU_MPLL		0x220
31 #define AST_SCU_MPLL_EXT	0x224
32 #define AST_SCU_FPGA_PLL	0x400
33 #define AST_SCU_HW_STRAP	0x500
34 
35 
36 /* bit-field of AST_SCU_HW_STRAP */
37 #define SCU_HWSTRAP_VGAMEM_SHIFT	13
38 #define SCU_HWSTRAP_VGAMEM_MASK		GENMASK(14, 13)
39 #define SCU_HWSTRAP_DDR3		BIT(25)
40 
41 
42 /* bit-field of AST_SCU_HANDSHAKE */
43 #define SCU_SDRAM_INIT_READY_MASK	BIT(6)
44 #define SCU_SDRAM_INIT_BY_SOC_MASK	BIT(7)
45 
46 /* bit-field of AST_SCU_MPLL */
47 #define SCU_MPLL_RESET			BIT(25)
48 #define SCU_MPLL_BYPASS			BIT(24)
49 #define SCU_MPLL_TURN_OFF		BIT(23)
50 #define SCU_MPLL_FREQ_MASK		GENMASK(22, 0)
51 
52 #define SCU_MPLL_FREQ_400M		0x0008405F
53 #define SCU_MPLL_EXT_400M		0x00000031
54 //#define SCU_MPLL_FREQ_400M		0x0038007F
55 //#define SCU_MPLL_EXT_400M		0x0000003F
56 #define SCU_MPLL_FREQ_200M		0x0078007F
57 #define SCU_MPLL_EXT_200M		0x0000003F
58 
59 /* MPLL configuration */
60 #if defined(CONFIG_ASPEED_DDR4_800)
61 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_200M
62 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_200M
63 #elif defined(CONFIG_ASPEED_DDR4_1600)
64 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_400M
65 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_400M
66 #else
67 #error "undefined DDR4 target rate\n"
68 #endif
69 
70 /* AC timing and SDRAM mode registers */
71 #ifdef CONFIG_FPGA_ASPEED
72 /* mode register settings for FPGA are fixed */
73 #define DDR4_MR01_MODE		0x03010100
74 #define DDR4_MR23_MODE		0x00000000
75 #define DDR4_MR45_MODE		0x04C00000
76 #define DDR4_MR6_MODE		0x00000050
77 #define DDR4_TRFC_FPGA		0x17263434
78 
79 /* FPGA need for an additional initialization procedure: search read window */
80 #define SEARCH_RDWIN_ANCHOR_0   (CONFIG_SYS_SDRAM_BASE + 0x0000)
81 #define SEARCH_RDWIN_ANCHOR_1   (CONFIG_SYS_SDRAM_BASE + 0x0004)
82 #define SEARCH_RDWIN_PTRN_0     0x12345678
83 #define SEARCH_RDWIN_PTRN_1     0xaabbccdd
84 #define SEARCH_RDWIN_PTRN_SUM   0xbcf02355
85 #else
86 /* mode register setting for real chip are derived from the model GDDR4-1600 */
87 #define DDR4_MR01_MODE		0x03010510
88 #define DDR4_MR23_MODE		0x00000000
89 #define DDR4_MR45_MODE		0x04000000
90 #define DDR4_MR6_MODE           0x00000400
91 #define DDR4_TRFC_1600		0x467299f1
92 #define DDR4_TRFC_800		0x23394c78
93 #endif  /* end of "#ifdef CONFIG_FPGA_ASPEED" */
94 
95 #if defined(CONFIG_FPGA_ASPEED)
96 #define DDR4_TRFC			DDR4_TRFC_FPGA
97 #else
98 /* real chip setting */
99 #if defined(CONFIG_ASPEED_DDR4_1600)
100 #define DDR4_TRFC			DDR4_TRFC_1600
101 #define DDR4_PHY_TRAIN_TRFC		0xc30
102 #elif defined(CONFIG_ASPEED_DDR4_800)
103 #define DDR4_TRFC			DDR4_TRFC_800
104 #define DDR4_PHY_TRAIN_TRFC		0x618
105 #else
106 #error "undefined tRFC setting"
107 #endif	/* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
108 #endif	/* end of "#if defined(CONFIG_FPGA_ASPEED)" */
109 
110 /* supported SDRAM size */
111 #define SDRAM_SIZE_1KB		(1024U)
112 #define SDRAM_SIZE_1MB		(SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
113 #define SDRAM_MIN_SIZE		(256 * SDRAM_SIZE_1MB)
114 #define SDRAM_MAX_SIZE		(2048 * SDRAM_SIZE_1MB)
115 
116 
117 DECLARE_GLOBAL_DATA_PTR;
118 
119 /*
120  * Bandwidth configuration parameters for different SDRAM requests.
121  * These are hardcoded settings taken from Aspeed SDK.
122  */
123  #ifdef CONFIG_FPGA_ASPEED
124 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200,
125                                       0x00000140};
126 
127 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888,
128                                             0x88888888};
129 #else
130 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304,
131                                       0x00001240};
132 
133 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444,
134                                             0x44444444};
135 #endif
136 
137 struct dram_info {
138 	struct ram_info info;
139 	struct clk ddr_clk;
140 	struct ast2600_sdrammc_regs *regs;
141 	void __iomem *scu;
142 	struct ast2600_ddr_phy *phy;
143 	void __iomem *phy_setting;
144 	void __iomem *phy_status;
145 	ulong clock_rate;
146 };
147 
148 static void ast2600_sdramphy_kick_training(struct dram_info *info)
149 {
150 #ifndef CONFIG_FPGA_ASPEED
151         struct ast2600_sdrammc_regs *regs = info->regs;
152         u32 volatile data;
153 
154         writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
155 	udelay(5);
156         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
157 	udelay(1000);
158 
159 	while (1) {
160 		data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
161 		if (~data) {
162 			break;
163 		}
164 	}
165 
166 #if 0
167 	while (1) {
168 		data = readl(0x1e6e0400) & BIT(1);
169 		if (data) {
170 			break;
171 		}
172 	}
173 #endif
174 #endif
175 }
176 
177 /**
178  * @brief	load DDR-PHY configurations table to the PHY registers
179  * @param[in]	p_tbl - pointer to the configuration table
180  * @param[in]	info - pointer to the DRAM info struct
181  *
182  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
183  * system: one is in the SDRAM MC (memory controller) which is used in run
184  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
185  * training.  To make these two configurations align, we overwrite the DDR-PHY
186  * setting by the MC setting before DDR-PHY training.
187 */
188 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
189 {
190 #ifndef CONFIG_FPGA_ASPEED
191 	u32 reg_base = (u32)info->phy_setting;
192 	u32 addr = p_tbl[0];
193         u32 data;
194         int i = 1;
195 
196         debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base,
197                addr);
198 
199         /* load PHY configuration table into PHY-setting registers */
200         while (1) {
201                 if (addr < reg_base) {
202                         debug("invalid DDR-PHY addr: 0x%08x\n", addr);
203                         break;
204                 }
205                 data = p_tbl[i++];
206 
207                 if (DDR_PHY_TBL_END == data) {
208                         break;
209                 } else if (DDR_PHY_TBL_CHG_ADDR == data) {
210                         addr = p_tbl[i++];
211                 } else {
212                         writel(data, addr);
213                         addr += 4;
214                 }
215         }
216 
217 	data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
218 	data |= DDR4_PHY_TRAIN_TRFC;
219 	writel(data, info->phy_setting + 0x84);
220 
221 #ifdef CONFIG_ASPEED_DDR4_800
222 
223 	debug("Overwrite DDR-PHY MRS by MCR config\n");
224 	/* MR0 and MR1 */
225 	data = readl(&info->regs->mr01_mode_setting);
226 	data =
227 	    ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16);
228 	writel(data, reg_base + 0x58);
229 	debug("[%08x] 0x%08x\n", reg_base + 0x58, data);
230 
231 	/* MR2 and MR3 */
232 	data = readl(&info->regs->mr23_mode_setting);
233 	writel(data, reg_base + 0x54);
234 	debug("[%08x] 0x%08x\n", reg_base + 0x54, data);
235 
236 	/* MR4 and MR5 */
237 	data = readl(&info->regs->mr45_mode_setting);
238 	writel(data, reg_base + 0x5c);
239 	debug("[%08x] 0x%08x\n", reg_base + 0x5c, data);
240 
241 	/* MR6 */
242 	data = readl(&info->regs->mr6_mode_setting);
243 	writel(data, reg_base + 0x60);
244 	debug("[%08x] 0x%08x\n", reg_base + 0x60, data);
245 #endif
246 #endif
247 }
248 
249 static void ast2600_sdramphy_show_status(struct dram_info *info)
250 {
251 #ifndef CONFIG_FPGA_ASPEED
252         u32 value, tmp;
253         u32 reg_base = (u32)info->phy_status;
254 
255 	debug("\nSDRAM PHY training report:\n");
256 	/* training status */
257         value = readl(reg_base + 0x00);
258 	debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
259         if (value & BIT(3)) {
260                 debug("\tinitial PVT calibration fail\n");
261         }
262         if (value & BIT(5)) {
263                 debug("\truntime calibration fail\n");
264         }
265 
266 	/* PU & PD */
267 	value = readl(reg_base + 0x30);
268 	debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
269         debug("  PU = 0x%02x\n", value & 0xff);
270         debug("  PD = 0x%02x\n", (value >> 16) & 0xff);
271 
272 	/* read eye window */
273         value = readl(reg_base + 0x68);
274 	debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
275 	debug("  rising edge of read data eye training pass window\n");
276 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
277 	debug("    B0:%d%%\n", tmp);
278 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
279         debug("    B1:%d%%\n", tmp);
280 
281 	value = readl(reg_base + 0xC8);
282 	debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
283 	debug("  falling edge of read data eye training pass window\n");
284 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
285 	debug("    B0:%d%%\n", tmp);
286 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
287         debug("    B1:%d%%\n", tmp);
288 
289         /* write eye window */
290         value = readl(reg_base + 0x7c);
291 	debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
292 	debug("  rising edge of write data eye training pass window\n");
293 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
294 	debug("    B0:%d%%\n", tmp);
295 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
296         debug("    B1:%d%%\n", tmp);
297 
298 	/* read Vref training result */
299         value = readl(reg_base + 0x88);
300 	debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
301         debug("  read Vref training result\n");
302 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
303 	debug("    B0:%d%%\n", tmp);
304 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
305         debug("    B1:%d%%\n", tmp);
306 
307         /* write Vref training result */
308         value = readl(reg_base + 0x90);
309 	debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
310 	tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127;
311         debug("  write Vref training result = %d%%\n", tmp);
312 
313         /* gate train */
314 	value = readl(reg_base + 0x50);
315 	debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
316 	debug("  gate training pass window\n");
317 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
318 	debug("    module 0: %d.%03d\n", (value >> 8) & 0xff, tmp);
319         tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255;
320 	debug("    module 1: %d.%03d\n", (value >> 24) & 0xff, tmp);
321 #endif
322 }
323 
324 #define MC_TEST_PATTERN_N 8
325 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
326     0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
327     0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253};
328 
329 #define DRAM_MapAdr	81000000
330 #define TIMEOUT_DRAM	5000000
331 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
332 {
333 	unsigned int data;
334 	unsigned int timeout = 0;
335 	struct ast2600_sdrammc_regs *regs = info->regs;
336 
337 	writel(0, &regs->ecc_test_ctrl);
338 	if (mode == 0) {
339 		writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl);
340 	} else {
341 		writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl);
342 	}
343 
344 	do {
345 		data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12);
346 
347 		if (data & BIT(13))
348 			return (0);
349 
350 		if (++timeout > TIMEOUT_DRAM) {
351 			printf("Timeout!!\n");
352 			writel(0, &regs->ecc_test_ctrl);
353 
354 			return (0);
355 		}
356 	} while (!data);
357 
358 	writel(0, &regs->ecc_test_ctrl);
359 
360 	return (1);
361 }
362 
363 int ast2600_sdrammc_cbr_test(struct dram_info *info)
364 {
365 	struct ast2600_sdrammc_regs *regs = info->regs;
366 	u32 i;
367 
368 	writel((DRAM_MapAdr | 0x7fffff), &regs->test_addr);
369 
370 	/* single */
371 	for (i=0; i<8; i++) {
372   		if(!ast2600_sdrammc_dg_test(info, i, 0))   return(0);
373 	}
374 
375 	/* burst */
376 	for (i=0; i<8; i++) {
377   		if(!ast2600_sdrammc_dg_test(info, i, i))   return(0);
378 	}
379 
380 	return(1);
381 }
382 
383 static int ast2600_sdrammc_test(struct dram_info *info)
384 {
385 	struct ast2600_sdrammc_regs *regs = info->regs;
386 
387 	u32 pass_cnt = 0;
388 	u32 fail_cnt = 0;
389 	u32 target_cnt = 4;
390 	u32 test_cnt = 0;
391 	u32 pattern;
392 	u32 i = 0;
393 	bool finish = false;
394 
395 	debug("sdram mc test:\n");
396 	while (finish == false) {
397 		pattern = as2600_sdrammc_test_pattern[i++];
398 		i = i % MC_TEST_PATTERN_N;
399 		debug("  pattern = %08X : ",pattern);
400 		writel(pattern, regs->test_init_val);
401 
402 		if (!ast2600_sdrammc_cbr_test(info)) {
403 			debug("fail\n");
404 			fail_cnt++;
405 		} else {
406 			debug("pass\n");
407 			pass_cnt++;
408 		}
409 
410 		if (++test_cnt == target_cnt) {
411 			finish = true;
412 		}
413 	}
414 	debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt,
415 	       target_cnt);
416 	return fail_cnt;
417 }
418 
419 /**
420  * scu500[14:13]
421  * 	2b'00: VGA memory size = 8MB * 2^((0+1) & 0x3) = 16MB
422  * 	2b'01: VGA memory size = 8MB * 2^((1+1) & 0x3) = 32MB
423  * 	2b'10: VGA memory size = 8MB * 2^((2+1) & 0x3) = 64MB
424  * 	2b'11: VGA memory size = 8MB * 2^((3+1) & 0x3) = 8MB
425  *
426  * mcr04[3:2]
427  * 	2b'00: VGA memory size = 8MB
428  * 	2b'01: VGA memory size = 16MB
429  * 	2b'10: VGA memory size = 32MB
430  * 	2b'11: VGA memory size = 64MB
431 */
432 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
433 {
434         u32 vga_hwconf;
435         size_t vga_mem_size_base = 8 * 1024 * 1024;
436 
437 	vga_hwconf =
438 	    (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >>
439 	    SCU_HWSTRAP_VGAMEM_SHIFT;
440 
441 	vga_hwconf = (vga_hwconf + 1) & 0x3;
442 
443 	clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK,
444 			((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) &
445 			 SDRAM_CONF_VGA_SIZE_MASK));
446 
447 	return vga_mem_size_base << vga_hwconf;
448 }
449 #ifdef CONFIG_FPGA_ASPEED
450 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
451 {
452         u32 data;
453         u32 scu_base = (u32)info->scu;
454 
455         writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
456 
457         do {
458                 data = readl(scu_base + AST_SCU_FPGA_STATUS);
459         } while (!(data & 0x100));
460 
461         writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
462 }
463 
464 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
465 {
466         u32 pll, pll_min, pll_max, dat1, offset;
467         u32 win = 0x03, gwin = 0, gwinsize = 0;
468         u32 phy_setting = (u32)info->phy_setting;
469 
470         writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
471         writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
472 
473         while (gwin == 0) {
474                 while (!(win & 0x80)) {
475                         debug("Window = 0x%X\n", win);
476                         writel(win, phy_setting + 0x0000);
477 
478                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
479                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
480                         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
481                                 ast2600_sdrammc_fpga_set_pll(info);
482                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
483                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
484                         }
485 
486                         pll_min = 0xfff;
487                         pll_max = 0x0;
488                         pll = 0;
489                         while (pll_max > 0 || pll < 256) {
490                                 ast2600_sdrammc_fpga_set_pll(info);
491                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
492                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
493                                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
494                                         if (pll_min > pll) {
495                                                 pll_min = pll;
496                                         }
497                                         if (pll_max < pll) {
498                                                 pll_max = pll;
499                                         }
500                                         debug("%3d_(%3d:%3d)\n", pll, pll_min,
501                                                pll_max);
502                                 } else if (pll_max > 0) {
503                                         pll_min = pll_max - pll_min;
504                                         if (gwinsize < pll_min) {
505                                                 gwin = win;
506                                                 gwinsize = pll_min;
507                                         }
508                                         break;
509                                 }
510                                 pll += 1;
511                         }
512 
513                         if (gwin != 0 && pll_max == 0) {
514                                 break;
515                         }
516                         win = win << 1;
517                 }
518                 if (gwin == 0) {
519                         win = 0x7;
520                 }
521         }
522         debug("Set PLL Read Gating Window = %x\n", gwin);
523         writel(gwin, phy_setting + 0x0000);
524 
525         debug("PLL Read Window training\n");
526         pll_min = 0xfff;
527         pll_max = 0x0;
528 
529         debug("Search Window Start\n");
530         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
531         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
532         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
533                 ast2600_sdrammc_fpga_set_pll(info);
534                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
535                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
536         }
537 
538         debug("Search Window Margin\n");
539         pll = 0;
540         while (pll_max > 0 || pll < 256) {
541                 ast2600_sdrammc_fpga_set_pll(info);
542                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
543                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
544                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
545                         if (pll_min > pll) {
546                                 pll_min = pll;
547                         }
548                         if (pll_max < pll) {
549                                 pll_max = pll;
550                         }
551                         debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
552                 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
553                         break;
554                 } else if (pll_max > 0) {
555                         pll_min = 0xfff;
556                         pll_max = 0x0;
557                 }
558                 pll += 1;
559         }
560         if (pll_min < pll_max) {
561                 debug("PLL Read window = %d\n", (pll_max - pll_min));
562                 offset = (pll_max - pll_min) >> 1;
563                 pll_min = 0xfff;
564                 pll = 0;
565                 while (pll < (pll_min + offset)) {
566                         ast2600_sdrammc_fpga_set_pll(info);
567                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
568                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
569                         if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
570                                 if (pll_min > pll) {
571                                         pll_min = pll;
572                                 }
573                                 debug("%d\n", pll);
574                         } else {
575                                 pll_min = 0xfff;
576                                 pll_max = 0x0;
577                         }
578                         pll += 1;
579                 }
580                 return (1);
581         } else {
582                 debug("PLL Read window training fail\n");
583                 return (0);
584         }
585 }
586 #endif  /* end of "#ifdef CONFIG_FPGA_ASPEED" */
587 
588 /*
589  * Find out RAM size and save it in dram_info
590  *
591  * The procedure is taken from Aspeed SDK
592  */
593 static void ast2600_sdrammc_calc_size(struct dram_info *info)
594 {
595 	/* The controller supports 256/512/1024/2048 MB ram */
596 	size_t ram_size = SDRAM_MIN_SIZE;
597 	const int write_test_offset = 0x100000;
598 	u32 test_pattern = 0xdeadbeef;
599 	u32 cap_param = SDRAM_CONF_CAP_2048M;
600 	u32 refresh_timing_param = DDR4_TRFC;
601 	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
602 
603 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
604 	     ram_size >>= 1) {
605 		writel(test_pattern, write_addr_base + (ram_size >> 1));
606 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
607 	}
608 
609 	/* One last write to overwrite all wrapped values */
610 	writel(test_pattern, write_addr_base);
611 
612 	/* Reset the pattern and see which value was really written */
613 	test_pattern = 0xdeadbeef;
614 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
615 	     ram_size >>= 1) {
616 		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
617 			break;
618 
619 		--cap_param;
620 		refresh_timing_param >>= 8;
621 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
622 	}
623 
624 	clrsetbits_le32(&info->regs->ac_timing[1],
625 			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
626 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
627 			 << SDRAM_AC_TRFC_SHIFT));
628 
629 	info->info.base = CONFIG_SYS_SDRAM_BASE;
630 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
631 
632 	clrsetbits_le32(
633 	    &info->regs->config, SDRAM_CONF_CAP_MASK,
634 	    ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK));
635 }
636 
637 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
638 {
639         const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
640                                MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
641                                MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
642                                (0x1 << MCR34_ODT_EXT_SHIFT);
643 
644         /* init SDRAM-PHY only on real chip */
645 	ast2600_sdramphy_init(ast2600_sdramphy_config, info);
646         writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
647                &info->regs->power_ctrl);
648 	udelay(5);
649 	ast2600_sdramphy_kick_training(info);
650 	udelay(500);
651         writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
652 
653         writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
654         writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
655         writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
656         writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
657         writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
658         writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
659         writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
660                &info->regs->mode_setting_control);
661 
662 #ifdef CONFIG_FPGA_ASPEED
663         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
664                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT),
665                &info->regs->refresh_timing);
666 #else
667         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
668                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
669                &info->regs->refresh_timing);
670 #endif
671 
672         /* wait self-refresh idle */
673         while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
674                 ;
675 
676 #ifdef CONFIG_FPGA_ASPEED
677         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
678                    SDRAM_REFRESH_ZQCS_EN |
679                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) |
680                    (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
681                &info->regs->refresh_timing);
682 #else
683         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
684                    SDRAM_REFRESH_ZQCS_EN |
685                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
686                    (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
687                &info->regs->refresh_timing);
688 #endif
689 
690         writel(power_ctrl, &info->regs->power_ctrl);
691 	udelay(500);
692 
693 #ifdef CONFIG_FPGA_ASPEED
694         /* toggle Vref training */
695         setbits_le32(&info->regs->mr6_mode_setting, 0x80);
696         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
697                &info->regs->mode_setting_control);
698         clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
699         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
700                &info->regs->mode_setting_control);
701 #endif
702 	return 0;
703 }
704 
705 static void ast2600_sdrammc_unlock(struct dram_info *info)
706 {
707 	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
708 	while (!readl(&info->regs->protection_key))
709 		;
710 }
711 
712 static void ast2600_sdrammc_lock(struct dram_info *info)
713 {
714 	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
715 	while (readl(&info->regs->protection_key))
716 		;
717 }
718 
719 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
720 {
721 	int i;
722 
723         writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
724         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
725         writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
726                &regs->arbitration_ctrl);
727         writel(0xFFBBFFF4, &regs->req_limit_mask);
728 
729 	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
730                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
731 
732         writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
733 
734         /* FIXME: the sample code does NOT match the datasheet */
735         writel(0x07FFFFFF, &regs->ecc_range_ctrl);
736 
737         writel(0, &regs->ecc_test_ctrl);
738         writel(0, &regs->test_addr);
739         writel(0, &regs->test_fail_dq_bit);
740         writel(0, &regs->test_init_val);
741 
742         writel(0xFFFFFFFF, &regs->req_input_ctrl);
743         writel(0, &regs->req_high_pri_ctrl);
744 
745         udelay(600);
746 
747 #ifdef CONFIG_ASPEED_DDR4_DUALX8
748 	writel(0x37, &regs->config);
749 #else
750 	writel(0x17, &regs->config);
751 #endif
752 
753 	/* load controller setting */
754 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
755 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
756 
757 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
758 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
759 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
760 	writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
761 }
762 
763 static int ast2600_sdrammc_probe(struct udevice *dev)
764 {
765 	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
766 	struct ast2600_sdrammc_regs *regs = priv->regs;
767 	struct udevice *clk_dev;
768 	int ret;
769 	uint32_t reg;
770 
771 	/* find SCU base address from clock device */
772 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
773                                           &clk_dev);
774 	if (ret) {
775 		debug("clock device not defined\n");
776 		return ret;
777 	}
778 
779 	priv->scu = devfdt_get_addr_ptr(clk_dev);
780 	if (IS_ERR(priv->scu)) {
781 		debug("%s(): can't get SCU\n", __func__);
782 		return PTR_ERR(priv->scu);
783 	}
784 
785 	if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) {
786 		debug("%s(): DDR SDRAM had been initialized\n", __func__);
787 		ast2600_sdrammc_calc_size(priv);
788 		return 0;
789 	}
790 
791 #ifdef AST2600_SDRAMMC_MANUAL_CLK
792 	reg = readl(priv->scu + AST_SCU_MPLL);
793 	reg &= ~(BIT(24) | GENMASK(22, 0));
794 	reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG);
795 	writel(reg, priv->scu + AST_SCU_MPLL);
796         writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
797 	udelay(100);
798 	reg &= ~(BIT(25) | BIT(23));
799 	writel(reg, priv->scu + AST_SCU_MPLL);
800 	while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)));
801 #else
802 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
803 	if (ret) {
804 		debug("DDR:No CLK\n");
805 		return ret;
806 	}
807 	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
808 #endif
809 
810 #if 0
811 	/* FIXME: enable the following code if reset-driver is ready */
812 	struct reset_ctl reset_ctl;
813 	ret = reset_get_by_index(dev, 0, &reset_ctl);
814 	if (ret) {
815 		debug("%s(): Failed to get reset signal\n", __func__);
816 		return ret;
817 	}
818 
819 	ret = reset_assert(&reset_ctl);
820 	if (ret) {
821 		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
822 		return ret;
823 	}
824 #endif
825 
826 	ast2600_sdrammc_unlock(priv);
827 	ast2600_sdrammc_common_init(regs);
828 
829 	if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) {
830 		debug("Unsupported SDRAM type: DDR3\n");
831 		return -EINVAL;
832 	} else {
833 		ast2600_sdrammc_init_ddr4(priv);
834 	}
835 
836 #ifdef CONFIG_FPGA_ASPEED
837         ast2600_sdrammc_search_read_window(priv);
838 #endif
839 
840 #ifndef DEBUG
841 	mdelay(10);
842 #endif
843 	ast2600_sdramphy_show_status(priv);
844 	ast2600_sdrammc_calc_size(priv);
845 
846         if (0 != ast2600_sdrammc_test(priv)) {
847 		printf("%s: DDR4 init fail\n", __func__);
848 		return -EINVAL;
849 	}
850 
851 	writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK,
852 	       priv->scu + AST_SCU_HANDSHAKE);
853 
854 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
855 	ast2600_sdrammc_lock(priv);
856 	return 0;
857 }
858 
859 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
860 {
861 	struct dram_info *priv = dev_get_priv(dev);
862 
863 	priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
864 	priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
865 	priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
866 
867 	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
868 					  "clock-frequency", 0);
869 	if (!priv->clock_rate) {
870 		debug("DDR Clock Rate not defined\n");
871 		return -EINVAL;
872 	}
873 
874 	return 0;
875 }
876 
877 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
878 {
879 	struct dram_info *priv = dev_get_priv(dev);
880 
881 	*info = priv->info;
882 
883 	return 0;
884 }
885 
886 static struct ram_ops ast2600_sdrammc_ops = {
887 	.get_info = ast2600_sdrammc_get_info,
888 };
889 
890 static const struct udevice_id ast2600_sdrammc_ids[] = {
891 	{ .compatible = "aspeed,ast2600-sdrammc" },
892 	{ }
893 };
894 
895 U_BOOT_DRIVER(sdrammc_ast2600) = {
896 	.name = "aspeed_ast2600_sdrammc",
897 	.id = UCLASS_RAM,
898 	.of_match = ast2600_sdrammc_ids,
899 	.ops = &ast2600_sdrammc_ops,
900 	.ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
901 	.probe = ast2600_sdrammc_probe,
902 	.priv_auto_alloc_size = sizeof(struct dram_info),
903 };
904